From 3a660c933af67d21d5f3f4493eccfd11acda6556 Mon Sep 17 00:00:00 2001 From: Samuel Antao Date: Tue, 17 Mar 2015 19:31:19 +0000 Subject: [PATCH] Add assertion to detect invalid registers in the PowerPC MC instruction lowering. We have observed that noreg was being generated due to a bug in FastIsel and was not being detected during emission. It happens that in the Asm emission there is an assertion that detects this in getRegisterName() from the tbl-generated file PPCGenAsmWriter.inc. However, when emitting an Obj file, invalid registers can be emitted given that no check are made in getBinaryCodeFromInstr() from PPCGenMCCodeEmitter.inc. In order to cover all cases this adds an assertion for reg operands in LowerPPCMachineInstrToMCInst. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@232525 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/PowerPC/PPCMCInstLower.cpp | 3 +++ 1 file changed, 3 insertions(+) diff --git a/lib/Target/PowerPC/PPCMCInstLower.cpp b/lib/Target/PowerPC/PPCMCInstLower.cpp index 819738b2062..0965cb35508 100644 --- a/lib/Target/PowerPC/PPCMCInstLower.cpp +++ b/lib/Target/PowerPC/PPCMCInstLower.cpp @@ -184,6 +184,9 @@ void llvm::LowerPPCMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI, llvm_unreachable("unknown operand type"); case MachineOperand::MO_Register: assert(!MO.getSubReg() && "Subregs should be eliminated!"); + assert(MO.getReg() > PPC::NoRegister && + MO.getReg() < PPC::NUM_TARGET_REGS && + "Invalid register for this target!"); MCOp = MCOperand::CreateReg(MO.getReg()); break; case MachineOperand::MO_Immediate: -- 2.34.1