From 3b79f0ccc33b68912c296c6151bd83a643fb9fc7 Mon Sep 17 00:00:00 2001 From: Vasileios Kalintiris Date: Thu, 30 Jul 2015 11:51:44 +0000 Subject: [PATCH] [mips][FastISel] Apply only zero-extension to constants prior to their materialization. Summary: Previously, we would sign-extend non-boolean negative constants and zero-extend otherwise. This was problematic for PHI instructions with negative values that had a type with bitwidth less than that of the register used for materialization. More specifically, ComputePHILiveOutRegInfo() assumes the constants present in a PHI node are zero extended in their container and afterwards deduces the known bits. For example, previously we would materialize an i16 -4 with the following instruction: addiu $r, $zero, -4 The register would end-up with the 32-bit 2's complement representation of -4. However, ComputePHILiveOutRegInfo() would generate a constant with the upper 16-bits set to zero. The SelectionDAG builder would use that information to generate an AssertZero node that would remove any subsequent trunc & zero_extend nodes. In theory, we should modify ComputePHILiveOutRegInfo() to consult target-specific hooks about the way they prefer to materialize the given constants. However, git-blame reports that this specific code has not been touched since 2011 and it seems to be working well for every target so far. Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11592 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243636 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Mips/MipsFastISel.cpp | 7 +------ test/CodeGen/Mips/Fast-ISel/logopm.ll | 20 ++++++++++---------- test/CodeGen/Mips/Fast-ISel/simplestorei.ll | 7 ++++--- 3 files changed, 15 insertions(+), 19 deletions(-) diff --git a/lib/Target/Mips/MipsFastISel.cpp b/lib/Target/Mips/MipsFastISel.cpp index 2c88950f8fd..bdeb94942ff 100644 --- a/lib/Target/Mips/MipsFastISel.cpp +++ b/lib/Target/Mips/MipsFastISel.cpp @@ -290,12 +290,7 @@ unsigned MipsFastISel::materializeInt(const Constant *C, MVT VT) { return 0; const TargetRegisterClass *RC = &Mips::GPR32RegClass; const ConstantInt *CI = cast(C); - int64_t Imm; - if ((VT != MVT::i1) && CI->isNegative()) - Imm = CI->getSExtValue(); - else - Imm = CI->getZExtValue(); - return materialize32BitInt(Imm, RC); + return materialize32BitInt(CI->getZExtValue(), RC); } unsigned MipsFastISel::materialize32BitInt(int64_t Imm, diff --git a/test/CodeGen/Mips/Fast-ISel/logopm.ll b/test/CodeGen/Mips/Fast-ISel/logopm.ll index 0f0c3bf9e1d..42a1c43d893 100644 --- a/test/CodeGen/Mips/Fast-ISel/logopm.ll +++ b/test/CodeGen/Mips/Fast-ISel/logopm.ll @@ -283,8 +283,8 @@ entry: ; CHECK-DAG: lw $[[UC_ADDR:[0-9]+]], %got(uc)($[[REG_GP]]) ; CHECK-DAG: lw $[[UC1_ADDR:[0-9]+]], %got(uc1)($[[REG_GP]]) ; CHECK-DAG: lbu $[[UC1:[0-9]+]], 0($[[UC1_ADDR]]) -; CHECK-DAG: addiu $[[CONST_Neg89:[0-9]+]], $zero, -89 -; CHECK-DAG: and $[[RES:[0-9]+]], $[[UC1]], $[[CONST_Neg89]] +; CHECK-DAG: addiu $[[CONST_167:[0-9]+]], $zero, 167 +; CHECK-DAG: and $[[RES:[0-9]+]], $[[UC1]], $[[CONST_167]] ; CHECK: sb $[[RES]], 0($[[UC_ADDR]]) ; CHECK: .end andUc1 ret void @@ -345,8 +345,8 @@ entry: ; CHECK-DAG: lw $[[UC_ADDR:[0-9]+]], %got(uc)($[[REG_GP]]) ; CHECK-DAG: lw $[[UC1_ADDR:[0-9]+]], %got(uc1)($[[REG_GP]]) ; CHECK-DAG: lbu $[[UC1:[0-9]+]], 0($[[UC1_ADDR]]) -; CHECK-DAG: addiu $[[CONST_neg18:[0-9]+]], $zero, -18 -; CHECK-DAG: or $[[RES:[0-9]+]], $[[UC1]], $[[CONST_neg18]] +; CHECK-DAG: addiu $[[CONST_238:[0-9]+]], $zero, 238 +; CHECK-DAG: or $[[RES:[0-9]+]], $[[UC1]], $[[CONST_238]] ; CHECK: sb $[[RES]], 0($[[UC_ADDR]]) ; CHECK: .end orUc1 ret void @@ -469,8 +469,8 @@ entry: ; CHECK-DAG: lw $[[US_ADDR:[0-9]+]], %got(us)($[[REG_GP]]) ; CHECK-DAG: lw $[[US1_ADDR:[0-9]+]], %got(us1)($[[REG_GP]]) ; CHECK-DAG: lhu $[[US1:[0-9]+]], 0($[[US1_ADDR]]) -; CHECK-DAG: addiu $[[CONST_Neg4185:[0-9]+]], $zero, -4185 -; CHECK-DAG: and $[[RES:[0-9]+]], $[[US1]], $[[CONST_Neg4185]] +; CHECK-DAG: ori $[[CONST_61351:[0-9]+]], $zero, 61351 +; CHECK-DAG: and $[[RES:[0-9]+]], $[[US1]], $[[CONST_61351]] ; CHECK: sh $[[RES]], 0($[[US_ADDR]]) ; CHECK: .end andUs1 ret void @@ -520,8 +520,8 @@ entry: ; CHECK-DAG: lw $[[US_ADDR:[0-9]+]], %got(us)($[[REG_GP]]) ; CHECK-DAG: lw $[[US1_ADDR:[0-9]+]], %got(us1)($[[REG_GP]]) ; CHECK-DAG: lhu $[[US1:[0-9]+]], 0($[[US1_ADDR]]) -; CHECK-DAG: addiu $[[CONST_neg4591:[0-9]+]], $zero, -4591 -; CHECK-DAG: or $[[RES:[0-9]+]], $[[US1]], $[[CONST_neg4591]] +; CHECK-DAG: ori $[[CONST_60945:[0-9]+]], $zero, 60945 +; CHECK-DAG: or $[[RES:[0-9]+]], $[[US1]], $[[CONST_60945]] ; CHECK: sh $[[RES]], 0($[[US_ADDR]]) ; CHECK: .end orUs1 ret void @@ -583,8 +583,8 @@ entry: ; CHECK-DAG: lw $[[US_ADDR:[0-9]+]], %got(us)($[[REG_GP]]) ; CHECK-DAG: lw $[[US1_ADDR:[0-9]+]], %got(us1)($[[REG_GP]]) ; CHECK-DAG: lhu $[[US1:[0-9]+]], 0($[[US1_ADDR]]) -; CHECK-DAG: addiu $[[CONST_Neg5512:[0-9]+]], $zero, -5512 -; CHECK-DAG: xor $[[RES:[0-9]+]], $[[US1]], $[[CONST_Neg5512]] +; CHECK-DAG: ori $[[CONST_60024:[0-9]+]], $zero, 60024 +; CHECK-DAG: xor $[[RES:[0-9]+]], $[[US1]], $[[CONST_60024]] ; CHECK: sh $[[RES]], 0($[[US_ADDR]]) ; CHECK: .end xorUs1 ret void diff --git a/test/CodeGen/Mips/Fast-ISel/simplestorei.ll b/test/CodeGen/Mips/Fast-ISel/simplestorei.ll index 83ccae0b1de..d8c03f22f9b 100644 --- a/test/CodeGen/Mips/Fast-ISel/simplestorei.ll +++ b/test/CodeGen/Mips/Fast-ISel/simplestorei.ll @@ -22,9 +22,10 @@ define void @si2_2() #0 { entry: store i32 -32768, i32* @ijk, align 4 ; CHECK: .ent si2_2 -; CHECK: addiu $[[REG1:[0-9]+]], $zero, -32768 -; CHECK: lw $[[REG2:[0-9]+]], %got(ijk)(${{[0-9]+}}) -; CHECK: sw $[[REG1]], 0($[[REG2]]) +; CHECK: lui $[[REG1:[0-9]+]], 65535 +; CHECK: ori $[[REG2:[0-9]+]], $[[REG1]], 32768 +; CHECK: lw $[[REG3:[0-9]+]], %got(ijk)(${{[0-9]+}}) +; CHECK: sw $[[REG2]], 0($[[REG3]]) ret void } -- 2.34.1