From 3d45a853db014fdddcdb79424e663dfed5eccbc7 Mon Sep 17 00:00:00 2001
From: Dan Gohman <gohman@apple.com>
Date: Thu, 3 Sep 2009 22:53:57 +0000
Subject: [PATCH] LLVM currently represents floating-point negation as -0.0 -
 x. Fix FastISel to recognize this pattern and emit a floating-point negation
 using xor.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80963 91177308-0d34-0410-b5e6-96231b3b80d8
---
 include/llvm/CodeGen/FastISel.h       |  2 ++
 lib/CodeGen/SelectionDAG/FastISel.cpp | 23 +++++++++++++++++++++++
 test/CodeGen/X86/fast-isel-fneg.ll    | 15 +++++++++++++++
 3 files changed, 40 insertions(+)
 create mode 100644 test/CodeGen/X86/fast-isel-fneg.ll

diff --git a/include/llvm/CodeGen/FastISel.h b/include/llvm/CodeGen/FastISel.h
index b2cc94db4e5..6cd551976c4 100644
--- a/include/llvm/CodeGen/FastISel.h
+++ b/include/llvm/CodeGen/FastISel.h
@@ -300,6 +300,8 @@ protected:
 private:
   bool SelectBinaryOp(User *I, ISD::NodeType ISDOpcode);
 
+  bool SelectFNeg(User *I);
+
   bool SelectGetElementPtr(User *I);
 
   bool SelectCall(User *I);
diff --git a/lib/CodeGen/SelectionDAG/FastISel.cpp b/lib/CodeGen/SelectionDAG/FastISel.cpp
index 5b4c79a9fd9..f0c70861843 100644
--- a/lib/CodeGen/SelectionDAG/FastISel.cpp
+++ b/lib/CodeGen/SelectionDAG/FastISel.cpp
@@ -608,6 +608,26 @@ FastISel::FastEmitBranch(MachineBasicBlock *MSucc) {
   MBB->addSuccessor(MSucc);
 }
 
+/// SelectFNeg - Emit an FNeg operation.
+///
+bool
+FastISel::SelectFNeg(User *I) {
+  unsigned OpReg = getRegForValue(BinaryOperator::getFNegArgument(I));
+  if (OpReg == 0) return false;
+
+  // Twiddle the sign bit with xor.
+  EVT VT = TLI.getValueType(I->getType());
+  if (VT.getSizeInBits() > 64) return false;
+  unsigned ResultReg = FastEmit_ri_(VT.getSimpleVT(), ISD::XOR, OpReg,
+                                    UINT64_C(1) << (VT.getSizeInBits()-1),
+                                    VT.getSimpleVT());
+  if (ResultReg == 0)
+    return false;
+
+  UpdateValueMap(I, ResultReg);
+  return true;
+}
+
 bool
 FastISel::SelectOperator(User *I, unsigned Opcode) {
   switch (Opcode) {
@@ -618,6 +638,9 @@ FastISel::SelectOperator(User *I, unsigned Opcode) {
   case Instruction::Sub:
     return SelectBinaryOp(I, ISD::SUB);
   case Instruction::FSub:
+    // FNeg is currently represented in LLVM IR as a special case of FSub.
+    if (BinaryOperator::isFNeg(I))
+      return SelectFNeg(I);
     return SelectBinaryOp(I, ISD::FSUB);
   case Instruction::Mul:
     return SelectBinaryOp(I, ISD::MUL);
diff --git a/test/CodeGen/X86/fast-isel-fneg.ll b/test/CodeGen/X86/fast-isel-fneg.ll
new file mode 100644
index 00000000000..41b288ba1de
--- /dev/null
+++ b/test/CodeGen/X86/fast-isel-fneg.ll
@@ -0,0 +1,15 @@
+; RUN: llvm-as < %s | llc -fast-isel -march=x86-64 | FileCheck %s
+
+; CHECK: doo:
+; CHECK: xorpd
+define double @doo(double %x) nounwind {
+  %y = fsub double -0.0, %x
+  ret double %y
+}
+
+; CHECK: foo:
+; CHECK: xorps
+define float @foo(float %x) nounwind {
+  %y = fsub float -0.0, %x
+  ret float %y
+}
-- 
2.34.1