From 3e6193627508f100fe58a289683f8ef44eef66eb Mon Sep 17 00:00:00 2001 From: Tang Yun ping Date: Thu, 6 Apr 2017 15:25:12 +0800 Subject: [PATCH] clk: rockchip: optimizing ddrclk_scpi_recalc_rate behavior Cat ddr frequency from rockchip_ddrclk_scpi_set_rate prior to rockchip_ddrclk_scpi_recalc_rate, to optimizing running time and reduce SCPI APIs usage rate. Change-Id: Iba31d33a5920816b1cc230f639ea3a9503d451c8 Signed-off-by: Tang Yun ping --- drivers/clk/rockchip/clk-ddr.c | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/drivers/clk/rockchip/clk-ddr.c b/drivers/clk/rockchip/clk-ddr.c index c247c9aaf5f5..9892c982d194 100644 --- a/drivers/clk/rockchip/clk-ddr.c +++ b/drivers/clk/rockchip/clk-ddr.c @@ -105,6 +105,8 @@ static const struct clk_ops rockchip_ddrclk_sip_ops = { .get_parent = rockchip_ddrclk_get_parent, }; +static u32 ddr_clk_cached; + static int rockchip_ddrclk_scpi_set_rate(struct clk_hw *hw, unsigned long drate, unsigned long prate) { @@ -112,6 +114,13 @@ static int rockchip_ddrclk_scpi_set_rate(struct clk_hw *hw, unsigned long drate, u32 lcdc_type = 7; ret = scpi_ddr_set_clk_rate(drate / MHZ, lcdc_type); + if (ret) { + ddr_clk_cached = ret; + ret = 0; + } else { + ddr_clk_cached = 0; + ret = -1; + } return ret; } @@ -119,7 +128,10 @@ static int rockchip_ddrclk_scpi_set_rate(struct clk_hw *hw, unsigned long drate, static unsigned long rockchip_ddrclk_scpi_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { - return (MHZ * scpi_ddr_get_clk_rate()); + if (ddr_clk_cached) + return (MHZ * ddr_clk_cached); + else + return (MHZ * scpi_ddr_get_clk_rate()); } static long rockchip_ddrclk_scpi_round_rate(struct clk_hw *hw, -- 2.34.1