From 3ea1b064a0b9c3d161b0f77a9e957970f98907ab Mon Sep 17 00:00:00 2001
From: Hal Finkel <hfinkel@anl.gov>
Date: Thu, 21 Mar 2013 23:23:34 +0000
Subject: [PATCH] Fix a register-class comparison bug in PPCCTRLoops

Thanks to Jakob for isolating the underlying problem from the
test case in r177423. The original commit had introduced
asymmetric copy operations, but these turned out to be a work-around
to the real problem (the use of == instead of hasSubClassEq in PPCCTRLoops).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177679 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Target/PowerPC/PPCCTRLoops.cpp         | 2 +-
 lib/Target/PowerPC/PPCInstr64Bit.td        | 9 ---------
 lib/Target/PowerPC/PPCInstrInfo.cpp        | 9 ---------
 test/CodeGen/PowerPC/asym-regclass-copy.ll | 3 ++-
 4 files changed, 3 insertions(+), 20 deletions(-)

diff --git a/lib/Target/PowerPC/PPCCTRLoops.cpp b/lib/Target/PowerPC/PPCCTRLoops.cpp
index 5b20f81a3e0..81a54d7015b 100644
--- a/lib/Target/PowerPC/PPCCTRLoops.cpp
+++ b/lib/Target/PowerPC/PPCCTRLoops.cpp
@@ -685,7 +685,7 @@ bool PPCCTRLoops::convertToCTRLoop(MachineLoop *L) {
     const TargetRegisterClass *SrcRC =
       MF->getRegInfo().getRegClass(TripCount->getReg());
     CountReg = MF->getRegInfo().createVirtualRegister(RC);
-    unsigned CopyOp = (isPPC64 && SrcRC == GPRC) ?
+    unsigned CopyOp = (isPPC64 && GPRC->hasSubClassEq(SrcRC)) ?
                         (unsigned) PPC::EXTSW_32_64 :
                         (unsigned) TargetOpcode::COPY;
     BuildMI(*Preheader, InsertPos, dl,
diff --git a/lib/Target/PowerPC/PPCInstr64Bit.td b/lib/Target/PowerPC/PPCInstr64Bit.td
index 975a7174f64..d2b1d6d3920 100644
--- a/lib/Target/PowerPC/PPCInstr64Bit.td
+++ b/lib/Target/PowerPC/PPCInstr64Bit.td
@@ -366,15 +366,6 @@ def XOR8 : XForm_6<31, 316, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
                    "xor $rA, $rS, $rB", IntSimple,
                    [(set G8RC:$rA, (xor G8RC:$rS, G8RC:$rB))]>;
 
-// Moves between 32-bit and 64-bit registers (used for copy resolution
-// after register allocation).
-let isCodeGenOnly = 1 in {
-def OR8_32  : XForm_6<31, 444, (outs G8RC:$rA), (ins GPRC:$rS, GPRC:$rB),
-                      "or $rA, $rS, $rB", IntSimple, []>;
-def OR_64   : XForm_6<31, 444, (outs GPRC:$rA), (ins G8RC:$rS, G8RC:$rB),
-                      "or $rA, $rS, $rB", IntSimple, []>;
-}
-
 // Logical ops with immediate.
 def ANDIo8  : DForm_4<28, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2),
                       "andi. $dst, $src1, $src2", IntGeneral,
diff --git a/lib/Target/PowerPC/PPCInstrInfo.cpp b/lib/Target/PowerPC/PPCInstrInfo.cpp
index 2b71f673312..cf39386c67b 100644
--- a/lib/Target/PowerPC/PPCInstrInfo.cpp
+++ b/lib/Target/PowerPC/PPCInstrInfo.cpp
@@ -422,15 +422,6 @@ void PPCInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
     Opc = PPC::VOR;
   else if (PPC::CRBITRCRegClass.contains(DestReg, SrcReg))
     Opc = PPC::CROR;
-
-  // Asymmetric copies:
-
-  else if (PPC::GPRCRegClass.contains(DestReg) &&
-           PPC::G8RCRegClass.contains(SrcReg))
-    Opc = PPC::OR_64;
-  else if (PPC::G8RCRegClass.contains(DestReg) &&
-           PPC::GPRCRegClass.contains(SrcReg))
-    Opc = PPC::OR8_32;
   else
     llvm_unreachable("Impossible reg-to-reg copy");
 
diff --git a/test/CodeGen/PowerPC/asym-regclass-copy.ll b/test/CodeGen/PowerPC/asym-regclass-copy.ll
index c399802a1ee..d04a6c98ee1 100644
--- a/test/CodeGen/PowerPC/asym-regclass-copy.ll
+++ b/test/CodeGen/PowerPC/asym-regclass-copy.ll
@@ -2,7 +2,8 @@
 target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
 target triple = "powerpc64-unknown-linux-gnu"
 
-; This test triggers the use of the asymmetric OR8_32 copy pattern.
+; This tests that the GPRC/GPRC_NOR0 intersection subclass relationship with
+; GPRC is handled correctly. When it was not, this test would assert.
 
 @gen_random.last = external unnamed_addr global i64, align 8
 @.str = external unnamed_addr constant [4 x i8], align 1
-- 
2.34.1