From 3ec43ed936007826d960b6edee43342b28ef868c Mon Sep 17 00:00:00 2001 From: =?utf8?q?=E9=99=88=E4=BA=AE?= Date: Mon, 17 Mar 2014 01:54:34 -0700 Subject: [PATCH] rk3188 : disable ddr freq && disable nand suspend && disable power onoff pll for sleep err --- arch/arm/mach-rockchip/Kconfig | 2 +- arch/arm/mach-rockchip/pm-rk3188.c | 12 ++++++------ drivers/mtd/rknand/rknand_base_ko.c | 8 ++++---- 3 files changed, 11 insertions(+), 11 deletions(-) diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 43389aab0314..a0c4d82fe7ae 100755 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -50,7 +50,7 @@ config DVFS config DDR_FREQ bool "Enable DDR frequency scaling" - default y + default n select DVFS config RK_VPU diff --git a/arch/arm/mach-rockchip/pm-rk3188.c b/arch/arm/mach-rockchip/pm-rk3188.c index 2f69c4404ca9..1aa770820c29 100755 --- a/arch/arm/mach-rockchip/pm-rk3188.c +++ b/arch/arm/mach-rockchip/pm-rk3188.c @@ -342,7 +342,7 @@ void plls_suspend(void) cru_writel(RK3188_PLL_MODE_SLOW(RK3188_CPLL_ID), RK3188_CRU_MODE_CON); cpll_con3 = cru_readl(RK3188_PLL_CONS(RK3188_CPLL_ID, 3)); - power_off_pll(RK3188_CPLL_ID); + //power_off_pll(RK3188_CPLL_ID); //apll @@ -364,7 +364,7 @@ void plls_suspend(void) | RK3188_ACLK_PCLK_W_MSK | RK3188_ACLK_PCLK_11 | RK3188_AHB2APB_W_MSK | RK3188_AHB2APB_11 , RK3188_CRU_CLKSELS_CON(1)); - power_off_pll(RK3188_APLL_ID); + //power_off_pll(RK3188_APLL_ID); cru_writel(RK3188_PLL_MODE_SLOW(RK3188_GPLL_ID), RK3188_CRU_MODE_CON); @@ -374,7 +374,7 @@ void plls_suspend(void) | RK3188_CRU_W_MSK_SETBITS(0, RK3188_PERI_PCLK_DIV_OFF, RK3188_PERI_PCLK_DIV_MASK) , RK3188_CRU_CLKSELS_CON(10)); - power_off_pll(RK3188_GPLL_ID); + //power_off_pll(RK3188_GPLL_ID); } @@ -384,7 +384,7 @@ void plls_resume(void) cru_writel(0xffff0000 | clk_sel10, RK3188_CRU_CLKSELS_CON(10)); - power_on_pll(RK3188_GPLL_ID); + // power_on_pll(RK3188_GPLL_ID); cru_writel((RK3188_PLL_MODE_MSK(RK3188_GPLL_ID) << 16) | (RK3188_PLL_MODE_MSK(RK3188_GPLL_ID) & cru_mode_con) , RK3188_CRU_MODE_CON); @@ -401,7 +401,7 @@ void plls_resume(void) | clk_sel0 , RK3188_CRU_CLKSELS_CON(0)); - power_on_pll(RK3188_APLL_ID); + // power_on_pll(RK3188_APLL_ID); cru_writel((RK3188_PLL_MODE_MSK(RK3188_APLL_ID) << 16) | (RK3188_PLL_MODE_MSK(RK3188_APLL_ID) & cru_mode_con) , RK3188_CRU_MODE_CON); @@ -411,7 +411,7 @@ void plls_resume(void) if (((cpll_con3 & RK3188_PLL_PWR_DN_MSK) == RK3188_PLL_PWR_ON) &&((RK3188_PLL_MODE_NORM(RK3188_CPLL_ID) & RK3188_PLL_MODE_MSK(RK3188_CPLL_ID)) == (cru_mode_con & RK3188_PLL_MODE_MSK(RK3188_CPLL_ID)))) { - power_on_pll(RK3188_CPLL_ID); + // power_on_pll(RK3188_CPLL_ID); } cru_writel((RK3188_PLL_MODE_MSK(RK3188_CPLL_ID) << 16) | (RK3188_PLL_MODE_MSK(RK3188_CPLL_ID) & cru_mode_con) diff --git a/drivers/mtd/rknand/rknand_base_ko.c b/drivers/mtd/rknand/rknand_base_ko.c index 9b8ebb83cfca..e0c2e59c4a26 100755 --- a/drivers/mtd/rknand/rknand_base_ko.c +++ b/drivers/mtd/rknand/rknand_base_ko.c @@ -627,16 +627,16 @@ exit_free: static int rknand_suspend(struct platform_device *pdev, pm_message_t state) { gpNandInfo->rknand.rknand_schedule_enable = 0; - if(gpNandInfo->rknand_suspend) - gpNandInfo->rknand_suspend(); + // if(gpNandInfo->rknand_suspend) + // gpNandInfo->rknand_suspend(); NAND_DEBUG(NAND_DEBUG_LEVEL0,"rknand_suspend: \n"); return 0; } static int rknand_resume(struct platform_device *pdev) { - if(gpNandInfo->rknand_resume) - gpNandInfo->rknand_resume(); + //if(gpNandInfo->rknand_resume) + // gpNandInfo->rknand_resume(); gpNandInfo->rknand.rknand_schedule_enable = 1; NAND_DEBUG(NAND_DEBUG_LEVEL0,"rknand_resume: \n"); return 0; -- 2.34.1