From 3ef392c4e2710c7f1709090d12e5e351fd4c69e1 Mon Sep 17 00:00:00 2001 From: Juergen Ributzka Date: Wed, 20 Aug 2014 01:10:36 +0000 Subject: [PATCH] [FastISel][AArch64] Use the proper FMOV instruction to materialize a +0.0. Use FMOVWSr/FMOVXDr instead of FMOVSr/FMOVDr, which have the proper register class to be used with the zero register. This makes the MachineInstruction verifier happy again. This is related to . git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216040 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/AArch64/AArch64FastISel.cpp | 2 +- test/CodeGen/AArch64/arm64-fast-isel-materialize.ll | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/lib/Target/AArch64/AArch64FastISel.cpp b/lib/Target/AArch64/AArch64FastISel.cpp index 9f59f884dee..90c509d4ce0 100644 --- a/lib/Target/AArch64/AArch64FastISel.cpp +++ b/lib/Target/AArch64/AArch64FastISel.cpp @@ -291,7 +291,7 @@ unsigned AArch64FastISel::AArch64MaterializeFP(const ConstantFP *CFP, MVT VT) { // register, because the immediate version of fmov cannot encode zero. if (Val.isPosZero()) { unsigned ZReg = Is64Bit ? AArch64::XZR : AArch64::WZR; - unsigned Opc = Is64Bit ? AArch64::FMOVDr : AArch64::FMOVSr; + unsigned Opc = Is64Bit ? AArch64::FMOVXDr : AArch64::FMOVWSr; BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg) .addReg(ZReg, getKillRegState(true)); return ResultReg; diff --git a/test/CodeGen/AArch64/arm64-fast-isel-materialize.ll b/test/CodeGen/AArch64/arm64-fast-isel-materialize.ll index 14dc0dd93b9..1dea5d944be 100644 --- a/test/CodeGen/AArch64/arm64-fast-isel-materialize.ll +++ b/test/CodeGen/AArch64/arm64-fast-isel-materialize.ll @@ -1,4 +1,4 @@ -; RUN: llc -O0 -fast-isel-abort -mtriple=arm64-apple-darwin < %s | FileCheck %s +; RUN: llc -O0 -fast-isel-abort -verify-machineinstrs -mtriple=arm64-apple-darwin < %s | FileCheck %s ; Materialize using fmov define float @fmov_float1() { -- 2.34.1