From 3f2aee7e02a5ddbe173bcf02fbb007f0dc71dcf0 Mon Sep 17 00:00:00 2001 From: Pete Cooper Date: Thu, 7 Aug 2014 05:46:54 +0000 Subject: [PATCH] Fix a whole bunch of binary literals which were the wrong size. All were being silently zero extended to the correct width. The commit after this changes { } and 0bxx literals to be of type bits and not int. This means we need to write exactly the right number of bits, and not rely on the values being silently zero extended for us. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215082 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/ARMInstrNEON.td | 2 +- lib/Target/ARM/ARMInstrThumb2.td | 4 ++-- lib/Target/Mips/Mips16InstrFormats.td | 2 +- lib/Target/Sparc/SparcInstrInfo.td | 2 +- lib/Target/Sparc/SparcInstrVIS.td | 34 +++++++++++++-------------- lib/Target/XCore/XCoreInstrInfo.td | 4 ++-- 6 files changed, 24 insertions(+), 24 deletions(-) diff --git a/lib/Target/ARM/ARMInstrNEON.td b/lib/Target/ARM/ARMInstrNEON.td index c02bb3b55f5..ca0b05d3842 100644 --- a/lib/Target/ARM/ARMInstrNEON.td +++ b/lib/Target/ARM/ARMInstrNEON.td @@ -4376,7 +4376,7 @@ defm VMLSLslu : N3VLMulOpSL_HS<1, 0b0110, "vmlsl", "u", NEONvmullu, sub>; // VQDMLSL : Vector Saturating Doubling Multiply Subtract Long (Q -= D * D) defm VQDMLSL : N3VLInt3_HS<0, 1, 0b1011, 0, IIC_VMACi16D, IIC_VMACi32D, "vqdmlsl", "s", null_frag>; -defm VQDMLSLsl: N3VLInt3SL_HS<0, 0b111, "vqdmlsl", "s", null_frag>; +defm VQDMLSLsl: N3VLInt3SL_HS<0, 0b0111, "vqdmlsl", "s", null_frag>; def : Pat<(v4i32 (int_arm_neon_vqsubs (v4i32 QPR:$src1), (v4i32 (int_arm_neon_vqdmull (v4i16 DPR:$Vn), diff --git a/lib/Target/ARM/ARMInstrThumb2.td b/lib/Target/ARM/ARMInstrThumb2.td index a1fee0ad458..46dbd8c95ed 100644 --- a/lib/Target/ARM/ARMInstrThumb2.td +++ b/lib/Target/ARM/ARMInstrThumb2.td @@ -3978,7 +3978,7 @@ def t2MRS_AR : T2I<(outs GPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, apsr", bits<4> Rd; let Inst{31-12} = 0b11110011111011111000; let Inst{11-8} = Rd; - let Inst{7-0} = 0b0000; + let Inst{7-0} = 0b00000000; } def : t2InstAlias<"mrs${p} $Rd, cpsr", (t2MRS_AR GPR:$Rd, pred:$p)>; @@ -3988,7 +3988,7 @@ def t2MRSsys_AR: T2I<(outs GPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, spsr", bits<4> Rd; let Inst{31-12} = 0b11110011111111111000; let Inst{11-8} = Rd; - let Inst{7-0} = 0b0000; + let Inst{7-0} = 0b00000000; } // M class MRS. diff --git a/lib/Target/Mips/Mips16InstrFormats.td b/lib/Target/Mips/Mips16InstrFormats.td index da3a1f114af..4ff68bef957 100644 --- a/lib/Target/Mips/Mips16InstrFormats.td +++ b/lib/Target/Mips/Mips16InstrFormats.td @@ -591,7 +591,7 @@ class FEXT_I816 _funct, dag outs, dag ins, string asmstr, bits<3> funct; let funct = _funct; - let I8 = 0b0110; + let I8 = 0b00110; let Inst{26-21} = imm16{10-5}; let Inst{20-16} = imm16{15-11}; diff --git a/lib/Target/Sparc/SparcInstrInfo.td b/lib/Target/Sparc/SparcInstrInfo.td index 960261ce983..c32023901b2 100644 --- a/lib/Target/Sparc/SparcInstrInfo.td +++ b/lib/Target/Sparc/SparcInstrInfo.td @@ -331,7 +331,7 @@ let hasSideEffects = 1, mayStore = 1 in { [(flushw)]>; } -let isBarrier = 1, isTerminator = 1, rd = 0b1000, rs1 = 0, simm13 = 5 in +let isBarrier = 1, isTerminator = 1, rd = 0b01000, rs1 = 0, simm13 = 5 in def TA5 : F3_2<0b10, 0b111010, (outs), (ins), "ta 5", [(trap)]>; let rd = 0 in diff --git a/lib/Target/Sparc/SparcInstrVIS.td b/lib/Target/Sparc/SparcInstrVIS.td index 3e2b49d05c2..d9adf3e8b0f 100644 --- a/lib/Target/Sparc/SparcInstrVIS.td +++ b/lib/Target/Sparc/SparcInstrVIS.td @@ -71,13 +71,13 @@ def FPACKFIX : VISInst2<0b000111101, "fpackfix">; def FEXPAND : VISInst2<0b001001101, "fexpand">; def FPMERGE : VISInst <0b001001011, "fpmerge">; -def FMUL8X16 : VISInst<0b00110001, "fmul8x16">; -def FMUL8X16AU : VISInst<0b00110011, "fmul8x16au">; -def FMUL8X16AL : VISInst<0b00110101, "fmul8x16al">; -def FMUL8SUX16 : VISInst<0b00110110, "fmul8sux16">; -def FMUL8ULX16 : VISInst<0b00110111, "fmul8ulx16">; -def FMULD8SUX16 : VISInst<0b00111000, "fmuld8sux16">; -def FMULD8ULX16 : VISInst<0b00111001, "fmuld8ulx16">; +def FMUL8X16 : VISInst<0b000110001, "fmul8x16">; +def FMUL8X16AU : VISInst<0b000110011, "fmul8x16au">; +def FMUL8X16AL : VISInst<0b000110101, "fmul8x16al">; +def FMUL8SUX16 : VISInst<0b000110110, "fmul8sux16">; +def FMUL8ULX16 : VISInst<0b000110111, "fmul8ulx16">; +def FMULD8SUX16 : VISInst<0b000111000, "fmuld8sux16">; +def FMULD8ULX16 : VISInst<0b000111001, "fmuld8ulx16">; def ALIGNADDR : VISInst<0b000011000, "alignaddr", I64Regs>; def ALIGNADDRL : VISInst<0b000011010, "alignaddrl", I64Regs>; @@ -134,7 +134,7 @@ def EDGE16L : VISInst<0b000000110, "edge16l", I64Regs>; def EDGE32 : VISInst<0b000001000, "edge32", I64Regs>; def EDGE32L : VISInst<0b000001010, "edge32l", I64Regs>; -def PDIST : VISInst<0b00111110, "pdist">; +def PDIST : VISInst<0b000111110, "pdist">; def ARRAY8 : VISInst<0b000010000, "array8", I64Regs>; def ARRAY16 : VISInst<0b000010010, "array16", I64Regs>; @@ -181,7 +181,7 @@ def CMASK32 : VISInstFormat<0b000011111, (outs), (ins I64Regs:$rs2), } -def FCHKSM16 : VISInst<0b01000100, "fchksm16">; +def FCHKSM16 : VISInst<0b001000100, "fchksm16">; def FHADDS : F3_3<0b10, 0b110100, 0b001100001, (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2), @@ -229,14 +229,14 @@ def FNSMULD : F3_3<0b10, 0b110100, 0b001111001, def FPADD64 : VISInst<0b001000010, "fpadd64">; -def FSLL16 : VISInst<0b00100001, "fsll16">; -def FSRL16 : VISInst<0b00100011, "fsrl16">; -def FSLL32 : VISInst<0b00100101, "fsll32">; -def FSRL32 : VISInst<0b00100111, "fsrl32">; -def FSLAS16 : VISInst<0b00101001, "fslas16">; -def FSRA16 : VISInst<0b00101011, "fsra16">; -def FSLAS32 : VISInst<0b00101101, "fslas32">; -def FSRA32 : VISInst<0b00101111, "fsra32">; +def FSLL16 : VISInst<0b000100001, "fsll16">; +def FSRL16 : VISInst<0b000100011, "fsrl16">; +def FSLL32 : VISInst<0b000100101, "fsll32">; +def FSRL32 : VISInst<0b000100111, "fsrl32">; +def FSLAS16 : VISInst<0b000101001, "fslas16">; +def FSRA16 : VISInst<0b000101011, "fsra16">; +def FSLAS32 : VISInst<0b000101101, "fslas32">; +def FSRA32 : VISInst<0b000101111, "fsra32">; let rs1 = 0 in def LZCNT : VISInstFormat<0b000010111, (outs I64Regs:$rd), diff --git a/lib/Target/XCore/XCoreInstrInfo.td b/lib/Target/XCore/XCoreInstrInfo.td index 00cb705c8d3..d34ed7a6ec8 100644 --- a/lib/Target/XCore/XCoreInstrInfo.td +++ b/lib/Target/XCore/XCoreInstrInfo.td @@ -412,7 +412,7 @@ def STW_l3r : _FL3R<0b000001100, (outs), (ins GRRegs:$val, GRRegs:$addr, GRRegs:$offset), "stw $val, $addr[$offset]", []>; -def STW_2rus : _F2RUS<0b0000, (outs), +def STW_2rus : _F2RUS<0b00000, (outs), (ins GRRegs:$val, GRRegs:$addr, i32imm:$offset), "stw $val, $addr[$offset]", []>; } @@ -902,7 +902,7 @@ def BYTEREV_l2r : _FL2R<0b0000011001, (outs GRRegs:$dst), (ins GRRegs:$src), "byterev $dst, $src", [(set GRRegs:$dst, (bswap GRRegs:$src))]>; -def CLZ_l2r : _FL2R<0b000111000, (outs GRRegs:$dst), (ins GRRegs:$src), +def CLZ_l2r : _FL2R<0b0000111000, (outs GRRegs:$dst), (ins GRRegs:$src), "clz $dst, $src", [(set GRRegs:$dst, (ctlz GRRegs:$src))]>; -- 2.34.1