From 3f3c5a9fc9e65823c8de0b7130b58cfec5918124 Mon Sep 17 00:00:00 2001 From: Rebecca Schultz Zavin Date: Tue, 22 Mar 2011 11:05:59 -0700 Subject: [PATCH] Revert "ARM: Cortex-A9: Enable dynamic clock gating" This reverts commit 91406b03fa4add49db13e55c3220911be55d9883. --- arch/arm/Kconfig | 10 ---------- arch/arm/mm/proc-v7.S | 10 ---------- 2 files changed, 20 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 0a293ee4a313..cd2c427f0e2b 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1129,16 +1129,6 @@ config ARM_ERRATA_743622 visible impact on the overall performance or power consumption of the processor. -config ARM_ERRATA_720791 - bool "ARM errata: Dynamic high-level clock gating corrupts the Jazelle instruction stream" - depends on CPU_V7 - help - This option enables the workaround for the 720791 Cortex-A9 - (r1p0..r1p2) erratum. The Jazelle instruction stream may be - corrupted when dynamic high-level clock gating is enabled. - This workaround disables gating the Core clock when the Instruction - side is waiting for a Page Table Walk answer or linefill completion. - endmenu source "arch/arm/common/Kconfig" diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index de77d5b4271a..8cdf3bf26719 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -238,16 +238,6 @@ __v7_setup: 2: ldr r10, =0x00000c09 @ Cortex-A9 primary part number teq r0, r10 bne 3f - cmp r6, #0x10 @ power ctrl reg added r1p0 - mrcge p15, 0, r10, c15, c0, 0 @ read power control register - orrge r10, r10, #1 @ enable dynamic clock gating - mcrge p15, 0, r10, c15, c0, 0 @ write power control register -#ifdef CONFIG_ARM_ERRATA_720791 - teq r5, #0x00100000 @ only present in r1p* - mrceq p15, 0, r10, c15, c0, 2 @ read "chicken power ctrl" reg - orreq r10, r10, #0x30 @ disable core clk gate on - mcreq p15, 0, r10, c15, c0, 2 @ instr-side waits -#endif #ifdef CONFIG_ARM_ERRATA_742230 cmp r6, #0x22 @ only present up to r2p2 mrcle p15, 0, r10, c15, c0, 1 @ read diagnostic register -- 2.34.1