From 4013e49d8c557d7e7980b92f73fda0cf31cf6124 Mon Sep 17 00:00:00 2001 From: Luowei Date: Thu, 18 Sep 2014 14:53:57 +0800 Subject: [PATCH] spi:fix bug of initial clock division --- drivers/spi/spi-rockchip-core.c | 9 +++++++-- drivers/spi/spi-rockchip.c | 2 +- 2 files changed, 8 insertions(+), 3 deletions(-) diff --git a/drivers/spi/spi-rockchip-core.c b/drivers/spi/spi-rockchip-core.c index 63aacfd2f8be..4626b9f00fda 100755 --- a/drivers/spi/spi-rockchip-core.c +++ b/drivers/spi/spi-rockchip-core.c @@ -579,7 +579,12 @@ static void pump_transfers(unsigned long data) spi = message->spi; if (unlikely(!chip->clk_div)) + { chip->clk_div = dws->max_freq / chip->speed_hz; + chip->clk_div = (chip->clk_div + 1) & 0xfffe; + chip->speed_hz = dws->max_freq / chip->clk_div; + } + if (message->state == ERROR_STATE) { message->status = -EIO; @@ -619,7 +624,6 @@ static void pump_transfers(unsigned long data) cr0 = chip->cr0; - DBG_SPI("%s:len=%d\n",__func__,dws->len); /* Handle per transfer options for bpw and speed */ if (transfer->speed_hz) { @@ -638,10 +642,11 @@ static void pump_transfers(unsigned long data) clk_div = dws->max_freq / speed; clk_div = (clk_div + 1) & 0xfffe; - chip->speed_hz = speed; + chip->speed_hz = dws->max_freq / clk_div; chip->clk_div = clk_div; } } + DBG_SPI("%s:len=%d,clk_div=%d,speed_hz=%d\n",__func__,dws->len,chip->clk_div,chip->speed_hz); if (transfer->bits_per_word) { bits = transfer->bits_per_word; diff --git a/drivers/spi/spi-rockchip.c b/drivers/spi/spi-rockchip.c index 6b04b8e0c2b6..257319be2dbe 100755 --- a/drivers/spi/spi-rockchip.c +++ b/drivers/spi/spi-rockchip.c @@ -228,7 +228,7 @@ static int rockchip_spi_probe(struct platform_device *pdev) platform_set_drvdata(pdev, sdd); - printk("%s:num_cs=%d,irq=%d,freq=%d ok\n",__func__, info->num_cs, irq, dws->max_freq); + printk("%s:num_cs=%d,bus_num=%d,irq=%d,freq=%d ok\n",__func__, info->num_cs, info->bus_num, irq, dws->max_freq); return 0; err_release_mem: -- 2.34.1