From 408c0ddf13ce80a9c0f5ce056385e55b0b21d348 Mon Sep 17 00:00:00 2001 From: ljf Date: Tue, 22 Apr 2014 17:02:46 +0800 Subject: [PATCH 1/1] rk3288: iep support yuv denoise --- drivers/video/rockchip/iep/hw_iep_reg.c | 4 ++++ drivers/video/rockchip/iep/hw_iep_reg.h | 12 ++++++++++++ 2 files changed, 16 insertions(+) diff --git a/drivers/video/rockchip/iep/hw_iep_reg.c b/drivers/video/rockchip/iep/hw_iep_reg.c index f926bee4404c..175ae424e9c1 100755 --- a/drivers/video/rockchip/iep/hw_iep_reg.c +++ b/drivers/video/rockchip/iep/hw_iep_reg.c @@ -381,6 +381,10 @@ static void iep_config_color_enh(IEP_MSG *iep_msg) static void iep_config_yuv_dns(IEP_MSG *iep_msg) { IEP_REGB_YUV_DNS_EN(iep_msg->base, iep_msg->yuv_3D_denoise_en); + IEP_REGB_YUV_DNS_LUMA_SPAT_SEL(iep_msg->base, 0); + IEP_REGB_YUV_DNS_LUMA_TEMP_SEL(iep_msg->base, 1); + IEP_REGB_YUV_DNS_CHROMA_SPAT_SEL(iep_msg->base, 2); + IEP_REGB_YUV_DNS_CHROMA_TEMP_SEL(iep_msg->base, 3); #ifdef IEP_PRINT_INFO IEP_DBG("//==yuv denoise config========================// \n\n"); IEP_DBG("sw_yuv_dns_en = %d;//0:yuv 3d denoise disable; 1:enable\n\n", iep_msg->yuv_3D_denoise_en); diff --git a/drivers/video/rockchip/iep/hw_iep_reg.h b/drivers/video/rockchip/iep/hw_iep_reg.h index 3f66966f9986..a28dd8110be9 100755 --- a/drivers/video/rockchip/iep/hw_iep_reg.h +++ b/drivers/video/rockchip/iep/hw_iep_reg.h @@ -234,6 +234,10 @@ enum iep_mmu_cmd { #define IEP_REGB_COLOR_BAR_U_Z(x) (((x)&0xff ) << 8 ) #define IEP_REGB_COLOR_BAR_Y_Z(x) (((x)&0xff ) << 0 ) //iep_enh_rgb_cnfg +#define IEP_REGB_YUV_DNS_LUMA_SPAT_SEL_Z(x) (((x)&0x3 ) << 30 ) +#define IEP_REGB_YUV_DNS_LUMA_TEMP_SEL_Z(x) (((x)&0x3 ) << 28 ) +#define IEP_REGB_YUV_DNS_CHROMA_SPAT_SEL_Z(x) (((x)&0x3 ) << 26 ) +#define IEP_REGB_YUV_DNS_CHROMA_TEMP_SEL_Z(x) (((x)&0x3 ) << 24 ) #define IEP_REGB_ENH_THRESHOLD_Z(x) (((x)&0xff ) << 16 ) #define IEP_REGB_ENH_ALPHA_Z(x) (((x)&0x3f ) << 8 ) #define IEP_REGB_ENH_RADIUS_Z(x) (((x)&0x3 ) << 0 ) @@ -394,6 +398,10 @@ enum iep_mmu_cmd { #define IEP_REGB_COLOR_BAR_U_Y (0xff << 8 ) #define IEP_REGB_COLOR_BAR_Y_Y (0xff << 0 ) //iep_enh_rgb_cnfg +#define IEP_REGB_YUV_DNS_LUMA_SPAT_SEL_Y (0x3 << 30) +#define IEP_REGB_YUV_DNS_LUMA_TEMP_SEL_Y (0x3 << 28) +#define IEP_REGB_YUV_DNS_CHROMA_SPAT_SEL_Y (0x3 << 26) +#define IEP_REGB_YUV_DNS_CHROMA_TEMP_SEL_Y (0x3 << 24) #define IEP_REGB_ENH_THRESHOLD_Y (0xff << 16) #define IEP_REGB_ENH_ALPHA_Y (0x3f << 8 ) #define IEP_REGB_ENH_RADIUS_Y (0x3 << 0 ) @@ -563,6 +571,10 @@ enum iep_mmu_cmd { #define IEP_REGB_COLOR_BAR_U(base, x) ConfRegBits32(base, RAW_rIEP_ENH_YUV_CNFG_2,rIEP_ENH_YUV_CNFG_2,IEP_REGB_COLOR_BAR_U_Y,IEP_REGB_COLOR_BAR_U_Z(x)) #define IEP_REGB_COLOR_BAR_Y(base, x) ConfRegBits32(base, RAW_rIEP_ENH_YUV_CNFG_2,rIEP_ENH_YUV_CNFG_2,IEP_REGB_COLOR_BAR_Y_Y,IEP_REGB_COLOR_BAR_Y_Z(x)) //iep_enh_rgb_cnfg +#define IEP_REGB_YUV_DNS_LUMA_SPAT_SEL(base, x) ConfRegBits32(base, RAW_rIEP_ENH_RGB_CNFG,rIEP_ENH_RGB_CNFG,IEP_REGB_YUV_DNS_LUMA_SPAT_SEL_Y,IEP_REGB_YUV_DNS_LUMA_SPAT_SEL_Z(x)) +#define IEP_REGB_YUV_DNS_LUMA_TEMP_SEL(base, x) ConfRegBits32(base, RAW_rIEP_ENH_RGB_CNFG,rIEP_ENH_RGB_CNFG,IEP_REGB_YUV_DNS_LUMA_TEMP_SEL_Y,IEP_REGB_YUV_DNS_LUMA_TEMP_SEL_Z(x)) +#define IEP_REGB_YUV_DNS_CHROMA_SPAT_SEL(base, x) ConfRegBits32(base, RAW_rIEP_ENH_RGB_CNFG,rIEP_ENH_RGB_CNFG,IEP_REGB_YUV_DNS_CHROMA_SPAT_SEL_Y,IEP_REGB_YUV_DNS_CHROMA_SPAT_SEL_Z(x)) +#define IEP_REGB_YUV_DNS_CHROMA_TEMP_SEL(base, x) ConfRegBits32(base, RAW_rIEP_ENH_RGB_CNFG,rIEP_ENH_RGB_CNFG,IEP_REGB_YUV_DNS_CHROMA_TEMP_SEL_Y,IEP_REGB_YUV_DNS_CHROMA_TEMP_SEL_Z(x)) #define IEP_REGB_ENH_THRESHOLD(base, x) ConfRegBits32(base, RAW_rIEP_ENH_RGB_CNFG,rIEP_ENH_RGB_CNFG,IEP_REGB_ENH_THRESHOLD_Y,IEP_REGB_ENH_THRESHOLD_Z(x)) #define IEP_REGB_ENH_ALPHA(base, x) ConfRegBits32(base, RAW_rIEP_ENH_RGB_CNFG,rIEP_ENH_RGB_CNFG,IEP_REGB_ENH_ALPHA_Y,IEP_REGB_ENH_ALPHA_Z(x)) #define IEP_REGB_ENH_RADIUS(base, x) ConfRegBits32(base, RAW_rIEP_ENH_RGB_CNFG,rIEP_ENH_RGB_CNFG,IEP_REGB_ENH_RADIUS_Y,IEP_REGB_ENH_RADIUS_Z(x)) -- 2.34.1