From 40a1ab5ca92ccda7cdbd88df6942e596c0702611 Mon Sep 17 00:00:00 2001 From: =?utf8?q?=E9=BB=84=E6=B6=9B?= Date: Fri, 10 Dec 2010 18:05:40 +0800 Subject: [PATCH] =?utf8?q?rk29:=20L2=20cache=E8=AE=BE=E7=BD=AE=E5=8F=98?= =?utf8?q?=E6=9B=B4=E3=80=82=E6=A0=B9=E6=8D=AEIC=E9=83=A8=E7=9A=84?= =?utf8?q?=E5=BB=BA=E8=AE=AE=EF=BC=8C810~972=E9=A2=91=E7=8E=87=EF=BC=8Cdat?= =?utf8?q?a=20ram=20latency=E8=AE=BE=E4=B8=BA6=20cycles?= MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit --- arch/arm/mm/proc-v7.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index f5e368dc0912..9e41985cca25 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -272,7 +272,7 @@ __v7_setup: bic r5, r5, #7 << 6 bic r5, r5, #15 orr r5, r5, #3 << 6 @ Tag RAM latency: b011 = 4 cycles - orr r5, r5, #4 @ Data RAM latency: b0100 = 5 cycles + orr r5, r5, #5 @ Data RAM latency: b0101 = 6 cycles mcr p15, 1, r5, c9, c0, 2 #endif -- 2.34.1