From 4151e89f1e37040452700f7d87eec68a45461cf6 Mon Sep 17 00:00:00 2001 From: Matthias Braun Date: Mon, 15 Dec 2014 21:36:35 +0000 Subject: [PATCH] Revert "LiveRangeCalc: Rewrite subrange calculation" Revert until I find out why non-subreg enabled targets break. This reverts commit 6097277eefb9c5fb35a7f493c783ee1fd1b9d6a7. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224278 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/CodeGen/LiveIntervalAnalysis.cpp | 20 ++- lib/CodeGen/LiveRangeCalc.cpp | 251 ++++++++++++++++----------- lib/CodeGen/LiveRangeCalc.h | 123 ++++++++----- 3 files changed, 242 insertions(+), 152 deletions(-) diff --git a/lib/CodeGen/LiveIntervalAnalysis.cpp b/lib/CodeGen/LiveIntervalAnalysis.cpp index b71e819f0d3..f48be4d5eb0 100644 --- a/lib/CodeGen/LiveIntervalAnalysis.cpp +++ b/lib/CodeGen/LiveIntervalAnalysis.cpp @@ -192,7 +192,8 @@ void LiveIntervals::computeVirtRegInterval(LiveInterval &LI) { assert(LRCalc && "LRCalc not initialized."); assert(LI.empty() && "Should only compute empty intervals."); LRCalc->reset(MF, getSlotIndexes(), DomTree, &getVNInfoAllocator()); - LRCalc->calculate(LI); + LRCalc->createDeadDefs(LI); + LRCalc->extendToUses(LI); computeDeadValues(LI, LI); } @@ -250,15 +251,22 @@ void LiveIntervals::computeRegUnitRange(LiveRange &LR, unsigned Unit) { // may share super-registers. That's OK because createDeadDefs() is // idempotent. It is very rare for a register unit to have multiple roots, so // uniquing super-registers is probably not worthwhile. + for (MCRegUnitRootIterator Roots(Unit, TRI); Roots.isValid(); ++Roots) { + for (MCSuperRegIterator Supers(*Roots, TRI, /*IncludeSelf=*/true); + Supers.isValid(); ++Supers) { + if (!MRI->reg_empty(*Supers)) + LRCalc->createDeadDefs(LR, *Supers); + } + } + + // Now extend LR to reach all uses. + // Ignore uses of reserved registers. We only track defs of those. for (MCRegUnitRootIterator Roots(Unit, TRI); Roots.isValid(); ++Roots) { for (MCSuperRegIterator Supers(*Roots, TRI, /*IncludeSelf=*/true); Supers.isValid(); ++Supers) { unsigned Reg = *Supers; - if (MRI->reg_empty(Reg)) - continue; - // Ignore uses of reserved registers. We only track defs of those. - bool IgnoreUses = MRI->isReserved(Reg); - LRCalc->calculate(LR, *Supers, IgnoreUses); + if (!MRI->isReserved(Reg) && !MRI->reg_empty(Reg)) + LRCalc->extendToUses(LR, Reg); } } } diff --git a/lib/CodeGen/LiveRangeCalc.cpp b/lib/CodeGen/LiveRangeCalc.cpp index 040148f065e..37ca87cd69d 100644 --- a/lib/CodeGen/LiveRangeCalc.cpp +++ b/lib/CodeGen/LiveRangeCalc.cpp @@ -29,35 +29,31 @@ void LiveRangeCalc::reset(const MachineFunction *mf, DomTree = MDT; Alloc = VNIA; - unsigned NumBlocks = MF->getNumBlockIDs(); - Seen.clear(); - Seen.resize(NumBlocks); - Map.resize(NumBlocks); + MainLiveOutData.reset(MF->getNumBlockIDs()); + LiveIn.clear(); } -static void createDeadDef(SlotIndexes &Indexes, VNInfo::Allocator &Alloc, - LiveRange &LR, const MachineOperand &MO) { - const MachineInstr *MI = MO.getParent(); - SlotIndex DefIdx; - if (MI->isPHI()) { - DefIdx = Indexes.getMBBStartIdx(MI->getParent()); - } else { - DefIdx = Indexes.getInstructionIndex(MI).getRegSlot(MO.isEarlyClobber()); - } - // Create the def in LR. This may find an existing def. - LR.createDeadDef(DefIdx, Alloc); +static SlotIndex getDefIndex(const SlotIndexes &Indexes, const MachineInstr &MI, + bool EarlyClobber) { + // PHI defs begin at the basic block start index. + if (MI.isPHI()) + return Indexes.getMBBStartIdx(MI.getParent()); + + // Instructions are either normal 'r', or early clobber 'e'. + return Indexes.getInstructionIndex(&MI).getRegSlot(EarlyClobber); } -void LiveRangeCalc::calculate(LiveInterval &LI) { +void LiveRangeCalc::createDeadDefs(LiveInterval &LI) { assert(MRI && Indexes && "call reset() first"); - // Step 1: Create minimal live segments for every definition of Reg. // Visit all def operands. If the same instruction has multiple defs of Reg, // LR.createDeadDef() will deduplicate. const TargetRegisterInfo &TRI = *MRI->getTargetRegisterInfo(); unsigned Reg = LI.reg; - for (const MachineOperand &MO : MRI->reg_nodbg_operands(Reg)) { + for (const MachineOperand &MO : MRI->def_operands(Reg)) { + const MachineInstr *MI = MO.getParent(); + SlotIndex Idx = getDefIndex(*Indexes, *MI, MO.isEarlyClobber()); unsigned SubReg = MO.getSubReg(); if (LI.hasSubRanges() || (SubReg != 0 && MRI->tracksSubRegLiveness())) { unsigned Mask = SubReg != 0 ? TRI.getSubRegIndexLaneMask(SubReg) @@ -86,108 +82,155 @@ void LiveRangeCalc::calculate(LiveInterval &LI) { assert(Common == S.LaneMask); CommonRange = &S; } - if (MO.isDef()) - createDeadDef(*Indexes, *Alloc, *CommonRange, MO); + CommonRange->createDeadDef(Idx, *Alloc); Mask &= ~Common; } - // Create a new SubRange for subregs we did not cover yet. if (Mask != 0) { - LiveInterval::SubRange *NewRange = LI.createSubRange(*Alloc, Mask); - if (MO.isDef()) - createDeadDef(*Indexes, *Alloc, *NewRange, MO); + LiveInterval::SubRange *SubRange = LI.createSubRange(*Alloc, Mask); + SubRange->createDeadDef(Idx, *Alloc); } } - // Create the def in the main liverange. - if (MO.isDef()) - createDeadDef(*Indexes, *Alloc, LI, MO); - } - - // Step 2: Extend live segments to all uses, constructing SSA form as - // necessary. - for (LiveInterval::SubRange &S : LI.subranges()) { - extendToUses(S, Reg, S.LaneMask); + // Create the def in LR. This may find an existing def. + LI.createDeadDef(Idx, *Alloc); } - extendToUses(LI, Reg, ~0u); } -void LiveRangeCalc::calculate(LiveRange &LR, unsigned Reg, bool IgnoreUses) { +void LiveRangeCalc::createDeadDefs(LiveRange &LR, unsigned Reg) { assert(MRI && Indexes && "call reset() first"); - // Step 1: Create minimal live segments for every definition of Reg. // Visit all def operands. If the same instruction has multiple defs of Reg, // LR.createDeadDef() will deduplicate. for (MachineOperand &MO : MRI->def_operands(Reg)) { - createDeadDef(*Indexes, *Alloc, LR, MO); + const MachineInstr *MI = MO.getParent(); + SlotIndex Idx = getDefIndex(*Indexes, *MI, MO.isEarlyClobber()); + // Create the def in LR. This may find an existing def. + LR.createDeadDef(Idx, *Alloc); + } +} + + +static SlotIndex getUseIndex(const SlotIndexes &Indexes, + const MachineOperand &MO) { + const MachineInstr *MI = MO.getParent(); + unsigned OpNo = (&MO - &MI->getOperand(0)); + if (MI->isPHI()) { + assert(!MO.isDef() && "Cannot handle PHI def of partial register."); + // The actual place where a phi operand is used is the end of the pred MBB. + // PHI operands are paired: (Reg, PredMBB). + return Indexes.getMBBEndIdx(MI->getOperand(OpNo+1).getMBB()); } - // Step 2: Extend live segments to all uses, constructing SSA form as - // necessary. - if (!IgnoreUses) - extendToUses(LR, Reg, ~0u); + // Check for early-clobber redefs. + bool isEarlyClobber = false; + unsigned DefIdx; + if (MO.isDef()) { + isEarlyClobber = MO.isEarlyClobber(); + } else if (MI->isRegTiedToDefOperand(OpNo, &DefIdx)) { + // FIXME: This would be a lot easier if tied early-clobber uses also + // had an early-clobber flag. + isEarlyClobber = MI->getOperand(DefIdx).isEarlyClobber(); + } + return Indexes.getInstructionIndex(MI).getRegSlot(isEarlyClobber); } -void LiveRangeCalc::extendToUses(LiveRange &LR, unsigned Reg, unsigned Mask) { - unsigned NumBlocks = MF->getNumBlockIDs(); - Seen.clear(); - Seen.resize(NumBlocks); - Map.resize(NumBlocks); +void LiveRangeCalc::extendToUses(LiveRange &LR, unsigned Reg) { + assert(MRI && Indexes && "call reset() first"); // Visit all operands that read Reg. This may include partial defs. + for (MachineOperand &MO : MRI->reg_nodbg_operands(Reg)) { + // Clear all kill flags. They will be reinserted after register allocation + // by LiveIntervalAnalysis::addKillFlags(). + if (MO.isUse()) + MO.setIsKill(false); + if (!MO.readsReg()) + continue; + // MI is reading Reg. We may have visited MI before if it happens to be + // reading Reg multiple times. That is OK, extend() is idempotent. + SlotIndex Idx = getUseIndex(*Indexes, MO); + extend(LR, Idx, Reg, MainLiveOutData); + } +} + + +void LiveRangeCalc::extendToUses(LiveInterval &LI) { + assert(MRI && Indexes && "call reset() first"); + const TargetRegisterInfo &TRI = *MRI->getTargetRegisterInfo(); + SmallVector LiveOuts; + unsigned NumSubRanges = 0; + for (const auto &S : LI.subranges()) { + (void)S; + ++NumSubRanges; + LiveOuts.push_back(LiveOutData()); + LiveOuts.back().reset(MF->getNumBlockIDs()); + } + + // Visit all operands that read Reg. This may include partial defs. + unsigned Reg = LI.reg; for (MachineOperand &MO : MRI->reg_nodbg_operands(Reg)) { // Clear all kill flags. They will be reinserted after register allocation // by LiveIntervalAnalysis::addKillFlags(). if (MO.isUse()) MO.setIsKill(false); - // We are only interested in uses. For the main range this also includes - // the reads happening on partial register defs. - if (!MO.isUse() && (!MO.readsReg() || Mask != ~0u)) + if (!MO.readsReg()) continue; + SlotIndex Idx = getUseIndex(*Indexes, MO); unsigned SubReg = MO.getSubReg(); - if (SubReg != 0) { - unsigned SubRegMask = TRI.getSubRegIndexLaneMask(SubReg); - // Ignore uses not covering the current subrange. - if ((SubRegMask & Mask) == 0) - continue; - // The create dead-defs logic in calculate() splits subranges as fine as - // necessary for all uses, so SubRegMask shouldn't be smaller than Mask. - assert((SubRegMask & ~Mask) == 0); - } + if (MO.isUse() && (LI.hasSubRanges() || + (MRI->tracksSubRegLiveness() && SubReg != 0))) { + unsigned Mask = SubReg != 0 + ? TRI.getSubRegIndexLaneMask(SubReg) + : MRI->getMaxLaneMaskForVReg(Reg); - // Determine the actual place of the use. - const MachineInstr *MI = MO.getParent(); - unsigned OpNo = (&MO - &MI->getOperand(0)); - SlotIndex UseIdx; - if (MI->isPHI()) { - assert(!MO.isDef() && "Cannot handle PHI def of partial register."); - // The actual place where a phi operand is used is the end of the pred - // MBB. PHI operands are paired: (Reg, PredMBB). - UseIdx = Indexes->getMBBEndIdx(MI->getOperand(OpNo+1).getMBB()); - } else { - // Check for early-clobber redefs. - bool isEarlyClobber = false; - unsigned DefIdx; - if (MO.isDef()) { - isEarlyClobber = MO.isEarlyClobber(); - } else if (MI->isRegTiedToDefOperand(OpNo, &DefIdx)) { - // FIXME: This would be a lot easier if tied early-clobber uses also - // had an early-clobber flag. - isEarlyClobber = MI->getOperand(DefIdx).isEarlyClobber(); + // If this is the first time we see a subregister def/use. Initialize + // subranges by creating a copy of the main range. + if (!LI.hasSubRanges()) { + unsigned ClassMask = MRI->getMaxLaneMaskForVReg(Reg); + LI.createSubRangeFrom(*Alloc, ClassMask, LI); + LiveOuts.insert(LiveOuts.begin(), LiveOutData()); + LiveOuts.front().reset(MF->getNumBlockIDs()); + ++NumSubRanges; } - UseIdx = Indexes->getInstructionIndex(MI).getRegSlot(isEarlyClobber); + unsigned SubRangeIdx = 0; + for (LiveInterval::subrange_iterator S = LI.subrange_begin(), + SE = LI.subrange_end(); S != SE; ++S, ++SubRangeIdx) { + // A Mask for subregs common to the existing subrange and current def. + unsigned Common = S->LaneMask & Mask; + if (Common == 0) + continue; + // A Mask for subregs covered by the subrange but not the current def. + unsigned LRest = S->LaneMask & ~Mask; + LiveInterval::SubRange *CommonRange; + unsigned CommonRangeIdx; + if (LRest != 0) { + // Split current subrange into Common and LRest ranges. + S->LaneMask = LRest; + CommonRange = LI.createSubRangeFrom(*Alloc, Common, *S); + CommonRangeIdx = 0; + LiveOuts.insert(LiveOuts.begin(), LiveOutData()); + LiveOuts.front().reset(MF->getNumBlockIDs()); + ++NumSubRanges; + ++SubRangeIdx; + } else { + // The subrange and current def lanemasks match completely. + assert(Common == S->LaneMask); + CommonRange = &*S; + CommonRangeIdx = SubRangeIdx; + } + extend(*CommonRange, Idx, Reg, LiveOuts[CommonRangeIdx]); + Mask &= ~Common; + } + assert(SubRangeIdx == NumSubRanges); } - - // MI is reading Reg. We may have visited MI before if it happens to be - // reading Reg multiple times. That is OK, extend() is idempotent. - extend(LR, UseIdx, Reg); + extend(LI, Idx, Reg, MainLiveOutData); } } -void LiveRangeCalc::updateFromLiveIns() { +void LiveRangeCalc::updateFromLiveIns(LiveOutData &LiveOuts) { LiveRangeUpdater Updater; for (const LiveInBlock &I : LiveIn) { if (!I.DomNode) @@ -203,8 +246,8 @@ void LiveRangeCalc::updateFromLiveIns() { else { // The value is live-through, update LiveOut as well. // Defer the Domtree lookup until it is needed. - assert(Seen.test(MBB->getNumber())); - Map[MBB] = LiveOutPair(I.Value, nullptr); + assert(LiveOuts.Seen.test(MBB->getNumber())); + LiveOuts.Map[MBB] = LiveOutPair(I.Value, nullptr); } Updater.setDest(&I.LR); Updater.add(Start, End, I.Value); @@ -213,7 +256,8 @@ void LiveRangeCalc::updateFromLiveIns() { } -void LiveRangeCalc::extend(LiveRange &LR, SlotIndex Kill, unsigned PhysReg) { +void LiveRangeCalc::extend(LiveRange &LR, SlotIndex Kill, unsigned PhysReg, + LiveOutData &LiveOuts) { assert(Kill.isValid() && "Invalid SlotIndex"); assert(Indexes && "Missing SlotIndexes"); assert(DomTree && "Missing dominator tree"); @@ -229,27 +273,28 @@ void LiveRangeCalc::extend(LiveRange &LR, SlotIndex Kill, unsigned PhysReg) { // multiple values, and we may need to create even more phi-defs to preserve // VNInfo SSA form. Perform a search for all predecessor blocks where we // know the dominating VNInfo. - if (findReachingDefs(LR, *KillMBB, Kill, PhysReg)) + if (findReachingDefs(LR, *KillMBB, Kill, PhysReg, LiveOuts)) return; // When there were multiple different values, we may need new PHIs. - calculateValues(); + calculateValues(LiveOuts); } // This function is called by a client after using the low-level API to add // live-out and live-in blocks. The unique value optimization is not // available, SplitEditor::transferValues handles that case directly anyway. -void LiveRangeCalc::calculateValues() { +void LiveRangeCalc::calculateValues(LiveOutData &LiveOuts) { assert(Indexes && "Missing SlotIndexes"); assert(DomTree && "Missing dominator tree"); - updateSSA(); - updateFromLiveIns(); + updateSSA(LiveOuts); + updateFromLiveIns(LiveOuts); } bool LiveRangeCalc::findReachingDefs(LiveRange &LR, MachineBasicBlock &KillMBB, - SlotIndex Kill, unsigned PhysReg) { + SlotIndex Kill, unsigned PhysReg, + LiveOutData &LiveOuts) { unsigned KillMBBNum = KillMBB.getNumber(); // Block numbers where LR should be live-in. @@ -283,8 +328,8 @@ bool LiveRangeCalc::findReachingDefs(LiveRange &LR, MachineBasicBlock &KillMBB, MachineBasicBlock *Pred = *PI; // Is this a known live-out block? - if (Seen.test(Pred->getNumber())) { - if (VNInfo *VNI = Map[Pred].first) { + if (LiveOuts.Seen.test(Pred->getNumber())) { + if (VNInfo *VNI = LiveOuts.Map[Pred].first) { if (TheVNI && TheVNI != VNI) UniqueVNI = false; TheVNI = VNI; @@ -298,7 +343,7 @@ bool LiveRangeCalc::findReachingDefs(LiveRange &LR, MachineBasicBlock &KillMBB, // First time we see Pred. Try to determine the live-out value, but set // it as null if Pred is live-through with an unknown value. VNInfo *VNI = LR.extendInBlock(Start, End); - setLiveOutValue(Pred, VNI); + LiveOuts.setLiveOutValue(Pred, VNI); if (VNI) { if (TheVNI && TheVNI != VNI) UniqueVNI = false; @@ -333,7 +378,8 @@ bool LiveRangeCalc::findReachingDefs(LiveRange &LR, MachineBasicBlock &KillMBB, if (*I == KillMBBNum && Kill.isValid()) End = Kill; else - Map[MF->getBlockNumbered(*I)] = LiveOutPair(TheVNI, nullptr); + LiveOuts.Map[MF->getBlockNumbered(*I)] = + LiveOutPair(TheVNI, nullptr); Updater.add(Start, End, TheVNI); } return true; @@ -356,7 +402,7 @@ bool LiveRangeCalc::findReachingDefs(LiveRange &LR, MachineBasicBlock &KillMBB, // This is essentially the same iterative algorithm that SSAUpdater uses, // except we already have a dominator tree, so we don't have to recompute it. -void LiveRangeCalc::updateSSA() { +void LiveRangeCalc::updateSSA(LiveOutData &LiveOuts) { assert(Indexes && "Missing SlotIndexes"); assert(DomTree && "Missing dominator tree"); @@ -377,22 +423,23 @@ void LiveRangeCalc::updateSSA() { // We need a live-in value to a block with no immediate dominator? // This is probably an unreachable block that has survived somehow. - bool needPHI = !IDom || !Seen.test(IDom->getBlock()->getNumber()); + bool needPHI = !IDom + || !LiveOuts.Seen.test(IDom->getBlock()->getNumber()); // IDom dominates all of our predecessors, but it may not be their // immediate dominator. Check if any of them have live-out values that are // properly dominated by IDom. If so, we need a phi-def here. if (!needPHI) { - IDomValue = Map[IDom->getBlock()]; + IDomValue = LiveOuts.Map[IDom->getBlock()]; // Cache the DomTree node that defined the value. if (IDomValue.first && !IDomValue.second) - Map[IDom->getBlock()].second = IDomValue.second = + LiveOuts.Map[IDom->getBlock()].second = IDomValue.second = DomTree->getNode(Indexes->getMBBFromIndex(IDomValue.first->def)); for (MachineBasicBlock::pred_iterator PI = MBB->pred_begin(), PE = MBB->pred_end(); PI != PE; ++PI) { - LiveOutPair &Value = Map[*PI]; + LiveOutPair &Value = LiveOuts.Map[*PI]; if (!Value.first || Value.first == IDomValue.first) continue; @@ -414,7 +461,7 @@ void LiveRangeCalc::updateSSA() { // The value may be live-through even if Kill is set, as can happen when // we are called from extendRange. In that case LiveOutSeen is true, and // LiveOut indicates a foreign or missing value. - LiveOutPair &LOP = Map[MBB]; + LiveOutPair &LOP = LiveOuts.Map[MBB]; // Create a phi-def if required. if (needPHI) { diff --git a/lib/CodeGen/LiveRangeCalc.h b/lib/CodeGen/LiveRangeCalc.h index 913d09edbdd..fd494797918 100644 --- a/lib/CodeGen/LiveRangeCalc.h +++ b/lib/CodeGen/LiveRangeCalc.h @@ -47,30 +47,44 @@ class LiveRangeCalc { /// LiveOutMap - Map basic blocks to the value leaving the block. typedef IndexedMap LiveOutMap; - /// Seen - Bit vector of active entries in LiveOut, also used as a visited - /// set by findReachingDefs. One entry per basic block, indexed by block - /// number. This is kept as a separate bit vector because it can be cleared - /// quickly when switching live ranges. - BitVector Seen; - - /// LiveOut - Map each basic block where a live range is live out to the - /// live-out value and its defining block. - /// - /// For every basic block, MBB, one of these conditions shall be true: - /// - /// 1. !Seen.count(MBB->getNumber()) - /// Blocks without a Seen bit are ignored. - /// 2. LiveOut[MBB].second.getNode() == MBB - /// The live-out value is defined in MBB. - /// 3. forall P in preds(MBB): LiveOut[P] == LiveOut[MBB] - /// The live-out value passses through MBB. All predecessors must carry - /// the same value. - /// - /// The domtree node may be null, it can be computed. - /// - /// The map can be shared by multiple live ranges as long as no two are - /// live-out of the same block. - LiveOutMap Map; + struct LiveOutData { + /// Seen - Bit vector of active entries in LiveOut, also used as a visited + /// set by findReachingDefs. One entry per basic block, indexed by block + /// number. This is kept as a separate bit vector because it can be cleared + /// quickly when switching live ranges. + BitVector Seen; + + /// LiveOut - Map each basic block where a live range is live out to the + /// live-out value and its defining block. + /// + /// For every basic block, MBB, one of these conditions shall be true: + /// + /// 1. !Seen.count(MBB->getNumber()) + /// Blocks without a Seen bit are ignored. + /// 2. LiveOut[MBB].second.getNode() == MBB + /// The live-out value is defined in MBB. + /// 3. forall P in preds(MBB): LiveOut[P] == LiveOut[MBB] + /// The live-out value passses through MBB. All predecessors must carry + /// the same value. + /// + /// The domtree node may be null, it can be computed. + /// + /// The map can be shared by multiple live ranges as long as no two are + /// live-out of the same block. + LiveOutMap Map; + + void reset(unsigned NumBlocks) { + Seen.clear(); + Seen.resize(NumBlocks); + Map.resize(NumBlocks); + } + + void setLiveOutValue(MachineBasicBlock *MBB, VNInfo *VNI) { + Seen.set(MBB->getNumber()); + Map[MBB] = LiveOutPair(VNI, nullptr); + } + }; + LiveOutData MainLiveOutData; /// LiveInBlock - Information about a basic block where a live range is known /// to be live-in, but the value has not yet been determined. @@ -112,24 +126,19 @@ class LiveRangeCalc { /// /// PhysReg, when set, is used to verify live-in lists on basic blocks. bool findReachingDefs(LiveRange &LR, MachineBasicBlock &KillMBB, - SlotIndex Kill, unsigned PhysReg); + SlotIndex Kill, unsigned PhysReg, + LiveOutData &LiveOuts); /// updateSSA - Compute the values that will be live in to all requested /// blocks in LiveIn. Create PHI-def values as required to preserve SSA form. /// /// Every live-in block must be jointly dominated by the added live-out /// blocks. No values are read from the live ranges. - void updateSSA(); + void updateSSA(LiveOutData &LiveOuts); /// Transfer information from the LiveIn vector to the live ranges and update /// the given @p LiveOuts. - void updateFromLiveIns(); - - /// Extend the live range of @p LR to reach all uses of Reg. - /// - /// All uses must be jointly dominated by existing liveness. PHI-defs are - /// inserted as needed to preserve SSA form. - void extendToUses(LiveRange &LR, unsigned Reg, unsigned LaneMask = ~0u); + void updateFromLiveIns(LiveOutData &LiveOuts); public: LiveRangeCalc() : MF(nullptr), MRI(nullptr), Indexes(nullptr), @@ -167,16 +176,39 @@ public: /// single existing value, Alloc may be null. /// /// PhysReg, when set, is used to verify live-in lists on basic blocks. - void extend(LiveRange &LR, SlotIndex Kill, unsigned PhysReg = 0); + void extend(LiveRange &LR, SlotIndex Kill, unsigned PhysReg, + LiveOutData &LiveOuts); - /// Calculates liveness for the uses/defs of a given registers. The results - /// are written to @p LR. - void calculate(LiveRange &LR, unsigned Reg, bool IgnoreUses); + void extend(LiveRange &LR, SlotIndex Kill) { + extend(LR, Kill, 0, MainLiveOutData); + } + + /// createDeadDefs - Create a dead def in LI for every def operand of Reg. + /// Each instruction defining Reg gets a new VNInfo with a corresponding + /// minimal live range. + void createDeadDefs(LiveRange &LR, unsigned Reg); - /// Calculates liveness for the register specified in live interval @p LI. - /// Creates subregister live ranges as needed if subreg liveness tracking is - /// enabled. - void calculate(LiveInterval &LI); + /// Subregister aware version of createDeadDefs(LiveRange &LR, unsigned Reg). + /// If subregister liveness tracking is enabled new subranges are created as + /// necessary when subregister defs are found. As with + /// createDeadDefs(LiveRange &LR, unsigned Reg) new short live segments are + /// created for every def of LI.reg. The new segments start and end at the + /// defining instruction (hence the name "DeadDef"). + void createDeadDefs(LiveInterval &LI); + + /// extendToUses - Extend the live range of LI to reach all uses of Reg. + /// + /// All uses must be jointly dominated by existing liveness. PHI-defs are + /// inserted as needed to preserve SSA form. + void extendToUses(LiveRange &LR, unsigned Reg); + + /// Subregister aware version of extendToUses(LiveRange &LR, unsigned Reg). + /// If subregister liveness tracking is enabled new subranges are created + /// as necessary when subregister uses are found. As with + /// extendToUses(LiveRange &LR, unsigned Reg) the segments existing at the + /// defs are extend until they reach all uses. New value numbers are created + /// at CFG joins as necessary (SSA construction). + void extendToUses(LiveInterval &LI); //===--------------------------------------------------------------------===// // Low-level interface. @@ -198,8 +230,7 @@ public: /// VNI may be null only if MBB is a live-through block also passed to /// addLiveInBlock(). void setLiveOutValue(MachineBasicBlock *MBB, VNInfo *VNI) { - Seen.set(MBB->getNumber()); - Map[MBB] = LiveOutPair(VNI, nullptr); + MainLiveOutData.setLiveOutValue(MBB, VNI); } /// addLiveInBlock - Add a block with an unknown live-in value. This @@ -224,7 +255,11 @@ public: /// /// Every predecessor of a live-in block must have been given a value with /// setLiveOutValue, the value may be null for live-trough blocks. - void calculateValues(); + void calculateValues(LiveOutData &LiveOuts); + + void calculateValues() { + calculateValues(MainLiveOutData); + } }; } // end namespace llvm -- 2.34.1