From 42cb3abaddfcff16ab18b114c3de034839c85e05 Mon Sep 17 00:00:00 2001 From: Zoran Jovanovic Date: Fri, 15 Nov 2013 08:07:34 +0000 Subject: [PATCH] Use instr mapping for microMIPS in llvm-mc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194792 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Mips/MicroMipsInstrFormats.td | 4 ++-- lib/Target/Mips/MipsInstrInfo.td | 10 ++++++--- test/MC/Mips/micromips-trap-instructions.s | 24 +++++++++++----------- 3 files changed, 21 insertions(+), 17 deletions(-) diff --git a/lib/Target/Mips/MicroMipsInstrFormats.td b/lib/Target/Mips/MicroMipsInstrFormats.td index 86470306297..c12a32e3d80 100644 --- a/lib/Target/Mips/MicroMipsInstrFormats.td +++ b/lib/Target/Mips/MicroMipsInstrFormats.td @@ -39,8 +39,8 @@ class SLTI_FM_MM op> : MMArch { bits<32> Inst; let Inst{31-26} = op; - let Inst{25-21} = rs; - let Inst{20-16} = rt; + let Inst{25-21} = rt; + let Inst{20-16} = rs; let Inst{15-0} = imm16; } diff --git a/lib/Target/Mips/MipsInstrInfo.td b/lib/Target/Mips/MipsInstrInfo.td index 02efb3d13f4..ebdbaa416fc 100644 --- a/lib/Target/Mips/MipsInstrInfo.td +++ b/lib/Target/Mips/MipsInstrInfo.td @@ -179,7 +179,7 @@ def RelocPIC : Predicate<"TM.getRelocationModel() == Reloc::PIC_">, def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">, AssemblerPredicate<"FeatureMips32">; def HasStdEnc : Predicate<"Subtarget.hasStandardEncoding()">, - AssemblerPredicate<"!FeatureMips16,!FeatureMicroMips">; + AssemblerPredicate<"!FeatureMips16">; def NotDSP : Predicate<"!Subtarget.hasDSP()">; def InMicroMips : Predicate<"Subtarget.inMicroMipsMode()">, AssemblerPredicate<"FeatureMicroMips">; @@ -958,10 +958,12 @@ def SH : Store<"sh", GPR32Opnd, truncstorei16, IIStore>, MMRel, LW_FM<0x29>; def SW : Store<"sw", GPR32Opnd, store, IIStore>, MMRel, LW_FM<0x2b>; /// load/store left/right +let Predicates = [NotInMicroMips] in { def LWL : LoadLeftRight<"lwl", MipsLWL, GPR32Opnd, IILoad>, LW_FM<0x22>; def LWR : LoadLeftRight<"lwr", MipsLWR, GPR32Opnd, IILoad>, LW_FM<0x26>; def SWL : StoreLeftRight<"swl", MipsSWL, GPR32Opnd, IIStore>, LW_FM<0x2a>; def SWR : StoreLeftRight<"swr", MipsSWR, GPR32Opnd, IIStore>, LW_FM<0x2e>; +} def SYNC : SYNC_FT, SYNC_FM; def TEQ : MMRel, TEQ_FT<"teq", GPR32Opnd>, TEQ_FM<0x34>; @@ -1049,8 +1051,10 @@ def MULT : MMRel, Mult<"mult", IIImult, GPR32Opnd, [HI0, LO0]>, MULT_FM<0, 0x18>; def MULTu : MMRel, Mult<"multu", IIImult, GPR32Opnd, [HI0, LO0]>, MULT_FM<0, 0x19>; -def SDIV : Div<"div", IIIdiv, GPR32Opnd, [HI0, LO0]>, MULT_FM<0, 0x1a>; -def UDIV : Div<"divu", IIIdiv, GPR32Opnd, [HI0, LO0]>, MULT_FM<0, 0x1b>; +def SDIV : MMRel, Div<"div", IIIdiv, GPR32Opnd, [HI0, LO0]>, + MULT_FM<0, 0x1a>; +def UDIV : MMRel, Div<"divu", IIIdiv, GPR32Opnd, [HI0, LO0]>, + MULT_FM<0, 0x1b>; def MTHI : MMRel, MoveToLOHI<"mthi", GPR32Opnd, [HI0]>, MTLO_FM<0x11>; def MTLO : MMRel, MoveToLOHI<"mtlo", GPR32Opnd, [LO0]>, MTLO_FM<0x13>; diff --git a/test/MC/Mips/micromips-trap-instructions.s b/test/MC/Mips/micromips-trap-instructions.s index d26b1b20486..404006c3e4c 100644 --- a/test/MC/Mips/micromips-trap-instructions.s +++ b/test/MC/Mips/micromips-trap-instructions.s @@ -9,12 +9,12 @@ #------------------------------------------------------------------------------ # Little endian #------------------------------------------------------------------------------ -# CHECK-EL: teq $8, $9, 0 # encoding: [0x28,0x01,0x3c,0x00] -# CHECK-EL: tge $8, $9, 0 # encoding: [0x28,0x01,0x3c,0x02] -# CHECK-EL: tgeu $8, $9, 0 # encoding: [0x28,0x01,0x3c,0x04] -# CHECK-EL: tlt $8, $9, 0 # encoding: [0x28,0x01,0x3c,0x08] -# CHECK-EL: tltu $8, $9, 0 # encoding: [0x28,0x01,0x3c,0x0a] -# CHECK-EL: tne $8, $9, 0 # encoding: [0x28,0x01,0x3c,0x0c] +# CHECK-EL: teq $8, $9 # encoding: [0x28,0x01,0x3c,0x00] +# CHECK-EL: tge $8, $9 # encoding: [0x28,0x01,0x3c,0x02] +# CHECK-EL: tgeu $8, $9 # encoding: [0x28,0x01,0x3c,0x04] +# CHECK-EL: tlt $8, $9 # encoding: [0x28,0x01,0x3c,0x08] +# CHECK-EL: tltu $8, $9 # encoding: [0x28,0x01,0x3c,0x0a] +# CHECK-EL: tne $8, $9 # encoding: [0x28,0x01,0x3c,0x0c] # CHECK-EL: teqi $9, 17767 # encoding: [0xc9,0x41,0x67,0x45] # CHECK-EL: tgei $9, 17767 # encoding: [0x29,0x41,0x67,0x45] # CHECK-EL: tgeiu $9, 17767 # encoding: [0x69,0x41,0x67,0x45] @@ -24,12 +24,12 @@ #------------------------------------------------------------------------------ # Big endian #------------------------------------------------------------------------------ -# CHECK-EB: teq $8, $9, 0 # encoding: [0x01,0x28,0x00,0x3c] -# CHECK-EB: tge $8, $9, 0 # encoding: [0x01,0x28,0x02,0x3c] -# CHECK-EB: tgeu $8, $9, 0 # encoding: [0x01,0x28,0x04,0x3c] -# CHECK-EB: tlt $8, $9, 0 # encoding: [0x01,0x28,0x08,0x3c] -# CHECK-EB: tltu $8, $9, 0 # encoding: [0x01,0x28,0x0a,0x3c] -# CHECK-EB: tne $8, $9, 0 # encoding: [0x01,0x28,0x0c,0x3c] +# CHECK-EB: teq $8, $9 # encoding: [0x01,0x28,0x00,0x3c] +# CHECK-EB: tge $8, $9 # encoding: [0x01,0x28,0x02,0x3c] +# CHECK-EB: tgeu $8, $9 # encoding: [0x01,0x28,0x04,0x3c] +# CHECK-EB: tlt $8, $9 # encoding: [0x01,0x28,0x08,0x3c] +# CHECK-EB: tltu $8, $9 # encoding: [0x01,0x28,0x0a,0x3c] +# CHECK-EB: tne $8, $9 # encoding: [0x01,0x28,0x0c,0x3c] # CHECK-EB: teqi $9, 17767 # encoding: [0x41,0xc9,0x45,0x67] # CHECK-EB: tgei $9, 17767 # encoding: [0x41,0x29,0x45,0x67] # CHECK-EB: tgeiu $9, 17767 # encoding: [0x41,0x69,0x45,0x67] -- 2.34.1