From 43ecf2d4d1d9c89b0a7519708bfce9c728d51f08 Mon Sep 17 00:00:00 2001 From: Oliver Stannard Date: Wed, 9 Dec 2015 14:32:11 +0000 Subject: [PATCH] [AArch64] Fix FP16 vector instructions that should only accept low registers git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@255113 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/AArch64/AArch64InstrFormats.td | 6 ++-- test/MC/AArch64/fullfp16-diagnostics.s | 40 +++++++++++++++++++++++ 2 files changed, 43 insertions(+), 3 deletions(-) diff --git a/lib/Target/AArch64/AArch64InstrFormats.td b/lib/Target/AArch64/AArch64InstrFormats.td index 101b0f7e1d3..6ac2175e503 100644 --- a/lib/Target/AArch64/AArch64InstrFormats.td +++ b/lib/Target/AArch64/AArch64InstrFormats.td @@ -6855,11 +6855,11 @@ multiclass SIMDFPIndexed opc, string asm, let Predicates = [HasNEON, HasFullFP16] in { def v1i16_indexed : BaseSIMDIndexed<1, U, 1, 0b00, opc, - FPR16Op, FPR16Op, V128, VectorIndexH, + FPR16Op, FPR16Op, V128_lo, VectorIndexH, asm, ".h", "", "", ".h", [(set (f16 FPR16Op:$Rd), (OpNode (f16 FPR16Op:$Rn), - (f16 (vector_extract (v8f16 V128:$Rm), + (f16 (vector_extract (v8f16 V128_lo:$Rm), VectorIndexH:$idx))))]> { bits<3> idx; let Inst{11} = idx{2}; @@ -6995,7 +6995,7 @@ multiclass SIMDFPIndexedTied opc, string asm> { let Predicates = [HasNEON, HasFullFP16] in { def v1i16_indexed : BaseSIMDIndexedTied<1, U, 1, 0b00, opc, - FPR16Op, FPR16Op, V128, VectorIndexH, + FPR16Op, FPR16Op, V128_lo, VectorIndexH, asm, ".h", "", "", ".h", []> { bits<3> idx; let Inst{11} = idx{2}; diff --git a/test/MC/AArch64/fullfp16-diagnostics.s b/test/MC/AArch64/fullfp16-diagnostics.s index 190b6e25a4b..06035dbf702 100644 --- a/test/MC/AArch64/fullfp16-diagnostics.s +++ b/test/MC/AArch64/fullfp16-diagnostics.s @@ -40,3 +40,43 @@ // CHECK: error: invalid operand for instruction // CHECK-NEXT: fmulx v2.8h, v3.8h, v17.h[6] // CHECK-NEXT: ^ + + fmla h0, h1, v16.h[3] + fmla h2, h3, v17.h[6] + +// CHECK: error: invalid operand for instruction +// CHECK-NEXT: fmla h0, h1, v16.h[3] +// CHECK-NEXT: ^ +// CHECK: error: invalid operand for instruction +// CHECK-NEXT: fmla h2, h3, v17.h[6] +// CHECK-NEXT: ^ + + fmls h0, h1, v16.h[3] + fmls h2, h3, v17.h[6] + +// CHECK: error: invalid operand for instruction +// CHECK-NEXT: fmls h0, h1, v16.h[3] +// CHECK-NEXT: ^ +// CHECK: error: invalid operand for instruction +// CHECK-NEXT: fmls h2, h3, v17.h[6] +// CHECK-NEXT: ^ + + fmul h0, h1, v16.h[3] + fmul h2, h3, v17.h[6] + +// CHECK: error: invalid operand for instruction +// CHECK-NEXT: fmul h0, h1, v16.h[3] +// CHECK-NEXT: ^ +// CHECK: error: invalid operand for instruction +// CHECK-NEXT: fmul h2, h3, v17.h[6] +// CHECK-NEXT: ^ + + fmulx h0, h1, v16.h[3] + fmulx h2, h3, v17.h[6] + +// CHECK: error: invalid operand for instruction +// CHECK-NEXT: fmulx h0, h1, v16.h[3] +// CHECK-NEXT: ^ +// CHECK: error: invalid operand for instruction +// CHECK-NEXT: fmulx h2, h3, v17.h[6] +// CHECK-NEXT: ^ -- 2.34.1