From 45924e87a9d6fccd974341b4328b1a37a7ad5ef5 Mon Sep 17 00:00:00 2001 From: zwl Date: Thu, 24 Jul 2014 09:11:54 +0800 Subject: [PATCH] rk312x lcdc: rename rk31xx_lcdc to rk312x_lcdc and change defined BIT to BITS --- .../lcdc/{rk31xx_lcdc.c => rk312x_lcdc.c} | 224 +++--- drivers/video/rockchip/lcdc/rk312x_lcdc.h | 736 +++++++++++++++++ drivers/video/rockchip/lcdc/rk31xx_lcdc.h | 742 ------------------ 3 files changed, 848 insertions(+), 854 deletions(-) rename drivers/video/rockchip/lcdc/{rk31xx_lcdc.c => rk312x_lcdc.c} (89%) create mode 100755 drivers/video/rockchip/lcdc/rk312x_lcdc.h delete mode 100755 drivers/video/rockchip/lcdc/rk31xx_lcdc.h diff --git a/drivers/video/rockchip/lcdc/rk31xx_lcdc.c b/drivers/video/rockchip/lcdc/rk312x_lcdc.c similarity index 89% rename from drivers/video/rockchip/lcdc/rk31xx_lcdc.c rename to drivers/video/rockchip/lcdc/rk312x_lcdc.c index e7057e5d0a09..071e956a3bff 100755 --- a/drivers/video/rockchip/lcdc/rk31xx_lcdc.c +++ b/drivers/video/rockchip/lcdc/rk312x_lcdc.c @@ -1,5 +1,5 @@ /* - * drivers/video/rockchip/lcdc/rk31xx_lcdc.c + * drivers/video/rockchip/lcdc/rk312x_lcdc.c * * Copyright (C) 2014 ROCKCHIP, Inc. * Author: zhuangwenlong @@ -38,7 +38,7 @@ #include #include #endif -#include "rk31xx_lcdc.h" +#include "rk312x_lcdc.h" static int dbg_thresd; module_param(dbg_thresd, int, S_IRUGO | S_IWUSR); @@ -65,7 +65,7 @@ static struct rk_lcdc_win lcdc_win[] = { }, }; -static irqreturn_t rk31xx_lcdc_isr(int irq, void *dev_id) +static irqreturn_t rk312x_lcdc_isr(int irq, void *dev_id) { struct lcdc_device *lcdc_dev = (struct lcdc_device *)dev_id; ktime_t timestamp = ktime_get(); @@ -91,7 +91,7 @@ static irqreturn_t rk31xx_lcdc_isr(int irq, void *dev_id) return IRQ_HANDLED; } -static int rk31xx_lcdc_clk_enable(struct lcdc_device *lcdc_dev) +static int rk312x_lcdc_clk_enable(struct lcdc_device *lcdc_dev) { #ifdef CONFIG_RK_FPGA lcdc_dev->clk_on = 1; @@ -110,7 +110,7 @@ static int rk31xx_lcdc_clk_enable(struct lcdc_device *lcdc_dev) return 0; } -static int rk31xx_lcdc_clk_disable(struct lcdc_device *lcdc_dev) +static int rk312x_lcdc_clk_disable(struct lcdc_device *lcdc_dev) { #ifdef CONFIG_RK_FPGA lcdc_dev->clk_on = 0; @@ -130,7 +130,7 @@ static int rk31xx_lcdc_clk_disable(struct lcdc_device *lcdc_dev) return 0; } -static int rk31xx_lcdc_enable_irq(struct rk_lcdc_driver *dev_drv) +static int rk312x_lcdc_enable_irq(struct rk_lcdc_driver *dev_drv) { u32 mask, val; struct lcdc_device *lcdc_dev = container_of(dev_drv, @@ -156,7 +156,7 @@ static int rk31xx_lcdc_enable_irq(struct rk_lcdc_driver *dev_drv) return 0; } -static int rk31xx_lcdc_disable_irq(struct lcdc_device *lcdc_dev) +static int rk312x_lcdc_disable_irq(struct lcdc_device *lcdc_dev) { u32 mask, val; @@ -189,7 +189,7 @@ static void rk_lcdc_read_reg_defalut_cfg(struct lcdc_device *lcdc_dev) spin_unlock(&lcdc_dev->reg_lock); } -static int rk31xx_lcdc_alpha_cfg(struct lcdc_device *lcdc_dev) +static int rk312x_lcdc_alpha_cfg(struct lcdc_device *lcdc_dev) { int win0_top = 0; u32 mask, val; @@ -343,7 +343,7 @@ static void lcdc_layer_enable(struct lcdc_device *lcdc_dev, unsigned int win_id, spin_unlock(&lcdc_dev->reg_lock); } -static int rk31xx_lcdc_reg_update(struct rk_lcdc_driver *dev_drv) +static int rk312x_lcdc_reg_update(struct rk_lcdc_driver *dev_drv) { struct lcdc_device *lcdc_dev = container_of(dev_drv, struct lcdc_device, driver); @@ -357,7 +357,7 @@ static int rk31xx_lcdc_reg_update(struct rk_lcdc_driver *dev_drv) v_LCDC_STANDBY(lcdc_dev->standby)); lcdc_layer_update_regs(lcdc_dev, win0); lcdc_layer_update_regs(lcdc_dev, win1); - rk31xx_lcdc_alpha_cfg(lcdc_dev); + rk312x_lcdc_alpha_cfg(lcdc_dev); lcdc_cfg_done(lcdc_dev); } @@ -382,12 +382,12 @@ static int rk31xx_lcdc_reg_update(struct rk_lcdc_driver *dev_drv) } -static void rk31xx_lcdc_reg_restore(struct lcdc_device *lcdc_dev) +static void rk312x_lcdc_reg_restore(struct lcdc_device *lcdc_dev) { memcpy((u8 *) lcdc_dev->regs, (u8 *) lcdc_dev->regsbak, 0xdc); } -static void rk31xx_lcdc_mmu_en(struct rk_lcdc_driver *dev_drv) +static void rk312x_lcdc_mmu_en(struct rk_lcdc_driver *dev_drv) { u32 mask, val; struct lcdc_device *lcdc_dev = @@ -404,7 +404,7 @@ static void rk31xx_lcdc_mmu_en(struct rk_lcdc_driver *dev_drv) spin_unlock(&lcdc_dev->reg_lock); } -static int rk31xx_lcdc_set_lut(struct rk_lcdc_driver *dev_drv) +static int rk312x_lcdc_set_lut(struct rk_lcdc_driver *dev_drv) { int i = 0; int __iomem *c; @@ -429,7 +429,7 @@ static int rk31xx_lcdc_set_lut(struct rk_lcdc_driver *dev_drv) } -static int rk31xx_lcdc_set_dclk(struct rk_lcdc_driver *dev_drv) +static int rk312x_lcdc_set_dclk(struct rk_lcdc_driver *dev_drv) { #ifdef CONFIG_RK_FPGA return 0; @@ -455,7 +455,7 @@ static int rk31xx_lcdc_set_dclk(struct rk_lcdc_driver *dev_drv) } /********do basic init*********/ -static int rk31xx_lcdc_pre_init(struct rk_lcdc_driver *dev_drv) +static int rk312x_lcdc_pre_init(struct rk_lcdc_driver *dev_drv) { struct lcdc_device *lcdc_dev = container_of(dev_drv, struct lcdc_device, driver); @@ -474,7 +474,7 @@ static int rk31xx_lcdc_pre_init(struct rk_lcdc_driver *dev_drv) } rk_disp_pwr_enable(dev_drv); - rk31xx_lcdc_clk_enable(lcdc_dev); + rk312x_lcdc_clk_enable(lcdc_dev); /* backup reg config at uboot */ rk_lcdc_read_reg_defalut_cfg(lcdc_dev); @@ -487,7 +487,7 @@ static int rk31xx_lcdc_pre_init(struct rk_lcdc_driver *dev_drv) return 0; } -static void rk31xx_lcdc_deinit(struct lcdc_device *lcdc_dev) +static void rk312x_lcdc_deinit(struct lcdc_device *lcdc_dev) { u32 mask, val; @@ -723,7 +723,7 @@ static int rk31xx_load_screen(struct rk_lcdc_driver *dev_drv, bool initscreen) } spin_unlock(&lcdc_dev->reg_lock); - rk31xx_lcdc_set_dclk(dev_drv); + rk312x_lcdc_set_dclk(dev_drv); if (dev_drv->trsm_ops && dev_drv->trsm_ops->enable) dev_drv->trsm_ops->enable(); if (screen->init) @@ -732,7 +732,7 @@ static int rk31xx_load_screen(struct rk_lcdc_driver *dev_drv, bool initscreen) return 0; } -static int rk31xx_lcdc_open(struct rk_lcdc_driver *dev_drv, int win_id, +static int rk312x_lcdc_open(struct rk_lcdc_driver *dev_drv, int win_id, bool open) { struct lcdc_device *lcdc_dev = container_of(dev_drv, @@ -741,7 +741,7 @@ static int rk31xx_lcdc_open(struct rk_lcdc_driver *dev_drv, int win_id, /* enable clk,when first layer open */ if ((open) && (!lcdc_dev->atv_layer_cnt)) { rockchip_set_system_status(SYS_STATUS_LCDC0); - rk31xx_lcdc_pre_init(dev_drv); + rk312x_lcdc_pre_init(dev_drv); #if defined(CONFIG_ROCKCHIP_IOMMU) if (dev_drv->iommu_enabled) { if (!dev_drv->mmu_dev) { @@ -760,19 +760,19 @@ static int rk31xx_lcdc_open(struct rk_lcdc_driver *dev_drv, int win_id, iovmm_activate(dev_drv->dev); } #endif - rk31xx_lcdc_reg_restore(lcdc_dev); + rk312x_lcdc_reg_restore(lcdc_dev); if (dev_drv->iommu_enabled) - rk31xx_lcdc_mmu_en(dev_drv); + rk312x_lcdc_mmu_en(dev_drv); if ((support_uboot_display() && (lcdc_dev->prop == PRMRY))) { - rk31xx_lcdc_set_dclk(dev_drv); - rk31xx_lcdc_enable_irq(dev_drv); + rk312x_lcdc_set_dclk(dev_drv); + rk312x_lcdc_enable_irq(dev_drv); } else { rk31xx_load_screen(dev_drv, 1); } /* set screen lut */ if (dev_drv->cur_screen->dsp_lut) - rk31xx_lcdc_set_lut(dev_drv); + rk312x_lcdc_set_lut(dev_drv); } if (win_id < ARRAY_SIZE(lcdc_win)) @@ -782,22 +782,22 @@ static int rk31xx_lcdc_open(struct rk_lcdc_driver *dev_drv, int win_id, /* when all layer closed,disable clk */ if ((!open) && (!lcdc_dev->atv_layer_cnt)) { - rk31xx_lcdc_disable_irq(lcdc_dev); - rk31xx_lcdc_reg_update(dev_drv); + rk312x_lcdc_disable_irq(lcdc_dev); + rk312x_lcdc_reg_update(dev_drv); #if defined(CONFIG_ROCKCHIP_IOMMU) if (dev_drv->iommu_enabled) { if (dev_drv->mmu_dev) iovmm_deactivate(dev_drv->dev); } #endif - rk31xx_lcdc_clk_disable(lcdc_dev); + rk312x_lcdc_clk_disable(lcdc_dev); rockchip_clear_system_status(SYS_STATUS_LCDC0); } return 0; } -static int rk31xx_lcdc_set_par(struct rk_lcdc_driver *dev_drv, int win_id) +static int rk312x_lcdc_set_par(struct rk_lcdc_driver *dev_drv, int win_id) { struct lcdc_device *lcdc_dev = container_of(dev_drv, struct lcdc_device, driver); @@ -911,7 +911,7 @@ static int rk31xx_lcdc_set_par(struct rk_lcdc_driver *dev_drv, int win_id) return 0; } -static int rk31xx_lcdc_pan_display(struct rk_lcdc_driver *dev_drv, int win_id) +static int rk312x_lcdc_pan_display(struct rk_lcdc_driver *dev_drv, int win_id) { struct lcdc_device *lcdc_dev = container_of(dev_drv, struct lcdc_device, driver); @@ -950,14 +950,14 @@ static int rk31xx_lcdc_pan_display(struct rk_lcdc_driver *dev_drv, int win_id) /* this is the first frame of the system,enable frame start interrupt */ if ((dev_drv->first_frame)) { dev_drv->first_frame = 0; - rk31xx_lcdc_enable_irq(dev_drv); + rk312x_lcdc_enable_irq(dev_drv); } return 0; } -static int rk31xx_lcdc_ioctl(struct rk_lcdc_driver *dev_drv, unsigned int cmd, +static int rk312x_lcdc_ioctl(struct rk_lcdc_driver *dev_drv, unsigned int cmd, unsigned long arg, int win_id) { struct lcdc_device *lcdc_dev = container_of(dev_drv, @@ -989,7 +989,7 @@ static int rk31xx_lcdc_ioctl(struct rk_lcdc_driver *dev_drv, unsigned int cmd, return 0; } -static int rk31xx_lcdc_get_win_id(struct rk_lcdc_driver *dev_drv, +static int rk312x_lcdc_get_win_id(struct rk_lcdc_driver *dev_drv, const char *id) { int win_id = 0; @@ -1005,12 +1005,12 @@ static int rk31xx_lcdc_get_win_id(struct rk_lcdc_driver *dev_drv, return win_id; } -static int rk31xx_lcdc_get_win_state(struct rk_lcdc_driver *dev_drv, int win_id) +static int rk312x_lcdc_get_win_state(struct rk_lcdc_driver *dev_drv, int win_id) { return 0; } -static int rk31xx_lcdc_ovl_mgr(struct rk_lcdc_driver *dev_drv, int swap, +static int rk312x_lcdc_ovl_mgr(struct rk_lcdc_driver *dev_drv, int swap, bool set) { struct lcdc_device *lcdc_dev = @@ -1033,7 +1033,7 @@ static int rk31xx_lcdc_ovl_mgr(struct rk_lcdc_driver *dev_drv, int swap, return ovl; } -static int rk31xx_lcdc_early_suspend(struct rk_lcdc_driver *dev_drv) +static int rk312x_lcdc_early_suspend(struct rk_lcdc_driver *dev_drv) { struct lcdc_device *lcdc_dev = container_of(dev_drv, @@ -1067,12 +1067,12 @@ static int rk31xx_lcdc_early_suspend(struct rk_lcdc_driver *dev_drv) spin_unlock(&lcdc_dev->reg_lock); return 0; } - rk31xx_lcdc_clk_disable(lcdc_dev); + rk312x_lcdc_clk_disable(lcdc_dev); rk_disp_pwr_disable(dev_drv); return 0; } -static int rk31xx_lcdc_early_resume(struct rk_lcdc_driver *dev_drv) +static int rk312x_lcdc_early_resume(struct rk_lcdc_driver *dev_drv) { struct lcdc_device *lcdc_dev = container_of(dev_drv, struct lcdc_device, driver); @@ -1083,11 +1083,11 @@ static int rk31xx_lcdc_early_resume(struct rk_lcdc_driver *dev_drv) dev_drv->suspend_flag = 0; if (lcdc_dev->atv_layer_cnt) { - rk31xx_lcdc_clk_enable(lcdc_dev); - rk31xx_lcdc_reg_restore(lcdc_dev); + rk312x_lcdc_clk_enable(lcdc_dev); + rk312x_lcdc_reg_restore(lcdc_dev); /* set screen lut */ if (dev_drv->cur_screen->dsp_lut) - rk31xx_lcdc_set_lut(dev_drv); + rk312x_lcdc_set_lut(dev_drv); spin_lock(&lcdc_dev->reg_lock); @@ -1106,18 +1106,18 @@ static int rk31xx_lcdc_early_resume(struct rk_lcdc_driver *dev_drv) return 0; } -static int rk31xx_lcdc_blank(struct rk_lcdc_driver *dev_drv, +static int rk312x_lcdc_blank(struct rk_lcdc_driver *dev_drv, int win_id, int blank_mode) { switch (blank_mode) { case FB_BLANK_UNBLANK: - rk31xx_lcdc_early_resume(dev_drv); + rk312x_lcdc_early_resume(dev_drv); break; case FB_BLANK_NORMAL: - rk31xx_lcdc_early_suspend(dev_drv); + rk312x_lcdc_early_suspend(dev_drv); break; default: - rk31xx_lcdc_early_suspend(dev_drv); + rk312x_lcdc_early_suspend(dev_drv); break; } @@ -1126,7 +1126,7 @@ static int rk31xx_lcdc_blank(struct rk_lcdc_driver *dev_drv, return 0; } -static int rk31xx_lcdc_cfg_done(struct rk_lcdc_driver *dev_drv) +static int rk312x_lcdc_cfg_done(struct rk_lcdc_driver *dev_drv) { struct lcdc_device *lcdc_dev = container_of(dev_drv, struct lcdc_device, driver); @@ -1145,7 +1145,7 @@ static int rk31xx_lcdc_cfg_done(struct rk_lcdc_driver *dev_drv) sin_hue = sin(a)*256; cos_hue = cos(a)*256; */ -static int rk31xx_lcdc_get_bcsh_hue(struct rk_lcdc_driver *dev_drv, +static int rk312x_lcdc_get_bcsh_hue(struct rk_lcdc_driver *dev_drv, bcsh_hue_mode mode) { @@ -1173,7 +1173,7 @@ static int rk31xx_lcdc_get_bcsh_hue(struct rk_lcdc_driver *dev_drv, return val; } -static int rk31xx_lcdc_set_bcsh_hue(struct rk_lcdc_driver *dev_drv, int sin_hue, +static int rk312x_lcdc_set_bcsh_hue(struct rk_lcdc_driver *dev_drv, int sin_hue, int cos_hue) { @@ -1193,7 +1193,7 @@ static int rk31xx_lcdc_set_bcsh_hue(struct rk_lcdc_driver *dev_drv, int sin_hue, return 0; } -static int rk31xx_lcdc_set_bcsh_bcs(struct rk_lcdc_driver *dev_drv, +static int rk312x_lcdc_set_bcsh_bcs(struct rk_lcdc_driver *dev_drv, bcsh_bcs_mode mode, int value) { struct lcdc_device *lcdc_dev = @@ -1232,7 +1232,7 @@ static int rk31xx_lcdc_set_bcsh_bcs(struct rk_lcdc_driver *dev_drv, return val; } -static int rk31xx_lcdc_get_bcsh_bcs(struct rk_lcdc_driver *dev_drv, +static int rk312x_lcdc_get_bcsh_bcs(struct rk_lcdc_driver *dev_drv, bcsh_bcs_mode mode) { struct lcdc_device *lcdc_dev = @@ -1266,7 +1266,7 @@ static int rk31xx_lcdc_get_bcsh_bcs(struct rk_lcdc_driver *dev_drv, return val; } -static int rk31xx_lcdc_open_bcsh(struct rk_lcdc_driver *dev_drv, bool open) +static int rk312x_lcdc_open_bcsh(struct rk_lcdc_driver *dev_drv, bool open) { struct lcdc_device *lcdc_dev = container_of(dev_drv, struct lcdc_device, driver); @@ -1303,7 +1303,7 @@ static int rk31xx_fb_win_remap(struct rk_lcdc_driver *dev_drv, return 0; } -static int rk31xx_lcdc_fps_mgr(struct rk_lcdc_driver *dev_drv, int fps, +static int rk312x_lcdc_fps_mgr(struct rk_lcdc_driver *dev_drv, int fps, bool set) { struct lcdc_device *lcdc_dev = @@ -1339,7 +1339,7 @@ static int rk31xx_lcdc_fps_mgr(struct rk_lcdc_driver *dev_drv, int fps, return fps; } -static int rk31xx_lcdc_poll_vblank(struct rk_lcdc_driver *dev_drv) +static int rk312x_lcdc_poll_vblank(struct rk_lcdc_driver *dev_drv) { struct lcdc_device *lcdc_dev = container_of(dev_drv, struct lcdc_device, driver); @@ -1364,7 +1364,7 @@ static int rk31xx_lcdc_poll_vblank(struct rk_lcdc_driver *dev_drv) return ret; } -static int rk31xx_lcdc_get_dsp_addr(struct rk_lcdc_driver *dev_drv, +static int rk312x_lcdc_get_dsp_addr(struct rk_lcdc_driver *dev_drv, unsigned int *dsp_addr) { struct lcdc_device *lcdc_dev = @@ -1380,7 +1380,7 @@ static int rk31xx_lcdc_get_dsp_addr(struct rk_lcdc_driver *dev_drv, return 0; } -static ssize_t rk31xx_lcdc_get_disp_info(struct rk_lcdc_driver *dev_drv, +static ssize_t rk312x_lcdc_get_disp_info(struct rk_lcdc_driver *dev_drv, char *buf, int win_id) { struct lcdc_device *lcdc_dev = container_of(dev_drv, struct lcdc_device, @@ -1523,7 +1523,7 @@ static ssize_t rk31xx_lcdc_get_disp_info(struct rk_lcdc_driver *dev_drv, "win1 on the top of win0\n"); } -static int rk31xx_lcdc_reg_dump(struct rk_lcdc_driver *dev_drv) +static int rk312x_lcdc_reg_dump(struct rk_lcdc_driver *dev_drv) { struct lcdc_device *lcdc_dev = container_of(dev_drv, struct lcdc_device, @@ -1548,7 +1548,7 @@ static int rk31xx_lcdc_reg_dump(struct rk_lcdc_driver *dev_drv) return 0; } -static int rk31xx_lcdc_dpi_open(struct rk_lcdc_driver *dev_drv, bool open) +static int rk312x_lcdc_dpi_open(struct rk_lcdc_driver *dev_drv, bool open) { struct lcdc_device *lcdc_dev = container_of(dev_drv, struct lcdc_device, driver); @@ -1560,7 +1560,7 @@ static int rk31xx_lcdc_dpi_open(struct rk_lcdc_driver *dev_drv, bool open) return 0; } -static int rk31xx_lcdc_dpi_win_sel(struct rk_lcdc_driver *dev_drv, int win_id) +static int rk312x_lcdc_dpi_win_sel(struct rk_lcdc_driver *dev_drv, int win_id) { struct lcdc_device *lcdc_dev = container_of(dev_drv, struct lcdc_device, driver); @@ -1574,7 +1574,7 @@ static int rk31xx_lcdc_dpi_win_sel(struct rk_lcdc_driver *dev_drv, int win_id) } -static int rk31xx_lcdc_dpi_status(struct rk_lcdc_driver *dev_drv) +static int rk312x_lcdc_dpi_status(struct rk_lcdc_driver *dev_drv) { struct lcdc_device *lcdc_dev = container_of(dev_drv, struct lcdc_device, driver); @@ -1587,30 +1587,30 @@ static int rk31xx_lcdc_dpi_status(struct rk_lcdc_driver *dev_drv) } static struct rk_lcdc_drv_ops lcdc_drv_ops = { - .open = rk31xx_lcdc_open, + .open = rk312x_lcdc_open, .load_screen = rk31xx_load_screen, - .set_par = rk31xx_lcdc_set_par, - .pan_display = rk31xx_lcdc_pan_display, - .blank = rk31xx_lcdc_blank, - .ioctl = rk31xx_lcdc_ioctl, - .get_win_state = rk31xx_lcdc_get_win_state, - .ovl_mgr = rk31xx_lcdc_ovl_mgr, - .get_disp_info = rk31xx_lcdc_get_disp_info, - .fps_mgr = rk31xx_lcdc_fps_mgr, - .fb_get_win_id = rk31xx_lcdc_get_win_id, + .set_par = rk312x_lcdc_set_par, + .pan_display = rk312x_lcdc_pan_display, + .blank = rk312x_lcdc_blank, + .ioctl = rk312x_lcdc_ioctl, + .get_win_state = rk312x_lcdc_get_win_state, + .ovl_mgr = rk312x_lcdc_ovl_mgr, + .get_disp_info = rk312x_lcdc_get_disp_info, + .fps_mgr = rk312x_lcdc_fps_mgr, + .fb_get_win_id = rk312x_lcdc_get_win_id, .fb_win_remap = rk31xx_fb_win_remap, - .poll_vblank = rk31xx_lcdc_poll_vblank, - .get_dsp_addr = rk31xx_lcdc_get_dsp_addr, - .cfg_done = rk31xx_lcdc_cfg_done, - .dump_reg = rk31xx_lcdc_reg_dump, - .dpi_open = rk31xx_lcdc_dpi_open, - .dpi_win_sel = rk31xx_lcdc_dpi_win_sel, - .dpi_status = rk31xx_lcdc_dpi_status, - .set_dsp_bcsh_hue = rk31xx_lcdc_set_bcsh_hue, - .set_dsp_bcsh_bcs = rk31xx_lcdc_set_bcsh_bcs, - .get_dsp_bcsh_hue = rk31xx_lcdc_get_bcsh_hue, - .get_dsp_bcsh_bcs = rk31xx_lcdc_get_bcsh_bcs, - .open_bcsh = rk31xx_lcdc_open_bcsh, + .poll_vblank = rk312x_lcdc_poll_vblank, + .get_dsp_addr = rk312x_lcdc_get_dsp_addr, + .cfg_done = rk312x_lcdc_cfg_done, + .dump_reg = rk312x_lcdc_reg_dump, + .dpi_open = rk312x_lcdc_dpi_open, + .dpi_win_sel = rk312x_lcdc_dpi_win_sel, + .dpi_status = rk312x_lcdc_dpi_status, + .set_dsp_bcsh_hue = rk312x_lcdc_set_bcsh_hue, + .set_dsp_bcsh_bcs = rk312x_lcdc_set_bcsh_bcs, + .get_dsp_bcsh_hue = rk312x_lcdc_get_bcsh_hue, + .get_dsp_bcsh_bcs = rk312x_lcdc_get_bcsh_bcs, + .open_bcsh = rk312x_lcdc_open_bcsh, }; static const struct rk_lcdc_drvdata rk3036_lcdc_drvdata = { @@ -1622,7 +1622,7 @@ static const struct rk_lcdc_drvdata rk312x_lcdc_drvdata = { }; #if defined(CONFIG_OF) -static const struct of_device_id rk31xx_lcdc_dt_ids[] = { +static const struct of_device_id rk312x_lcdc_dt_ids[] = { { .compatible = "rockchip,rk3036-lcdc", .data = (void *)&rk3036_lcdc_drvdata, @@ -1634,7 +1634,7 @@ static const struct of_device_id rk31xx_lcdc_dt_ids[] = { }; #endif -static int rk31xx_lcdc_parse_dt(struct lcdc_device *lcdc_dev) +static int rk312x_lcdc_parse_dt(struct lcdc_device *lcdc_dev) { struct device_node *np = lcdc_dev->dev->of_node; const struct of_device_id *match; @@ -1649,7 +1649,7 @@ static int rk31xx_lcdc_parse_dt(struct lcdc_device *lcdc_dev) #else lcdc_dev->driver.iommu_enabled = 0; #endif - match = of_match_node(rk31xx_lcdc_dt_ids, np); + match = of_match_node(rk312x_lcdc_dt_ids, np); if (match) { lcdc_drvdata = (const struct rk_lcdc_drvdata *)match->data; lcdc_dev->soc_type = lcdc_drvdata->soc_type; @@ -1660,7 +1660,7 @@ static int rk31xx_lcdc_parse_dt(struct lcdc_device *lcdc_dev) return 0; } -static int rk31xx_lcdc_probe(struct platform_device *pdev) +static int rk312x_lcdc_probe(struct platform_device *pdev) { struct lcdc_device *lcdc_dev = NULL; struct rk_lcdc_driver *dev_drv; @@ -1670,13 +1670,13 @@ static int rk31xx_lcdc_probe(struct platform_device *pdev) lcdc_dev = devm_kzalloc(dev, sizeof(struct lcdc_device), GFP_KERNEL); if (!lcdc_dev) { - dev_err(&pdev->dev, "rk31xx lcdc device kzalloc fail!\n"); + dev_err(&pdev->dev, "rk312x lcdc device kzalloc fail!\n"); return -ENOMEM; } platform_set_drvdata(pdev, lcdc_dev); lcdc_dev->dev = dev; - if (rk31xx_lcdc_parse_dt(lcdc_dev)) { - dev_err(lcdc_dev->dev, "rk31xx lcdc parse dt failed!\n"); + if (rk312x_lcdc_parse_dt(lcdc_dev)) { + dev_err(lcdc_dev->dev, "rk312x lcdc parse dt failed!\n"); goto err_parse_dt; } @@ -1691,7 +1691,7 @@ static int rk31xx_lcdc_probe(struct platform_device *pdev) lcdc_dev->regsbak = devm_kzalloc(dev, lcdc_dev->len, GFP_KERNEL); if (IS_ERR(lcdc_dev->regsbak)) { - dev_err(&pdev->dev, "rk31xx lcdc device kmalloc fail!\n"); + dev_err(&pdev->dev, "rk312x lcdc device kmalloc fail!\n"); ret = PTR_ERR(lcdc_dev->regsbak); goto err_remap_reg; } @@ -1713,7 +1713,7 @@ static int rk31xx_lcdc_probe(struct platform_device *pdev) goto err_request_irq; } - ret = devm_request_irq(dev, lcdc_dev->irq, rk31xx_lcdc_isr, + ret = devm_request_irq(dev, lcdc_dev->irq, rk312x_lcdc_isr, IRQF_DISABLED, dev_name(dev), lcdc_dev); if (ret) { dev_err(&pdev->dev, "cannot requeset irq %d - err %d\n", @@ -1745,56 +1745,56 @@ err_parse_dt: } #if defined(CONFIG_PM) -static int rk31xx_lcdc_suspend(struct platform_device *pdev, pm_message_t state) +static int rk312x_lcdc_suspend(struct platform_device *pdev, pm_message_t state) { return 0; } -static int rk31xx_lcdc_resume(struct platform_device *pdev) +static int rk312x_lcdc_resume(struct platform_device *pdev) { return 0; } #else -#define rk31xx_lcdc_suspend NULL -#define rk31xx_lcdc_resume NULL +#define rk312x_lcdc_suspend NULL +#define rk312x_lcdc_resume NULL #endif -static int rk31xx_lcdc_remove(struct platform_device *pdev) +static int rk312x_lcdc_remove(struct platform_device *pdev) { return 0; } -static void rk31xx_lcdc_shutdown(struct platform_device *pdev) +static void rk312x_lcdc_shutdown(struct platform_device *pdev) { struct lcdc_device *lcdc_dev = platform_get_drvdata(pdev); - rk31xx_lcdc_deinit(lcdc_dev); - rk31xx_lcdc_clk_disable(lcdc_dev); + rk312x_lcdc_deinit(lcdc_dev); + rk312x_lcdc_clk_disable(lcdc_dev); rk_disp_pwr_disable(&lcdc_dev->driver); } -static struct platform_driver rk31xx_lcdc_driver = { - .probe = rk31xx_lcdc_probe, - .remove = rk31xx_lcdc_remove, +static struct platform_driver rk312x_lcdc_driver = { + .probe = rk312x_lcdc_probe, + .remove = rk312x_lcdc_remove, .driver = { - .name = "rk31xx-lcdc", + .name = "rk312x-lcdc", .owner = THIS_MODULE, - .of_match_table = of_match_ptr(rk31xx_lcdc_dt_ids), + .of_match_table = of_match_ptr(rk312x_lcdc_dt_ids), }, - .suspend = rk31xx_lcdc_suspend, - .resume = rk31xx_lcdc_resume, - .shutdown = rk31xx_lcdc_shutdown, + .suspend = rk312x_lcdc_suspend, + .resume = rk312x_lcdc_resume, + .shutdown = rk312x_lcdc_shutdown, }; -static int __init rk31xx_lcdc_module_init(void) +static int __init rk312x_lcdc_module_init(void) { - return platform_driver_register(&rk31xx_lcdc_driver); + return platform_driver_register(&rk312x_lcdc_driver); } -static void __exit rk31xx_lcdc_module_exit(void) +static void __exit rk312x_lcdc_module_exit(void) { - platform_driver_unregister(&rk31xx_lcdc_driver); + platform_driver_unregister(&rk312x_lcdc_driver); } -fs_initcall(rk31xx_lcdc_module_init); -module_exit(rk31xx_lcdc_module_exit); +fs_initcall(rk312x_lcdc_module_init); +module_exit(rk312x_lcdc_module_exit); diff --git a/drivers/video/rockchip/lcdc/rk312x_lcdc.h b/drivers/video/rockchip/lcdc/rk312x_lcdc.h new file mode 100755 index 000000000000..81b6db5d637e --- /dev/null +++ b/drivers/video/rockchip/lcdc/rk312x_lcdc.h @@ -0,0 +1,736 @@ +#ifndef _RK312X_LCDC_H_ +#define _RK312X_LCDC_H_ + +#include +#include +#include + +enum _VOP_SOC_TYPE { + VOP_RK3036 = 0, + VOP_RK312X, +}; + + +#define BITS(x, bit) ((x) << (bit)) +#define BITS_MASK(x, mask, bit) BITS((x) & (mask), bit) + +/*******************register definition**********************/ + +#define SYS_CTRL (0x00) + #define m_WIN0_EN BITS(1, 0) + #define m_WIN1_EN BITS(1, 1) + #define m_HWC_EN BITS(1, 2) + #define m_WIN0_FORMAT BITS(7, 3) + #define m_WIN1_FORMAT BITS(7, 6) + #define m_HWC_LUT_EN BITS(1, 9) + #define m_HWC_SIZE BITS(1, 10) + #define m_DIRECT_PATH_EN BITS(1, 11) /* rk312x */ + #define m_DIRECT_PATH_LAYER BITS(1, 12) /* rk312x */ + #define m_TVE_MODE_SEL BITS(1, 13) /* rk312x */ + #define m_TVE_DAC_EN BITS(1, 14) /* rk312x */ + #define m_WIN0_RB_SWAP BITS(1, 15) + #define m_WIN0_ALPHA_SWAP BITS(1, 16) + #define m_WIN0_Y8_SWAP BITS(1, 17) + #define m_WIN0_UV_SWAP BITS(1, 18) + #define m_WIN1_RB_SWAP BITS(1, 19) + #define m_WIN1_ALPHA_SWAP BITS(1, 20) + #define m_WIN1_ENDIAN_SWAP BITS(1, 21) /* rk312x */ + #define m_WIN0_OTSD_DISABLE BITS(1, 22) + #define m_WIN1_OTSD_DISABLE BITS(1, 23) + #define m_DMA_BURST_LENGTH BITS(3, 24) + #define m_HWC_LODAD_EN BITS(1, 26) + #define m_WIN1_LUT_EN BITS(1, 27) /* rk312x */ + #define m_DSP_LUT_EN BITS(1, 28) /* rk312x */ + #define m_DMA_STOP BITS(1, 29) + #define m_LCDC_STANDBY BITS(1, 30) + #define m_AUTO_GATING_EN BITS(1, 31) + + #define v_WIN0_EN(x) BITS_MASK(x, 1, 0) + #define v_WIN1_EN(x) BITS_MASK(x, 1, 1) + #define v_HWC_EN(x) BITS_MASK(x, 1, 2) + #define v_WIN0_FORMAT(x) BITS_MASK(x, 7, 3) + #define v_WIN1_FORMAT(x) BITS_MASK(x, 7, 6) + #define v_HWC_LUT_EN(x) BITS_MASK(x, 1, 9) + #define v_HWC_SIZE(x) BITS_MASK(x, 1, 10) + #define v_DIRECT_PATH_EN(x) BITS_MASK(x, 1, 11) + #define v_DIRECT_PATH_LAYER(x) BITS_MASK(x, 1, 12) + #define v_TVE_MODE_SEL(x) BITS_MASK(x, 1, 13) + #define v_TVE_DAC_EN(x) BITS_MASK(x, 1, 14) + #define v_WIN0_RB_SWAP(x) BITS_MASK(x, 1, 15) + #define v_WIN0_ALPHA_SWAP(x) BITS_MASK(x, 1, 16) + #define v_WIN0_Y8_SWAP(x) BITS_MASK(x, 1, 17) + #define v_WIN0_UV_SWAP(x) BITS_MASK(x, 1, 18) + #define v_WIN1_RB_SWAP(x) BITS_MASK(x, 1, 19) + #define v_WIN1_ALPHA_SWAP(x) BITS_MASK(x, 1, 20) + #define v_WIN1_ENDIAN_SWAP(x) BITS_MASK(x, 1, 21) + #define v_WIN0_OTSD_DISABLE(x) BITS_MASK(x, 1, 22) + #define v_WIN1_OTSD_DISABLE(x) BITS_MASK(x, 1, 23) + #define v_DMA_BURST_LENGTH(x) BITS_MASK(x, 3, 24) + #define v_HWC_LODAD_EN(x) BITS_MASK(x, 1, 26) + #define v_WIN1_LUT_EN(x) BITS_MASK(x, 1, 27) + #define v_DSP_LUT_EN(x) BITS_MASK(x, 1, 28) + #define v_DMA_STOP(x) BITS_MASK(x, 1, 29) + #define v_LCDC_STANDBY(x) BITS_MASK(x, 1, 30) + #define v_AUTO_GATING_EN(x) BITS_MASK(x, 1, 31) + +#define DSP_CTRL0 (0x04) + #define m_DSP_OUT_FORMAT BITS(0x0f, 0) + #define m_HSYNC_POL BITS(1, 4) + #define m_VSYNC_POL BITS(1, 5) + #define m_DEN_POL BITS(1, 6) + #define m_DCLK_POL BITS(1, 7) + #define m_WIN0_TOP BITS(1, 8) + #define m_DITHER_UP_EN BITS(1, 9) + #define m_DITHER_DOWN_MODE BITS(1, 10) /* use for rk312x */ + #define m_DITHER_DOWN_EN BITS(1, 11) /* use for rk312x */ + #define m_INTERLACE_DSP_EN BITS(1, 12) + #define m_INTERLACE_FIELD_POL BITS(1, 13) /* use for rk312x */ + #define m_WIN0_INTERLACE_EN BITS(1, 14) /* use for rk312x */ + #define m_WIN1_INTERLACE_EN BITS(1, 15) + #define m_WIN0_YRGB_DEFLICK_EN BITS(1, 16) + #define m_WIN0_CBR_DEFLICK_EN BITS(1, 17) + #define m_WIN0_ALPHA_MODE BITS(1, 18) + #define m_WIN1_ALPHA_MODE BITS(1, 19) + #define m_WIN0_CSC_MODE BITS(3, 20) + #define m_WIN0_YUV_CLIP BITS(1, 23) + #define m_TVE_MODE BITS(1, 25) + #define m_SW_UV_OFFSET_EN BITS(1, 26) /* use for rk312x */ + #define m_DITHER_DOWN_SEL BITS(1, 27) /* use for rk312x */ + #define m_HWC_ALPHA_MODE BITS(1, 28) + #define m_ALPHA_MODE_SEL0 BITS(1, 29) + #define m_ALPHA_MODE_SEL1 BITS(1, 30) + #define m_WIN1_DIFF_DCLK_EN BITS(1, 31) /* use for rk3036 */ + #define m_SW_OVERLAY_MODE BITS(1, 31) /* use for rk312x */ + + #define v_DSP_OUT_FORMAT(x) BITS_MASK(x, 0x0f, 0) + #define v_HSYNC_POL(x) BITS_MASK(x, 1, 4) + #define v_VSYNC_POL(x) BITS_MASK(x, 1, 5) + #define v_DEN_POL(x) BITS_MASK(x, 1, 6) + #define v_DCLK_POL(x) BITS_MASK(x, 1, 7) + #define v_WIN0_TOP(x) BITS_MASK(x, 1, 8) + #define v_DITHER_UP_EN(x) BITS_MASK(x, 1, 9) + #define v_DITHER_DOWN_MODE(x) BITS_MASK(x, 1, 10) /* rk312x */ + #define v_DITHER_DOWN_EN(x) BITS_MASK(x, 1, 11) /* rk312x */ + #define v_INTERLACE_DSP_EN(x) BITS_MASK(x, 1, 12) + #define v_INTERLACE_FIELD_POL(x) BITS_MASK(x, 1, 13) /* rk312x */ + #define v_WIN0_INTERLACE_EN(x) BITS_MASK(x, 1, 14) /* rk312x */ + #define v_WIN1_INTERLACE_EN(x) BITS_MASK(x, 1, 15) + #define v_WIN0_YRGB_DEFLICK_EN(x) BITS_MASK(x, 1, 16) + #define v_WIN0_CBR_DEFLICK_EN(x) BITS_MASK(x, 1, 17) + #define v_WIN0_ALPHA_MODE(x) BITS_MASK(x, 1, 18) + #define v_WIN1_ALPHA_MODE(x) BITS_MASK(x, 1, 19) + #define v_WIN0_CSC_MODE(x) BITS_MASK(x, 3, 20) + #define v_WIN0_YUV_CLIP(x) BITS_MASK(x, 1, 23) + #define v_TVE_MODE(x) BITS_MASK(x, 1, 25) + #define v_SW_UV_OFFSET_EN(x) BITS_MASK(x, 1, 26) /* rk312x */ + #define v_DITHER_DOWN_SEL(x) BITS_MASK(x, 1, 27) /* rk312x */ + #define v_HWC_ALPHA_MODE(x) BITS_MASK(x, 1, 28) + #define v_ALPHA_MODE_SEL0(x) BITS_MASK(x, 1, 29) + #define v_ALPHA_MODE_SEL1(x) BITS_MASK(x, 1, 30) + #define v_WIN1_DIFF_DCLK_EN(x) BITS_MASK(x, 1, 31) /* rk3036 */ + #define v_SW_OVERLAY_MODE(x) BITS_MASK(x, 1, 31) /* rk312x */ + +#define DSP_CTRL1 (0x08) + #define m_BG_COLOR BITS(0xffffff, 0) + #define m_BG_B BITS(0xff, 0) + #define m_BG_G BITS(0xff, 8) + #define m_BG_R BITS(0xff, 16) + #define m_BLANK_EN BITS(1, 24) + #define m_BLACK_EN BITS(1, 25) + #define m_DSP_BG_SWAP BITS(1, 26) + #define m_DSP_RB_SWAP BITS(1, 27) + #define m_DSP_RG_SWAP BITS(1, 28) + #define m_DSP_DELTA_SWAP BITS(1, 29) /* rk3036 */ + #define m_DSP_DUMMY_SWAP BITS(1, 30) /* rk3036 */ + #define m_DSP_OUT_ZERO BITS(1, 31) + + #define v_BG_COLOR(x) BITS_MASK(x, 0xffffff, 0) + #define v_BG_B(x) BITS_MASK(x, 0xff, 0) + #define v_BG_G(x) BITS_MASK(x, 0xff, 8) + #define v_BG_R(x) BITS_MASK(x, 0xff, 16) + #define v_BLANK_EN(x) BITS_MASK(x, 1, 24) + #define v_BLACK_EN(x) BITS_MASK(x, 1, 25) + #define v_DSP_BG_SWAP(x) BITS_MASK(x, 1, 26) + #define v_DSP_RB_SWAP(x) BITS_MASK(x, 1, 27) + #define v_DSP_RG_SWAP(x) BITS_MASK(x, 1, 28) + #define v_DSP_DELTA_SWAP(x) BITS_MASK(x, 1, 29) /* rk3036 */ + #define v_DSP_DUMMY_SWAP(x) BITS_MASK(x, 1, 30) /* rk3036 */ + #define v_DSP_OUT_ZERO(x) BITS_MASK(x, 1, 31) + +#define INT_SCALER (0x0c) /* only use for rk312x */ + #define m_SCALER_EMPTY_INTR_EN BITS(1, 0) + #define m_SCLAER_EMPTY_INTR_CLR BITS(1, 1) + #define m_SCLAER_EMPTY_INTR_STA BITS(1, 2) + #define m_FS_MASK_EN BITS(1, 3) + #define m_HDMI_HSYNC_POL BITS(1, 4) + #define m_HDMI_VSYNC_POL BITS(1, 5) + #define m_HDMI_DEN_POL BITS(1, 6) + + #define v_SCALER_EMPTY_INTR_EN(x) BITS_MASK(x, 1, 0) + #define v_SCLAER_EMPTY_INTR_CLR(x) BITS_MASK(x, 1, 1) + #define v_SCLAER_EMPTY_INTR_STA(x) BITS_MASK(x, 1, 2) + #define v_FS_MASK_EN(x) BITS_MASK(x, 1, 3) + #define v_HDMI_HSYNC_POL(x) BITS_MASK(x, 1, 4) + #define v_HDMI_VSYNC_POL(x) BITS_MASK(x, 1, 5) + #define v_HDMI_DEN_POL(x) BITS_MASK(x. 1, 6) + +#define INT_STATUS (0x10) + #define m_HS_INT_STA BITS(1, 0) + #define m_FS_INT_STA BITS(1, 1) + #define m_LF_INT_STA BITS(1, 2) + #define m_BUS_ERR_INT_STA BITS(1, 3) + #define m_HS_INT_EN BITS(1, 4) + #define m_FS_INT_EN BITS(1, 5) + #define m_LF_INT_EN BITS(1, 6) + #define m_BUS_ERR_INT_EN BITS(1, 7) + #define m_HS_INT_CLEAR BITS(1, 8) + #define m_FS_INT_CLEAR BITS(1, 9) + #define m_LF_INT_CLEAR BITS(1, 10) + #define m_BUS_ERR_INT_CLEAR BITS(1, 11) + #define m_LF_INT_NUM BITS(0xfff, 12) + #define m_WIN0_EMPTY_INT_EN BITS(1, 24) + #define m_WIN1_EMPTY_INT_EN BITS(1, 25) + #define m_WIN0_EMPTY_INT_CLEAR BITS(1, 26) + #define m_WIN1_EMPTY_INT_CLEAR BITS(1, 27) + #define m_WIN0_EMPTY_INT_STA BITS(1, 28) + #define m_WIN1_EMPTY_INT_STA BITS(1, 29) + #define m_FS_RAW_STA BITS(1, 30) + #define m_LF_RAW_STA BITS(1, 31) + + #define v_HS_INT_EN(x) BITS_MASK(x, 1, 4) + #define v_FS_INT_EN(x) BITS_MASK(x, 1, 5) + #define v_LF_INT_EN(x) BITS_MASK(x, 1, 6) + #define v_BUS_ERR_INT_EN(x) BITS_MASK(x, 1, 7) + #define v_HS_INT_CLEAR(x) BITS_MASK(x, 1, 8) + #define v_FS_INT_CLEAR(x) BITS_MASK(x, 1, 9) + #define v_LF_INT_CLEAR(x) BITS_MASK(x, 1, 10) + #define v_BUS_ERR_INT_CLEAR(x) BITS_MASK(x, 1, 11) + #define v_LF_INT_NUM(x) BITS_MASK(x, 0xfff, 12) + #define v_WIN0_EMPTY_INT_EN(x) BITS_MASK(x, 1, 24) + #define v_WIN1_EMPTY_INT_EN(x) BITS_MASK(x, 1, 25) + #define v_WIN0_EMPTY_INT_CLEAR(x) BITS_MASK(x, 1, 26) + #define v_WIN1_EMPTY_INT_CLEAR(x) BITS_MASK(x, 1, 27) + +#define ALPHA_CTRL (0x14) + #define m_WIN0_ALPHA_EN BITS(1, 0) + #define m_WIN1_ALPHA_EN BITS(1, 1) + #define m_HWC_ALPAH_EN BITS(1, 2) + #define m_WIN1_PREMUL_SCALE BITS(1, 3) /* rk3036 */ + #define m_WIN0_ALPHA_VAL BITS(0xff, 4) + #define m_WIN1_ALPHA_VAL BITS(0xff, 12) + #define m_HWC_ALPAH_VAL BITS(0xff, 20) + + #define v_WIN0_ALPHA_EN(x) BITS_MASK(x, 1, 0) + #define v_WIN1_ALPHA_EN(x) BITS_MASK(x, 1, 1) + #define v_HWC_ALPAH_EN(x) BITS_MASK(x, 1, 2) + #define v_WIN1_PREMUL_SCALE(x) BITS_MASK(x, 1, 3) /* rk3036 */ + #define v_WIN0_ALPHA_VAL(x) BITS_MASK(x, 0xff, 4) + #define v_WIN1_ALPHA_VAL(x) BITS_MASK(x, 0xff, 12) + #define v_HWC_ALPAH_VAL(x) BITS_MASK(x, 0xff, 20) + +#define WIN0_COLOR_KEY (0x18) +#define WIN1_COLOR_KEY (0x1c) + #define m_COLOR_KEY_VAL BITS(0xffffff, 0) + #define m_COLOR_KEY_EN BITS(1, 24) + + #define v_COLOR_KEY_VAL(x) BITS_MASK(x, 0xffffff, 0) + #define v_COLOR_KEY_EN(x) BITS_MASK(x, 1, 24) + +/* Layer Registers */ +#define WIN0_YRGB_MST (0x20) +#define WIN0_CBR_MST (0x24) +#define WIN1_MST (0xa0) /* rk3036 */ +#define WIN1_MST_RK312X (0x4c) /* rk312x */ +#define HWC_MST (0x58) + +#define WIN1_VIR (0x28) +#define WIN0_VIR (0x30) + #define m_YRGB_VIR BITS(0x1fff, 0) + #define m_CBBR_VIR BITS(0x1fff, 16) + + #define v_YRGB_VIR(x) BITS_MASK(x, 0x1fff, 0) + #define v_CBBR_VIR(x) BITS_MASK(x, 0x1fff, 16) + + #define v_ARGB888_VIRWIDTH(x) BITS_MASK(x, 0x1fff, 0) + #define v_RGB888_VIRWIDTH(x) BITS_MASK(((x*3)>>2)+((x)%3), 0x1fff, 0) + #define v_RGB565_VIRWIDTH(x) BITS_MASK(DIV_ROUND_UP(x, 2), 0x1fff, 0) + #define v_YUV_VIRWIDTH(x) BITS_MASK(DIV_ROUND_UP(x, 4), 0x1fff, 0) + #define v_CBCR_VIR(x) BITS_MASK(x, 0x1fff, 16) + +#define WIN0_ACT_INFO (0x34) +#define WIN1_ACT_INFO (0xb4) /* rk3036 */ + #define m_ACT_WIDTH BITS(0x1fff, 0) + #define m_ACT_HEIGHT BITS(0x1fff, 16) + + #define v_ACT_WIDTH(x) BITS_MASK(x - 1, 0x1fff, 0) + #define v_ACT_HEIGHT(x) BITS_MASK(x - 1, 0x1fff, 16) + +#define WIN0_DSP_INFO (0x38) +#define WIN1_DSP_INFO (0xb8) /* rk3036 */ +#define WIN1_DSP_INFO_RK312X (0x50) /* rk312x */ + #define m_DSP_WIDTH BITS(0x7ff, 0) + #define m_DSP_HEIGHT BITS(0x7ff, 16) + + #define v_DSP_WIDTH(x) BITS_MASK(x - 1, 0x7ff, 0) + #define v_DSP_HEIGHT(x) BITS_MASK(x - 1, 0x7ff, 16) + +#define WIN0_DSP_ST (0x3c) +#define WIN1_DSP_ST (0xbc) /* rk3036 */ +#define WIN1_DSP_ST_RK312X (0x54) /* rk312x */ +#define HWC_DSP_ST (0x5c) + #define m_DSP_STX BITS(0xfff, 0) + #define m_DSP_STY BITS(0xfff, 16) + + #define v_DSP_STX(x) BITS_MASK(x, 0xfff, 0) + #define v_DSP_STY(x) BITS_MASK(x, 0xfff, 16) + +#define WIN0_SCL_FACTOR_YRGB (0x40) +#define WIN0_SCL_FACTOR_CBR (0x44) +#define WIN1_SCL_FACTOR_YRGB (0xc0) /* rk3036 */ + #define m_X_SCL_FACTOR BITS(0xffff, 0) + #define m_Y_SCL_FACTOR BITS(0xffff, 16) + + #define v_X_SCL_FACTOR(x) BITS_MASK(x, 0xffff, 0) + #define v_Y_SCL_FACTOR(x) BITS_MASK(x, 0xffff, 16) + +#define WIN0_SCL_OFFSET (0x48) +#define WIN1_SCL_OFFSET (0xc8) /* rk3036 */ + +/* LUT Registers */ +#define WIN1_LUT_ADDR (0x0400) /* rk3036 */ +#define HWC_LUT_ADDR (0x0800) +#define DSP_LUT_ADDR (0x0c00) /* rk312x */ + +/* Display Infomation Registers */ +#define DSP_HTOTAL_HS_END (0x6c) + #define v_HSYNC(x) BITS_MASK(x, 0xfff, 0) /* hsync pulse width */ + #define v_HORPRD(x) BITS_MASK(x, 0xfff, 16) /* horizontal period */ + +#define DSP_HACT_ST_END (0x70) + #define v_HAEP(x) BITS_MASK(x, 0xfff, 0) /* horizontal active end point */ + #define v_HASP(x) BITS_MASK(x, 0xfff, 16) /* horizontal active start point */ + +#define DSP_VTOTAL_VS_END (0x74) + #define v_VSYNC(x) BITS_MASK(x, 0xfff, 0) + #define v_VERPRD(x) BITS_MASK(x, 0xfff, 16) + +#define DSP_VACT_ST_END (0x78) + #define v_VAEP(x) BITS_MASK(x, 0xfff, 0) + #define v_VASP(x) BITS_MASK(x, 0xfff, 16) + +#define DSP_VS_ST_END_F1 (0x7c) + #define v_VSYNC_END_F1(x) BITS_MASK(x, 0xfff, 0) + #define v_VSYNC_ST_F1(x) BITS_MASK(x, 0xfff, 16) +#define DSP_VACT_ST_END_F1 (0x80) + #define v_VAEP_F1(x) BITS_MASK(x, 0xfff, 0) + #define v_VASP_F1(x) BITS_MASK(x, 0xfff, 16) + +/* Scaler Registers + * Only used for rk312x + */ +#define SCALER_CTRL (0xa0) + #define m_SCALER_EN BITS(1, 0) + #define m_SCALER_SYNC_INVERT BITS(1, 2) + #define m_SCALER_DEN_INVERT BITS(1, 3) + #define m_SCALER_OUT_ZERO BITS(1, 4) + #define m_SCALER_OUT_EN BITS(1, 5) + #define m_SCALER_VSYNC_MODE BITS(3, 6) + #define m_SCALER_VSYNC_VST BITS(0xff, 8) + + #define v_SCALER_EN(x) BITS_MASK(x, 1, 0) + #define v_SCALER_SYNC_INVERT(x) BITS_MASK(x, 1, 2) + #define v_SCALER_DEN_INVERT(x) BITS_MASK(x, 1, 3) + #define v_SCALER_OUT_ZERO(x) BITS_MASK(x, 1, 4) + #define v_SCALER_OUT_EN(x) BITS_MASK(x, 1, 5) + #define v_SCALER_VSYNC_MODE(x) BITS_MASK(x, 3, 6) + #define v_SCALER_VSYNC_VST(x) BITS_MASK(x, 0xff, 8) + +#define SCALER_FACTOR (0xa4) + #define m_SCALER_H_FACTOR BITS(0x3fff, 0) + #define m_SCALER_V_FACTOR BITS(0x3fff, 16) + + #define v_SCALER_H_FACTOR(x) BITS_MASK(x, 0x3fff, 0) + #define v_SCALER_V_FACTOR(x) BITS_MASK(x, 0x3fff, 16) + +#define SCALER_FRAME_ST (0xa8) + #define m_SCALER_FRAME_HST BITS(0xfff, 0) + #define m_SCALER_FRAME_VST BITS(0xfff, 16) + + #define v_SCALER_FRAME_HST(x) BITS_MASK(x, 0xfff, 0) + #define v_SCALER_FRAME_VST(x) BITS_MASK(x, 0xfff, 16) + +#define SCALER_DSP_HOR_TIMING (0xac) + #define m_SCALER_HTOTAL BITS(0xfff, 0) + #define m_SCALER_HS_END BITS(0xff, 16) + + #define v_SCALER_HTOTAL(x) BITS_MASK(x, 0xfff, 0) + #define v_SCALER_HS_END(x) BITS_MASK(x, 0xff, 16) + +#define SCALER_DSP_HACT_ST_END (0xb0) + #define m_SCALER_HAEP BITS(0xfff, 0) + #define m_SCALER_HASP BITS(0x3ff, 16) + + #define v_SCALER_HAEP(x) BITS_MASK(x, 0xfff, 0) + #define v_SCALER_HASP(x) BITS_MASK(x, 0x3ff, 16) + +#define SCALER_DSP_VER_TIMING (0xb4) + #define m_SCALER_VTOTAL BITS(0xfff, 0) + #define m_SCALER_VS_END BITS(0xff, 16) + + #define v_SCALER_VTOTAL(x) BITS_MASK(0xfff, 0) + #define v_SCALER_VS_END(x) BITS_MASK(0xff, 16) + +#define SCALER_DSP_VACT_ST_END (0xb8) + #define m_SCALER_VAEP BITS(0xfff, 0) + #define m_SCALER_VASP BITS(0xff, 16) + + #define v_SCALER_VAEP(x) BITS_MASK(x, 0xfff, 0) + #define v_SCALER_VASP(x) BITS_MASK(x, 0xff, 16) + +#define SCALER_DSP_HBOR_TIMING (0xbc) + #define m_SCALER_HBOR_END BITS(0xfff, 0) + #define m_SCALER_HBOR_ST BITS(0x3ff, 16) + + #define v_SCALER_HBOR_END(x) BITS_MASK(x, 0xfff, 0) + #define v_SCALER_HBOR_ST(x) BITS_MASK(x, 0x3ff, 16) + +#define SCALER_DSP_VBOR_TIMING (0xc0) + #define m_SCALER_VBOR_END BITS(0xfff, 0) + #define m_SCALER_VBOR_ST BITS(0xff, 16) + + #define v_SCALER_VBOR_END(x) BITS_MASK(x, 0xfff, 0) + #define v_SCALER_VBOR_ST(x) BITS_MASK(x, 0xff, 16) + +/* BCSH Registers */ +#define BCSH_CTRL (0xd0) + #define m_BCSH_EN BITS(1, 0) + #define m_BCSH_R2Y_CSC_MODE BITS(1, 1) /* rk312x */ + #define m_BCSH_OUT_MODE BITS(3, 2) + #define m_BCSH_Y2R_CSC_MODE BITS(3, 4) + #define m_BCSH_Y2R_EN BITS(1, 6) /* rk312x */ + #define m_BCSH_R2Y_EN BITS(1, 7) /* rk312x */ + + #define v_BCSH_EN(x) BITS_MASK(x, 1, 0) + #define v_BCSH_R2Y_CSC_MODE(x) BITS_MASK(x, 1, 1) /* rk312x */ + #define v_BCSH_OUT_MODE(x) BITS_MASK(x, 3, 2) + #define v_BCSH_CSC_MODE(x) BITS_MASK(x, 3, 4) + #define v_BCSH_Y2R_EN(x) BITS_MASK(x, 1, 6) /* rk312x */ + #define v_BCSH_R2Y_EN(x) BITS_MASK(x, 1, 7) /* rk312x */ + +#define BCSH_COLOR_BAR (0xd4) + #define m_BCSH_COLOR_BAR_Y BITS(0xff, 0) + #define m_BCSH_COLOR_BAR_U BITS(0xff, 8) + #define m_BCSH_COLOR_BAR_V BITS(0xff, 16) + + #define v_BCSH_COLOR_BAR_Y(x) BITS_MASK(x, 0xff, 0) + #define v_BCSH_COLOR_BAR_U(x) BITS_MASK(x, 0xff, 8) + #define v_BCSH_COLOR_BAR_V(x) BITS_MASK(x, 0xff, 16) + +#define BCSH_BCS (0xd8) + #define m_BCSH_BRIGHTNESS BITS(0x1f, 0) + #define m_BCSH_CONTRAST BITS(0xff, 8) + #define m_BCSH_SAT_CON BITS(0x1ff, 16) + + #define v_BCSH_BRIGHTNESS(x) BITS_MASK(x, 0x1f, 0) + #define v_BCSH_CONTRAST(x) BITS_MASK(x, 0xff, 8) + #define v_BCSH_SAT_CON(x) BITS_MASK(x, 0x1ff, 16) + +#define BCSH_H (0xdc) + #define m_BCSH_SIN_HUE BITS(0xff, 0) + #define m_BCSH_COS_HUE BITS(0xff, 16) + + #define v_BCSH_SIN_HUE(x) BITS_MASK(x, 0xff, 0) + #define v_BCSH_COS_HUE(x) BITS_MASK(x, 0xff, 16) + +#define FRC_LOWER01_0 (0xe0) +#define FRC_LOWER01_1 (0xe4) +#define FRC_LOWER10_0 (0xe8) +#define FRC_LOWER10_1 (0xec) +#define FRC_LOWER11_0 (0xf0) +#define FRC_LOWER11_1 (0xf4) + +/* Bus Register */ +#define AXI_BUS_CTRL (0x2c) + #define m_IO_PAD_CLK BITS(1, 31) + #define m_CORE_CLK_DIV_EN BITS(1, 30) + #define m_MIPI_DCLK_INVERT BITS(1, 29) /* rk312x */ + #define m_MIPI_DCLK_EN BITS(1, 28) /* rk312x */ + #define m_LVDS_DCLK_INVERT BITS(1, 27) /* rk312x */ + #define m_LVDS_DCLK_EN BITS(1, 26) /* rk312x */ + #define m_RGB_DCLK_INVERT BITS(1, 25) /* rk312x */ + #define m_RGB_DCLK_EN BITS(1, 24) /* rk312x */ + #define m_HDMI_DCLK_INVERT BITS(1, 23) + #define m_HDMI_DCLK_EN BITS(1, 22) + #define m_TVE_DAC_DCLK_INVERT BITS(1, 21) + #define m_TVE_DAC_DCLK_EN BITS(1, 20) + #define m_HDMI_DCLK_DIV_EN BITS(1, 19) + #define m_AXI_OUTSTANDING_MAX_NUM BITS(0x1f, 12) + #define m_AXI_MAX_OUTSTANDING_EN BITS(1, 11) + #define m_MMU_EN BITS(1, 10) + #define m_NOC_HURRY_THRESHOLD BITS(0xf, 6) + #define m_NOC_HURRY_VALUE BITS(3, 4) + #define m_NOC_HURRY_EN BITS(1, 3) + #define m_NOC_QOS_VALUE BITS(3, 1) + #define m_NOC_QOS_EN BITS(1, 0) + + #define v_IO_PAD_CLK(x) BITS_MASK(x, 1, 31) + #define v_CORE_CLK_DIV_EN(x) BITS_MASK(x, 1, 30) + #define v_MIPI_DCLK_INVERT(x) BITS_MASK(x, 1, 29) + #define v_MIPI_DCLK_EN(x) BITS_MASK(x, 1, 28) + #define v_LVDS_DCLK_INVERT(x) BITS_MASK(x, 1, 27) + #define v_LVDS_DCLK_EN(x) BITS_MASK(x, 1, 26) + #define v_RGB_DCLK_INVERT(x) BITS_MASK(x, 1, 25) + #define v_RGB_DCLK_EN(x) BITS_MASK(x, 1, 24) + #define v_HDMI_DCLK_INVERT(x) BITS_MASK(x, 1, 23) + #define v_HDMI_DCLK_EN(x) BITS_MASK(x, 1, 22) + #define v_TVE_DAC_DCLK_INVERT(x) BITS_MASK(x, 1, 21) + #define v_TVE_DAC_DCLK_EN(x) BITS_MASK(x, 1, 20) + #define v_HDMI_DCLK_DIV_EN(x) BITS_MASK(x, 1, 19) + #define v_AXI_OUTSTANDING_MAX_NUM(x) BITS_MASK(x, 0x1f, 12) + #define v_AXI_MAX_OUTSTANDING_EN(x) BITS_MASK(x, 1, 11) + #define v_MMU_EN(x) BITS_MASK(x, 1, 10) + #define v_NOC_HURRY_THRESHOLD(x) BITS_MASK(x, 0xf, 6) + #define v_NOC_HURRY_VALUE(x) BITS_MASK(x, 3, 4) + #define v_NOC_HURRY_EN(x) BITS_MASK(x, 1, 3) + #define v_NOC_QOS_VALUE(x) BITS_MASK(x, 3, 1) + #define v_NOC_QOS_EN(x) BITS_MASK(x, 1, 0) + +#define GATHER_TRANSFER (0x84) + #define m_WIN1_AXI_GATHER_NUM BITS(0xf, 12) + #define m_WIN0_CBCR_AXI_GATHER_NUM BITS(0x7, 8) + #define m_WIN0_YRGB_AXI_GATHER_NUM BITS(0xf, 4) + #define m_WIN1_AXI_GAHTER_EN BITS(1, 2) + #define m_WIN0_CBCR_AXI_GATHER_EN BITS(1, 1) + #define m_WIN0_YRGB_AXI_GATHER_EN BITS(1, 0) + + #define v_WIN1_AXI_GATHER_NUM(x) BITS_MASK(x, 0xf, 12) + #define v_WIN0_CBCR_AXI_GATHER_NUM(x) BITS_MASK(x, 0x7, 8) + #define v_WIN0_YRGB_AXI_GATHER_NUM(x) BITS_MASK(x, 0xf, 4) + #define v_WIN1_AXI_GAHTER_EN(x) BITS_MASK(x, 1, 2) + #define v_WIN0_CBCR_AXI_GATHER_EN(x) BITS_MASK(x, 1, 1) + #define v_WIN0_YRGB_AXI_GATHER_EN(x) BITS_MASK(x, 1, 0) + +#define VERSION_INFO (0x94) + #define m_MAJOR BITS(0xff, 24) + #define m_MINOR BITS(0xff, 16) + #define m_BUILD BITS(0xffff) + +#define REG_CFG_DONE (0x90) + +/* TV Control Registers */ +#define TV_CTRL (0x200) +#define TV_SYNC_TIMING (0x204) +#define TV_ACT_TIMING (0x208) +#define TV_ADJ_TIMING (0x20c) +#define TV_FREQ_SC (0x210) +#define TV_FILTER0 (0x214) +#define TV_FILTER1 (0x218) +#define TV_FILTER2 (0x21C) +#define TV_ACT_ST (0x234) +#define TV_ROUTING (0x238) +#define TV_SYNC_ADJUST (0x250) +#define TV_STATUS (0x254) +#define TV_RESET (0x268) +#define TV_SATURATION (0x278) +#define TV_BW_CTRL (0x28C) +#define TV_BRIGHTNESS_CONTRAST (0x290) + + +/* MMU registers */ +#define MMU_DTE_ADDR (0x0300) + #define m_MMU_DTE_ADDR BITS(0xffffffff, 0) + #define v_MMU_DTE_ADDR(x) BITS_MASK(x, 0xffffffff, 0) + +#define MMU_STATUS (0x0304) + #define m_PAGING_ENABLED BITS(1, 0) + #define m_PAGE_FAULT_ACTIVE BITS(1, 1) + #define m_STAIL_ACTIVE BITS(1, 2) + #define m_MMU_IDLE BITS(1, 3) + #define m_REPLAY_BUFFER_EMPTY BITS(1, 4) + #define m_PAGE_FAULT_IS_WRITE BITS(1, 5) + #define m_PAGE_FAULT_BUS_ID BITS(0x1f, 6) + + #define v_PAGING_ENABLED(x) BITS_MASK(x, 1, 0) + #define v_PAGE_FAULT_ACTIVE(x) BITS_MASK(x, 1, 1) + #define v_STAIL_ACTIVE(x) BITS_MASK(x, 1, 2) + #define v_MMU_IDLE(x) BITS_MASK(x, 1, 3) + #define v_REPLAY_BUFFER_EMPTY(x) BITS_MASK(x, 1, 4) + #define v_PAGE_FAULT_IS_WRITE(x) BITS_MASK(x, 1, 5) + #define v_PAGE_FAULT_BUS_ID(x) BITS_MASK(x, 0x1f, 6) + +#define MMU_COMMAND (0x0308) + #define m_MMU_CMD BITS(0x7, 0) + #define v_MMU_CMD(x) BITS_MASK(x, 0x7, 0) + +#define MMU_PAGE_FAULT_ADDR (0x030c) + #define m_PAGE_FAULT_ADDR BITS(0xffffffff, 0) + #define v_PAGE_FAULT_ADDR(x) BITS_MASK(x, 0xffffffff, 0) + +#define MMU_ZAP_ONE_LINE (0x0310) + #define m_MMU_ZAP_ONE_LINE BITS(0xffffffff, 0) + #define v_MMU_ZAP_ONE_LINE(x) BITS_MASK(x, 0xffffffff, 0) + +#define MMU_INT_RAWSTAT (0x0314) + #define m_PAGE_FAULT_RAWSTAT BITS(1, 0) + #define m_READ_BUS_ERROR_RAWSTAT BITS(1, 1) + + #define v_PAGE_FAULT_RAWSTAT(x) BITS(x, 1, 0) + #define v_READ_BUS_ERROR_RAWSTAT(x) BITS(x, 1, 1) + +#define MMU_INT_CLEAR (0x0318) + #define m_PAGE_FAULT_CLEAR BITS(1, 0) + #define m_READ_BUS_ERROR_CLEAR BITS(1, 1) + + #define v_PAGE_FAULT_CLEAR(x) BITS(x, 1, 0) + #define v_READ_BUS_ERROR_CLEAR(x) BITS(x, 1, 1) + +#define MMU_INT_MASK (0x031c) + #define m_PAGE_FAULT_MASK BITS(1, 0) + #define m_READ_BUS_ERROR_MASK BITS(1, 1) + + #define v_PAGE_FAULT_MASK(x) BITS(x, 1, 0) + #define v_READ_BUS_ERROR_MASK(x) BITS(x, 1, 1) + +#define MMU_INT_STATUS (0x0320) + #define m_PAGE_FAULT_STATUS BITS(1, 0) + #define m_READ_BUS_ERROR_STATUS BITS(1, 1) + + #define v_PAGE_FAULT_STATUS(x) BITS(x, 1, 0) + #define v_READ_BUS_ERROR_STATUS(x) BITS(x, 1, 1) + +#define MMU_AUTO_GATING (0x0324) + #define m_MMU_AUTO_GATING BITS(1, 0) + #define v_MMU_AUTO_GATING(x) BITS(x, 1, 0) + + +enum _vop_dma_burst { + DMA_BURST_16 = 0, + DMA_BURST_8, + DMA_BURST_4 +}; + +enum _vop_format_e { + VOP_FORMAT_ARGB888 = 0, + VOP_FORMAT_RGB888, + VOP_FORMAT_RGB565, + VOP_FORMAT_YCBCR420 = 4, + VOP_FORMAT_YCBCR422, + VOP_FORMAT_YCBCR444 +}; + +enum _vop_tv_mode { + TV_NTSC, + TV_PAL, +}; + +enum _vop_csc_mode { + VOP_CSC_BT601 = 0, + VOP_CSC_JPEG, + VOP_CSC_BT709 +}; + +enum _vop_hwc_size { + VOP_HWC_SIZE_32, + VOP_HWC_SIZE_64 +}; + +#define CalScale(x, y) ((((u32)(x - 1)) * 0x1000) / (y - 1)) + +struct rk_lcdc_drvdata { + u8 soc_type; + u32 reserve; +}; + +struct lcdc_device { + int id; + u8 soc_type; + struct rk_lcdc_driver driver; + struct device *dev; + struct rk_screen *screen; + + void __iomem *regs; + void *regsbak; /* back up reg */ + u32 reg_phy_base; /* physical basic address of lcdc register */ + u32 len; /* physical map length of lcdc register */ + spinlock_t reg_lock; /* one time only one process allowed to config the register */ + + int __iomem *dsp_lut_addr_base; + + int prop; /* used for primary or extended display device */ + bool pre_init; + bool pwr18; /* if lcdc use 1.8v power supply */ + bool clk_on; /* if aclk or hclk is closed ,acess to register is not allowed */ + u8 atv_layer_cnt; /* active layer counter,when atv_layer_cnt = 0,lcdc is disable*/ + + unsigned int irq; + + struct clk *pd; /* lcdc power domain */ + struct clk *hclk; /* lcdc AHP clk */ + struct clk *dclk; /* lcdc dclk */ + struct clk *aclk; /* lcdc share memory frequency */ + u32 pixclock; + + u32 standby; /* 1:standby,0:work */ +}; + +static inline void lcdc_writel(struct lcdc_device *lcdc_dev, u32 offset, u32 v) +{ + u32 *_pv = (u32*)lcdc_dev->regsbak; + _pv += (offset >> 2); + *_pv = v; + writel_relaxed(v, lcdc_dev->regs + offset); +} + +static inline u32 lcdc_readl(struct lcdc_device *lcdc_dev, u32 offset) +{ + u32 v; + u32 *_pv = (u32*)lcdc_dev->regsbak; + _pv += (offset >> 2); + v = readl_relaxed(lcdc_dev->regs + offset); + *_pv = v; + return v; +} + +static inline u32 lcdc_read_bit(struct lcdc_device *lcdc_dev, u32 offset, + u32 msk) +{ + u32 _v = readl_relaxed(lcdc_dev->regs + offset); + _v &= msk; + return (_v? 1 : 0); +} + +static inline void lcdc_set_bit(struct lcdc_device *lcdc_dev, u32 offset, + u32 msk) +{ + u32* _pv = (u32*)lcdc_dev->regsbak; + _pv += (offset >> 2); + (*_pv) |= msk; + writel_relaxed(*_pv, lcdc_dev->regs + offset); +} + +static inline void lcdc_clr_bit(struct lcdc_device *lcdc_dev, u32 offset, + u32 msk) +{ + u32* _pv = (u32*)lcdc_dev->regsbak; + _pv += (offset >> 2); + (*_pv) &= (~msk); + writel_relaxed(*_pv, lcdc_dev->regs + offset); +} + +static inline void lcdc_msk_reg(struct lcdc_device *lcdc_dev, u32 offset, + u32 msk, u32 v) +{ + u32 *_pv = (u32*)lcdc_dev->regsbak; + _pv += (offset >> 2); + (*_pv) &= (~msk); + (*_pv) |= v; + writel_relaxed(*_pv, lcdc_dev->regs + offset); +} + +static inline void lcdc_cfg_done(struct lcdc_device *lcdc_dev) +{ + writel_relaxed(0x01, lcdc_dev->regs + REG_CFG_DONE); + dsb(); +} + +#endif /* _RK312X_LCDC_H_ */ diff --git a/drivers/video/rockchip/lcdc/rk31xx_lcdc.h b/drivers/video/rockchip/lcdc/rk31xx_lcdc.h deleted file mode 100755 index c56a071b1b5d..000000000000 --- a/drivers/video/rockchip/lcdc/rk31xx_lcdc.h +++ /dev/null @@ -1,742 +0,0 @@ -#ifndef _RK31XX_LCDC_H_ -#define _RK31XX_LCDC_H_ - -#include -#include -#include - -enum _VOP_SOC_TYPE { - VOP_RK3036 = 0, - VOP_RK312X, -}; - -#ifdef BIT -#undef BIT -#endif -#define BIT(x, bit) ((x) << (bit)) - -#ifdef BIT_MASK -#undef BIT_MASK -#endif -#define BIT_MASK(x, mask, bit) BIT((x) & (mask), bit) - -/*******************register definition**********************/ - -#define SYS_CTRL (0x00) - #define m_WIN0_EN BIT(1, 0) - #define m_WIN1_EN BIT(1, 1) - #define m_HWC_EN BIT(1, 2) - #define m_WIN0_FORMAT BIT(7, 3) - #define m_WIN1_FORMAT BIT(7, 6) - #define m_HWC_LUT_EN BIT(1, 9) - #define m_HWC_SIZE BIT(1, 10) - #define m_DIRECT_PATH_EN BIT(1, 11) /* rk312x */ - #define m_DIRECT_PATH_LAYER BIT(1, 12) /* rk312x */ - #define m_TVE_MODE_SEL BIT(1, 13) /* rk312x */ - #define m_TVE_DAC_EN BIT(1, 14) /* rk312x */ - #define m_WIN0_RB_SWAP BIT(1, 15) - #define m_WIN0_ALPHA_SWAP BIT(1, 16) - #define m_WIN0_Y8_SWAP BIT(1, 17) - #define m_WIN0_UV_SWAP BIT(1, 18) - #define m_WIN1_RB_SWAP BIT(1, 19) - #define m_WIN1_ALPHA_SWAP BIT(1, 20) - #define m_WIN1_ENDIAN_SWAP BIT(1, 21) /* rk312x */ - #define m_WIN0_OTSD_DISABLE BIT(1, 22) - #define m_WIN1_OTSD_DISABLE BIT(1, 23) - #define m_DMA_BURST_LENGTH BIT(3, 24) - #define m_HWC_LODAD_EN BIT(1, 26) - #define m_WIN1_LUT_EN BIT(1, 27) /* rk312x */ - #define m_DSP_LUT_EN BIT(1, 28) /* rk312x */ - #define m_DMA_STOP BIT(1, 29) - #define m_LCDC_STANDBY BIT(1, 30) - #define m_AUTO_GATING_EN BIT(1, 31) - - #define v_WIN0_EN(x) BIT_MASK(x, 1, 0) - #define v_WIN1_EN(x) BIT_MASK(x, 1, 1) - #define v_HWC_EN(x) BIT_MASK(x, 1, 2) - #define v_WIN0_FORMAT(x) BIT_MASK(x, 7, 3) - #define v_WIN1_FORMAT(x) BIT_MASK(x, 7, 6) - #define v_HWC_LUT_EN(x) BIT_MASK(x, 1, 9) - #define v_HWC_SIZE(x) BIT_MASK(x, 1, 10) - #define v_DIRECT_PATH_EN(x) BIT_MASK(x, 1, 11) - #define v_DIRECT_PATH_LAYER(x) BIT_MASK(x, 1, 12) - #define v_TVE_MODE_SEL(x) BIT_MASK(x, 1, 13) - #define v_TVE_DAC_EN(x) BIT_MASK(x, 1, 14) - #define v_WIN0_RB_SWAP(x) BIT_MASK(x, 1, 15) - #define v_WIN0_ALPHA_SWAP(x) BIT_MASK(x, 1, 16) - #define v_WIN0_Y8_SWAP(x) BIT_MASK(x, 1, 17) - #define v_WIN0_UV_SWAP(x) BIT_MASK(x, 1, 18) - #define v_WIN1_RB_SWAP(x) BIT_MASK(x, 1, 19) - #define v_WIN1_ALPHA_SWAP(x) BIT_MASK(x, 1, 20) - #define v_WIN1_ENDIAN_SWAP(x) BIT_MASK(x, 1, 21) - #define v_WIN0_OTSD_DISABLE(x) BIT_MASK(x, 1, 22) - #define v_WIN1_OTSD_DISABLE(x) BIT_MASK(x, 1, 23) - #define v_DMA_BURST_LENGTH(x) BIT_MASK(x, 3, 24) - #define v_HWC_LODAD_EN(x) BIT_MASK(x, 1, 26) - #define v_WIN1_LUT_EN(x) BIT_MASK(x, 1, 27) - #define v_DSP_LUT_EN(x) BIT_MASK(x, 1, 28) - #define v_DMA_STOP(x) BIT_MASK(x, 1, 29) - #define v_LCDC_STANDBY(x) BIT_MASK(x, 1, 30) - #define v_AUTO_GATING_EN(x) BIT_MASK(x, 1, 31) - -#define DSP_CTRL0 (0x04) - #define m_DSP_OUT_FORMAT BIT(0x0f, 0) - #define m_HSYNC_POL BIT(1, 4) - #define m_VSYNC_POL BIT(1, 5) - #define m_DEN_POL BIT(1, 6) - #define m_DCLK_POL BIT(1, 7) - #define m_WIN0_TOP BIT(1, 8) - #define m_DITHER_UP_EN BIT(1, 9) - #define m_DITHER_DOWN_MODE BIT(1, 10) /* use for rk312x */ - #define m_DITHER_DOWN_EN BIT(1, 11) /* use for rk312x */ - #define m_INTERLACE_DSP_EN BIT(1, 12) - #define m_INTERLACE_FIELD_POL BIT(1, 13) /* use for rk312x */ - #define m_WIN0_INTERLACE_EN BIT(1, 14) /* use for rk312x */ - #define m_WIN1_INTERLACE_EN BIT(1, 15) - #define m_WIN0_YRGB_DEFLICK_EN BIT(1, 16) - #define m_WIN0_CBR_DEFLICK_EN BIT(1, 17) - #define m_WIN0_ALPHA_MODE BIT(1, 18) - #define m_WIN1_ALPHA_MODE BIT(1, 19) - #define m_WIN0_CSC_MODE BIT(3, 20) - #define m_WIN0_YUV_CLIP BIT(1, 23) - #define m_TVE_MODE BIT(1, 25) - #define m_SW_UV_OFFSET_EN BIT(1, 26) /* use for rk312x */ - #define m_DITHER_DOWN_SEL BIT(1, 27) /* use for rk312x */ - #define m_HWC_ALPHA_MODE BIT(1, 28) - #define m_ALPHA_MODE_SEL0 BIT(1, 29) - #define m_ALPHA_MODE_SEL1 BIT(1, 30) - #define m_WIN1_DIFF_DCLK_EN BIT(1, 31) /* use for rk3036 */ - #define m_SW_OVERLAY_MODE BIT(1, 31) /* use for rk312x */ - - #define v_DSP_OUT_FORMAT(x) BIT_MASK(x, 0x0f, 0) - #define v_HSYNC_POL(x) BIT_MASK(x, 1, 4) - #define v_VSYNC_POL(x) BIT_MASK(x, 1, 5) - #define v_DEN_POL(x) BIT_MASK(x, 1, 6) - #define v_DCLK_POL(x) BIT_MASK(x, 1, 7) - #define v_WIN0_TOP(x) BIT_MASK(x, 1, 8) - #define v_DITHER_UP_EN(x) BIT_MASK(x, 1, 9) - #define v_DITHER_DOWN_MODE(x) BIT_MASK(x, 1, 10) /* rk312x */ - #define v_DITHER_DOWN_EN(x) BIT_MASK(x, 1, 11) /* rk312x */ - #define v_INTERLACE_DSP_EN(x) BIT_MASK(x, 1, 12) - #define v_INTERLACE_FIELD_POL(x) BIT_MASK(x, 1, 13) /* rk312x */ - #define v_WIN0_INTERLACE_EN(x) BIT_MASK(x, 1, 14) /* rk312x */ - #define v_WIN1_INTERLACE_EN(x) BIT_MASK(x, 1, 15) - #define v_WIN0_YRGB_DEFLICK_EN(x) BIT_MASK(x, 1, 16) - #define v_WIN0_CBR_DEFLICK_EN(x) BIT_MASK(x, 1, 17) - #define v_WIN0_ALPHA_MODE(x) BIT_MASK(x, 1, 18) - #define v_WIN1_ALPHA_MODE(x) BIT_MASK(x, 1, 19) - #define v_WIN0_CSC_MODE(x) BIT_MASK(x, 3, 20) - #define v_WIN0_YUV_CLIP(x) BIT_MASK(x, 1, 23) - #define v_TVE_MODE(x) BIT_MASK(x, 1, 25) - #define v_SW_UV_OFFSET_EN(x) BIT_MASK(x, 1, 26) /* rk312x */ - #define v_DITHER_DOWN_SEL(x) BIT_MASK(x, 1, 27) /* rk312x */ - #define v_HWC_ALPHA_MODE(x) BIT_MASK(x, 1, 28) - #define v_ALPHA_MODE_SEL0(x) BIT_MASK(x, 1, 29) - #define v_ALPHA_MODE_SEL1(x) BIT_MASK(x, 1, 30) - #define v_WIN1_DIFF_DCLK_EN(x) BIT_MASK(x, 1, 31) /* rk3036 */ - #define v_SW_OVERLAY_MODE(x) BIT_MASK(x, 1, 31) /* rk312x */ - -#define DSP_CTRL1 (0x08) - #define m_BG_COLOR BIT(0xffffff, 0) - #define m_BG_B BIT(0xff, 0) - #define m_BG_G BIT(0xff, 8) - #define m_BG_R BIT(0xff, 16) - #define m_BLANK_EN BIT(1, 24) - #define m_BLACK_EN BIT(1, 25) - #define m_DSP_BG_SWAP BIT(1, 26) - #define m_DSP_RB_SWAP BIT(1, 27) - #define m_DSP_RG_SWAP BIT(1, 28) - #define m_DSP_DELTA_SWAP BIT(1, 29) /* rk3036 */ - #define m_DSP_DUMMY_SWAP BIT(1, 30) /* rk3036 */ - #define m_DSP_OUT_ZERO BIT(1, 31) - - #define v_BG_COLOR(x) BIT_MASK(x, 0xffffff, 0) - #define v_BG_B(x) BIT_MASK(x, 0xff, 0) - #define v_BG_G(x) BIT_MASK(x, 0xff, 8) - #define v_BG_R(x) BIT_MASK(x, 0xff, 16) - #define v_BLANK_EN(x) BIT_MASK(x, 1, 24) - #define v_BLACK_EN(x) BIT_MASK(x, 1, 25) - #define v_DSP_BG_SWAP(x) BIT_MASK(x, 1, 26) - #define v_DSP_RB_SWAP(x) BIT_MASK(x, 1, 27) - #define v_DSP_RG_SWAP(x) BIT_MASK(x, 1, 28) - #define v_DSP_DELTA_SWAP(x) BIT_MASK(x, 1, 29) /* rk3036 */ - #define v_DSP_DUMMY_SWAP(x) BIT_MASK(x, 1, 30) /* rk3036 */ - #define v_DSP_OUT_ZERO(x) BIT_MASK(x, 1, 31) - -#define INT_SCALER (0x0c) /* only use for rk312x */ - #define m_SCALER_EMPTY_INTR_EN BIT(1, 0) - #define m_SCLAER_EMPTY_INTR_CLR BIT(1, 1) - #define m_SCLAER_EMPTY_INTR_STA BIT(1, 2) - #define m_FS_MASK_EN BIT(1, 3) - #define m_HDMI_HSYNC_POL BIT(1, 4) - #define m_HDMI_VSYNC_POL BIT(1, 5) - #define m_HDMI_DEN_POL BIT(1, 6) - - #define v_SCALER_EMPTY_INTR_EN(x) BIT_MASK(x, 1, 0) - #define v_SCLAER_EMPTY_INTR_CLR(x) BIT_MASK(x, 1, 1) - #define v_SCLAER_EMPTY_INTR_STA(x) BIT_MASK(x, 1, 2) - #define v_FS_MASK_EN(x) BIT_MASK(x, 1, 3) - #define v_HDMI_HSYNC_POL(x) BIT_MASK(x, 1, 4) - #define v_HDMI_VSYNC_POL(x) BIT_MASK(x, 1, 5) - #define v_HDMI_DEN_POL(x) BIT_MASK(x. 1, 6) - -#define INT_STATUS (0x10) - #define m_HS_INT_STA BIT(1, 0) - #define m_FS_INT_STA BIT(1, 1) - #define m_LF_INT_STA BIT(1, 2) - #define m_BUS_ERR_INT_STA BIT(1, 3) - #define m_HS_INT_EN BIT(1, 4) - #define m_FS_INT_EN BIT(1, 5) - #define m_LF_INT_EN BIT(1, 6) - #define m_BUS_ERR_INT_EN BIT(1, 7) - #define m_HS_INT_CLEAR BIT(1, 8) - #define m_FS_INT_CLEAR BIT(1, 9) - #define m_LF_INT_CLEAR BIT(1, 10) - #define m_BUS_ERR_INT_CLEAR BIT(1, 11) - #define m_LF_INT_NUM BIT(0xfff, 12) - #define m_WIN0_EMPTY_INT_EN BIT(1, 24) - #define m_WIN1_EMPTY_INT_EN BIT(1, 25) - #define m_WIN0_EMPTY_INT_CLEAR BIT(1, 26) - #define m_WIN1_EMPTY_INT_CLEAR BIT(1, 27) - #define m_WIN0_EMPTY_INT_STA BIT(1, 28) - #define m_WIN1_EMPTY_INT_STA BIT(1, 29) - #define m_FS_RAW_STA BIT(1, 30) - #define m_LF_RAW_STA BIT(1, 31) - - #define v_HS_INT_EN(x) BIT_MASK(x, 1, 4) - #define v_FS_INT_EN(x) BIT_MASK(x, 1, 5) - #define v_LF_INT_EN(x) BIT_MASK(x, 1, 6) - #define v_BUS_ERR_INT_EN(x) BIT_MASK(x, 1, 7) - #define v_HS_INT_CLEAR(x) BIT_MASK(x, 1, 8) - #define v_FS_INT_CLEAR(x) BIT_MASK(x, 1, 9) - #define v_LF_INT_CLEAR(x) BIT_MASK(x, 1, 10) - #define v_BUS_ERR_INT_CLEAR(x) BIT_MASK(x, 1, 11) - #define v_LF_INT_NUM(x) BIT_MASK(x, 0xfff, 12) - #define v_WIN0_EMPTY_INT_EN(x) BIT_MASK(x, 1, 24) - #define v_WIN1_EMPTY_INT_EN(x) BIT_MASK(x, 1, 25) - #define v_WIN0_EMPTY_INT_CLEAR(x) BIT_MASK(x, 1, 26) - #define v_WIN1_EMPTY_INT_CLEAR(x) BIT_MASK(x, 1, 27) - -#define ALPHA_CTRL (0x14) - #define m_WIN0_ALPHA_EN BIT(1, 0) - #define m_WIN1_ALPHA_EN BIT(1, 1) - #define m_HWC_ALPAH_EN BIT(1, 2) - #define m_WIN1_PREMUL_SCALE BIT(1, 3) /* rk3036 */ - #define m_WIN0_ALPHA_VAL BIT(0xff, 4) - #define m_WIN1_ALPHA_VAL BIT(0xff, 12) - #define m_HWC_ALPAH_VAL BIT(0xff, 20) - - #define v_WIN0_ALPHA_EN(x) BIT_MASK(x, 1, 0) - #define v_WIN1_ALPHA_EN(x) BIT_MASK(x, 1, 1) - #define v_HWC_ALPAH_EN(x) BIT_MASK(x, 1, 2) - #define v_WIN1_PREMUL_SCALE(x) BIT_MASK(x, 1, 3) /* rk3036 */ - #define v_WIN0_ALPHA_VAL(x) BIT_MASK(x, 0xff, 4) - #define v_WIN1_ALPHA_VAL(x) BIT_MASK(x, 0xff, 12) - #define v_HWC_ALPAH_VAL(x) BIT_MASK(x, 0xff, 20) - -#define WIN0_COLOR_KEY (0x18) -#define WIN1_COLOR_KEY (0x1c) - #define m_COLOR_KEY_VAL BIT(0xffffff, 0) - #define m_COLOR_KEY_EN BIT(1, 24) - - #define v_COLOR_KEY_VAL(x) BIT_MASK(x, 0xffffff, 0) - #define v_COLOR_KEY_EN(x) BIT_MASK(x, 1, 24) - -/* Layer Registers */ -#define WIN0_YRGB_MST (0x20) -#define WIN0_CBR_MST (0x24) -#define WIN1_MST (0xa0) /* rk3036 */ -#define WIN1_MST_RK312X (0x4c) /* rk312x */ -#define HWC_MST (0x58) - -#define WIN1_VIR (0x28) -#define WIN0_VIR (0x30) - #define m_YRGB_VIR BIT(0x1fff, 0) - #define m_CBBR_VIR BIT(0x1fff, 16) - - #define v_YRGB_VIR(x) BIT_MASK(x, 0x1fff, 0) - #define v_CBBR_VIR(x) BIT_MASK(x, 0x1fff, 16) - - #define v_ARGB888_VIRWIDTH(x) BIT_MASK(x, 0x1fff, 0) - #define v_RGB888_VIRWIDTH(x) BIT_MASK(((x*3)>>2)+((x)%3), 0x1fff, 0) - #define v_RGB565_VIRWIDTH(x) BIT_MASK(DIV_ROUND_UP(x, 2), 0x1fff, 0) - #define v_YUV_VIRWIDTH(x) BIT_MASK(DIV_ROUND_UP(x, 4), 0x1fff, 0) - #define v_CBCR_VIR(x) BIT_MASK(x, 0x1fff, 16) - -#define WIN0_ACT_INFO (0x34) -#define WIN1_ACT_INFO (0xb4) /* rk3036 */ - #define m_ACT_WIDTH BIT(0x1fff, 0) - #define m_ACT_HEIGHT BIT(0x1fff, 16) - - #define v_ACT_WIDTH(x) BIT_MASK(x - 1, 0x1fff, 0) - #define v_ACT_HEIGHT(x) BIT_MASK(x - 1, 0x1fff, 16) - -#define WIN0_DSP_INFO (0x38) -#define WIN1_DSP_INFO (0xb8) /* rk3036 */ -#define WIN1_DSP_INFO_RK312X (0x50) /* rk312x */ - #define m_DSP_WIDTH BIT(0x7ff, 0) - #define m_DSP_HEIGHT BIT(0x7ff, 16) - - #define v_DSP_WIDTH(x) BIT_MASK(x - 1, 0x7ff, 0) - #define v_DSP_HEIGHT(x) BIT_MASK(x - 1, 0x7ff, 16) - -#define WIN0_DSP_ST (0x3c) -#define WIN1_DSP_ST (0xbc) /* rk3036 */ -#define WIN1_DSP_ST_RK312X (0x54) /* rk312x */ -#define HWC_DSP_ST (0x5c) - #define m_DSP_STX BIT(0xfff, 0) - #define m_DSP_STY BIT(0xfff, 16) - - #define v_DSP_STX(x) BIT_MASK(x, 0xfff, 0) - #define v_DSP_STY(x) BIT_MASK(x, 0xfff, 16) - -#define WIN0_SCL_FACTOR_YRGB (0x40) -#define WIN0_SCL_FACTOR_CBR (0x44) -#define WIN1_SCL_FACTOR_YRGB (0xc0) /* rk3036 */ - #define m_X_SCL_FACTOR BIT(0xffff, 0) - #define m_Y_SCL_FACTOR BIT(0xffff, 16) - - #define v_X_SCL_FACTOR(x) BIT_MASK(x, 0xffff, 0) - #define v_Y_SCL_FACTOR(x) BIT_MASK(x, 0xffff, 16) - -#define WIN0_SCL_OFFSET (0x48) -#define WIN1_SCL_OFFSET (0xc8) /* rk3036 */ - -/* LUT Registers */ -#define WIN1_LUT_ADDR (0x0400) /* rk3036 */ -#define HWC_LUT_ADDR (0x0800) -#define DSP_LUT_ADDR (0x0c00) /* rk312x */ - -/* Display Infomation Registers */ -#define DSP_HTOTAL_HS_END (0x6c) - #define v_HSYNC(x) BIT_MASK(x, 0xfff, 0) /* hsync pulse width */ - #define v_HORPRD(x) BIT_MASK(x, 0xfff, 16) /* horizontal period */ - -#define DSP_HACT_ST_END (0x70) - #define v_HAEP(x) BIT_MASK(x, 0xfff, 0) /* horizontal active end point */ - #define v_HASP(x) BIT_MASK(x, 0xfff, 16) /* horizontal active start point */ - -#define DSP_VTOTAL_VS_END (0x74) - #define v_VSYNC(x) BIT_MASK(x, 0xfff, 0) - #define v_VERPRD(x) BIT_MASK(x, 0xfff, 16) - -#define DSP_VACT_ST_END (0x78) - #define v_VAEP(x) BIT_MASK(x, 0xfff, 0) - #define v_VASP(x) BIT_MASK(x, 0xfff, 16) - -#define DSP_VS_ST_END_F1 (0x7c) - #define v_VSYNC_END_F1(x) BIT_MASK(x, 0xfff, 0) - #define v_VSYNC_ST_F1(x) BIT_MASK(x, 0xfff, 16) -#define DSP_VACT_ST_END_F1 (0x80) - #define v_VAEP_F1(x) BIT_MASK(x, 0xfff, 0) - #define v_VASP_F1(x) BIT_MASK(x, 0xfff, 16) - -/* Scaler Registers - * Only used for rk312x - */ -#define SCALER_CTRL (0xa0) - #define m_SCALER_EN BIT(1, 0) - #define m_SCALER_SYNC_INVERT BIT(1, 2) - #define m_SCALER_DEN_INVERT BIT(1, 3) - #define m_SCALER_OUT_ZERO BIT(1, 4) - #define m_SCALER_OUT_EN BIT(1, 5) - #define m_SCALER_VSYNC_MODE BIT(3, 6) - #define m_SCALER_VSYNC_VST BIT(0xff, 8) - - #define v_SCALER_EN(x) BIT_MASK(x, 1, 0) - #define v_SCALER_SYNC_INVERT(x) BIT_MASK(x, 1, 2) - #define v_SCALER_DEN_INVERT(x) BIT_MASK(x, 1, 3) - #define v_SCALER_OUT_ZERO(x) BIT_MASK(x, 1, 4) - #define v_SCALER_OUT_EN(x) BIT_MASK(x, 1, 5) - #define v_SCALER_VSYNC_MODE(x) BIT_MASK(x, 3, 6) - #define v_SCALER_VSYNC_VST(x) BIT_MASK(x, 0xff, 8) - -#define SCALER_FACTOR (0xa4) - #define m_SCALER_H_FACTOR BIT(0x3fff, 0) - #define m_SCALER_V_FACTOR BIT(0x3fff, 16) - - #define v_SCALER_H_FACTOR(x) BIT_MASK(x, 0x3fff, 0) - #define v_SCALER_V_FACTOR(x) BIT_MASK(x, 0x3fff, 16) - -#define SCALER_FRAME_ST (0xa8) - #define m_SCALER_FRAME_HST BIT(0xfff, 0) - #define m_SCALER_FRAME_VST BIT(0xfff, 16) - - #define v_SCALER_FRAME_HST(x) BIT_MASK(x, 0xfff, 0) - #define v_SCALER_FRAME_VST(x) BIT_MASK(x, 0xfff, 16) - -#define SCALER_DSP_HOR_TIMING (0xac) - #define m_SCALER_HTOTAL BIT(0xfff, 0) - #define m_SCALER_HS_END BIT(0xff, 16) - - #define v_SCALER_HTOTAL(x) BIT_MASK(x, 0xfff, 0) - #define v_SCALER_HS_END(x) BIT_MASK(x, 0xff, 16) - -#define SCALER_DSP_HACT_ST_END (0xb0) - #define m_SCALER_HAEP BIT(0xfff, 0) - #define m_SCALER_HASP BIT(0x3ff, 16) - - #define v_SCALER_HAEP(x) BIT_MASK(x, 0xfff, 0) - #define v_SCALER_HASP(x) BIT_MASK(x, 0x3ff, 16) - -#define SCALER_DSP_VER_TIMING (0xb4) - #define m_SCALER_VTOTAL BIT(0xfff, 0) - #define m_SCALER_VS_END BIT(0xff, 16) - - #define v_SCALER_VTOTAL(x) BIT_MASK(0xfff, 0) - #define v_SCALER_VS_END(x) BIT_MASK(0xff, 16) - -#define SCALER_DSP_VACT_ST_END (0xb8) - #define m_SCALER_VAEP BIT(0xfff, 0) - #define m_SCALER_VASP BIT(0xff, 16) - - #define v_SCALER_VAEP(x) BIT_MASK(x, 0xfff, 0) - #define v_SCALER_VASP(x) BIT_MASK(x, 0xff, 16) - -#define SCALER_DSP_HBOR_TIMING (0xbc) - #define m_SCALER_HBOR_END BIT(0xfff, 0) - #define m_SCALER_HBOR_ST BIT(0x3ff, 16) - - #define v_SCALER_HBOR_END(x) BIT_MASK(x, 0xfff, 0) - #define v_SCALER_HBOR_ST(x) BIT_MASK(x, 0x3ff, 16) - -#define SCALER_DSP_VBOR_TIMING (0xc0) - #define m_SCALER_VBOR_END BIT(0xfff, 0) - #define m_SCALER_VBOR_ST BIT(0xff, 16) - - #define v_SCALER_VBOR_END(x) BIT_MASK(x, 0xfff, 0) - #define v_SCALER_VBOR_ST(x) BIT_MASK(x, 0xff, 16) - -/* BCSH Registers */ -#define BCSH_CTRL (0xd0) - #define m_BCSH_EN BIT(1, 0) - #define m_BCSH_R2Y_CSC_MODE BIT(1, 1) /* rk312x */ - #define m_BCSH_OUT_MODE BIT(3, 2) - #define m_BCSH_Y2R_CSC_MODE BIT(3, 4) - #define m_BCSH_Y2R_EN BIT(1, 6) /* rk312x */ - #define m_BCSH_R2Y_EN BIT(1, 7) /* rk312x */ - - #define v_BCSH_EN(x) BIT_MASK(x, 1, 0) - #define v_BCSH_R2Y_CSC_MODE(x) BIT_MASK(x, 1, 1) /* rk312x */ - #define v_BCSH_OUT_MODE(x) BIT_MASK(x, 3, 2) - #define v_BCSH_CSC_MODE(x) BIT_MASK(x, 3, 4) - #define v_BCSH_Y2R_EN(x) BIT_MASK(x, 1, 6) /* rk312x */ - #define v_BCSH_R2Y_EN(x) BIT_MASK(x, 1, 7) /* rk312x */ - -#define BCSH_COLOR_BAR (0xd4) - #define m_BCSH_COLOR_BAR_Y BIT(0xff, 0) - #define m_BCSH_COLOR_BAR_U BIT(0xff, 8) - #define m_BCSH_COLOR_BAR_V BIT(0xff, 16) - - #define v_BCSH_COLOR_BAR_Y(x) BIT_MASK(x, 0xff, 0) - #define v_BCSH_COLOR_BAR_U(x) BIT_MASK(x, 0xff, 8) - #define v_BCSH_COLOR_BAR_V(x) BIT_MASK(x, 0xff, 16) - -#define BCSH_BCS (0xd8) - #define m_BCSH_BRIGHTNESS BIT(0x1f, 0) - #define m_BCSH_CONTRAST BIT(0xff, 8) - #define m_BCSH_SAT_CON BIT(0x1ff, 16) - - #define v_BCSH_BRIGHTNESS(x) BIT_MASK(x, 0x1f, 0) - #define v_BCSH_CONTRAST(x) BIT_MASK(x, 0xff, 8) - #define v_BCSH_SAT_CON(x) BIT_MASK(x, 0x1ff, 16) - -#define BCSH_H (0xdc) - #define m_BCSH_SIN_HUE BIT(0xff, 0) - #define m_BCSH_COS_HUE BIT(0xff, 16) - - #define v_BCSH_SIN_HUE(x) BIT_MASK(x, 0xff, 0) - #define v_BCSH_COS_HUE(x) BIT_MASK(x, 0xff, 16) - -#define FRC_LOWER01_0 (0xe0) -#define FRC_LOWER01_1 (0xe4) -#define FRC_LOWER10_0 (0xe8) -#define FRC_LOWER10_1 (0xec) -#define FRC_LOWER11_0 (0xf0) -#define FRC_LOWER11_1 (0xf4) - -/* Bus Register */ -#define AXI_BUS_CTRL (0x2c) - #define m_IO_PAD_CLK BIT(1, 31) - #define m_CORE_CLK_DIV_EN BIT(1, 30) - #define m_MIPI_DCLK_INVERT BIT(1, 29) /* rk312x */ - #define m_MIPI_DCLK_EN BIT(1, 28) /* rk312x */ - #define m_LVDS_DCLK_INVERT BIT(1, 27) /* rk312x */ - #define m_LVDS_DCLK_EN BIT(1, 26) /* rk312x */ - #define m_RGB_DCLK_INVERT BIT(1, 25) /* rk312x */ - #define m_RGB_DCLK_EN BIT(1, 24) /* rk312x */ - #define m_HDMI_DCLK_INVERT BIT(1, 23) - #define m_HDMI_DCLK_EN BIT(1, 22) - #define m_TVE_DAC_DCLK_INVERT BIT(1, 21) - #define m_TVE_DAC_DCLK_EN BIT(1, 20) - #define m_HDMI_DCLK_DIV_EN BIT(1, 19) - #define m_AXI_OUTSTANDING_MAX_NUM BIT(0x1f, 12) - #define m_AXI_MAX_OUTSTANDING_EN BIT(1, 11) - #define m_MMU_EN BIT(1, 10) - #define m_NOC_HURRY_THRESHOLD BIT(0xf, 6) - #define m_NOC_HURRY_VALUE BIT(3, 4) - #define m_NOC_HURRY_EN BIT(1, 3) - #define m_NOC_QOS_VALUE BIT(3, 1) - #define m_NOC_QOS_EN BIT(1, 0) - - #define v_IO_PAD_CLK(x) BIT_MASK(x, 1, 31) - #define v_CORE_CLK_DIV_EN(x) BIT_MASK(x, 1, 30) - #define v_MIPI_DCLK_INVERT(x) BIT_MASK(x, 1, 29) - #define v_MIPI_DCLK_EN(x) BIT_MASK(x, 1, 28) - #define v_LVDS_DCLK_INVERT(x) BIT_MASK(x, 1, 27) - #define v_LVDS_DCLK_EN(x) BIT_MASK(x, 1, 26) - #define v_RGB_DCLK_INVERT(x) BIT_MASK(x, 1, 25) - #define v_RGB_DCLK_EN(x) BIT_MASK(x, 1, 24) - #define v_HDMI_DCLK_INVERT(x) BIT_MASK(x, 1, 23) - #define v_HDMI_DCLK_EN(x) BIT_MASK(x, 1, 22) - #define v_TVE_DAC_DCLK_INVERT(x) BIT_MASK(x, 1, 21) - #define v_TVE_DAC_DCLK_EN(x) BIT_MASK(x, 1, 20) - #define v_HDMI_DCLK_DIV_EN(x) BIT_MASK(x, 1, 19) - #define v_AXI_OUTSTANDING_MAX_NUM(x) BIT_MASK(x, 0x1f, 12) - #define v_AXI_MAX_OUTSTANDING_EN(x) BIT_MASK(x, 1, 11) - #define v_MMU_EN(x) BIT_MASK(x, 1, 10) - #define v_NOC_HURRY_THRESHOLD(x) BIT_MASK(x, 0xf, 6) - #define v_NOC_HURRY_VALUE(x) BIT_MASK(x, 3, 4) - #define v_NOC_HURRY_EN(x) BIT_MASK(x, 1, 3) - #define v_NOC_QOS_VALUE(x) BIT_MASK(x, 3, 1) - #define v_NOC_QOS_EN(x) BIT_MASK(x, 1, 0) - -#define GATHER_TRANSFER (0x84) - #define m_WIN1_AXI_GATHER_NUM BIT(0xf, 12) - #define m_WIN0_CBCR_AXI_GATHER_NUM BIT(0x7, 8) - #define m_WIN0_YRGB_AXI_GATHER_NUM BIT(0xf, 4) - #define m_WIN1_AXI_GAHTER_EN BIT(1, 2) - #define m_WIN0_CBCR_AXI_GATHER_EN BIT(1, 1) - #define m_WIN0_YRGB_AXI_GATHER_EN BIT(1, 0) - - #define v_WIN1_AXI_GATHER_NUM(x) BIT_MASK(x, 0xf, 12) - #define v_WIN0_CBCR_AXI_GATHER_NUM(x) BIT_MASK(x, 0x7, 8) - #define v_WIN0_YRGB_AXI_GATHER_NUM(x) BIT_MASK(x, 0xf, 4) - #define v_WIN1_AXI_GAHTER_EN(x) BIT_MASK(x, 1, 2) - #define v_WIN0_CBCR_AXI_GATHER_EN(x) BIT_MASK(x, 1, 1) - #define v_WIN0_YRGB_AXI_GATHER_EN(x) BIT_MASK(x, 1, 0) - -#define VERSION_INFO (0x94) - #define m_MAJOR BIT(0xff, 24) - #define m_MINOR BIT(0xff, 16) - #define m_BUILD BIT(0xffff) - -#define REG_CFG_DONE (0x90) - -/* TV Control Registers */ -#define TV_CTRL (0x200) -#define TV_SYNC_TIMING (0x204) -#define TV_ACT_TIMING (0x208) -#define TV_ADJ_TIMING (0x20c) -#define TV_FREQ_SC (0x210) -#define TV_FILTER0 (0x214) -#define TV_FILTER1 (0x218) -#define TV_FILTER2 (0x21C) -#define TV_ACT_ST (0x234) -#define TV_ROUTING (0x238) -#define TV_SYNC_ADJUST (0x250) -#define TV_STATUS (0x254) -#define TV_RESET (0x268) -#define TV_SATURATION (0x278) -#define TV_BW_CTRL (0x28C) -#define TV_BRIGHTNESS_CONTRAST (0x290) - - -/* MMU registers */ -#define MMU_DTE_ADDR (0x0300) - #define m_MMU_DTE_ADDR BIT(0xffffffff, 0) - #define v_MMU_DTE_ADDR(x) BIT_MASK(x, 0xffffffff, 0) - -#define MMU_STATUS (0x0304) - #define m_PAGING_ENABLED BIT(1, 0) - #define m_PAGE_FAULT_ACTIVE BIT(1, 1) - #define m_STAIL_ACTIVE BIT(1, 2) - #define m_MMU_IDLE BIT(1, 3) - #define m_REPLAY_BUFFER_EMPTY BIT(1, 4) - #define m_PAGE_FAULT_IS_WRITE BIT(1, 5) - #define m_PAGE_FAULT_BUS_ID BIT(0x1f, 6) - - #define v_PAGING_ENABLED(x) BIT_MASK(x, 1, 0) - #define v_PAGE_FAULT_ACTIVE(x) BIT_MASK(x, 1, 1) - #define v_STAIL_ACTIVE(x) BIT_MASK(x, 1, 2) - #define v_MMU_IDLE(x) BIT_MASK(x, 1, 3) - #define v_REPLAY_BUFFER_EMPTY(x) BIT_MASK(x, 1, 4) - #define v_PAGE_FAULT_IS_WRITE(x) BIT_MASK(x, 1, 5) - #define v_PAGE_FAULT_BUS_ID(x) BIT_MASK(x, 0x1f, 6) - -#define MMU_COMMAND (0x0308) - #define m_MMU_CMD BIT(0x7, 0) - #define v_MMU_CMD(x) BIT_MASK(x, 0x7, 0) - -#define MMU_PAGE_FAULT_ADDR (0x030c) - #define m_PAGE_FAULT_ADDR BIT(0xffffffff, 0) - #define v_PAGE_FAULT_ADDR(x) BIT_MASK(x, 0xffffffff, 0) - -#define MMU_ZAP_ONE_LINE (0x0310) - #define m_MMU_ZAP_ONE_LINE BIT(0xffffffff, 0) - #define v_MMU_ZAP_ONE_LINE(x) BIT_MASK(x, 0xffffffff, 0) - -#define MMU_INT_RAWSTAT (0x0314) - #define m_PAGE_FAULT_RAWSTAT BIT(1, 0) - #define m_READ_BUS_ERROR_RAWSTAT BIT(1, 1) - - #define v_PAGE_FAULT_RAWSTAT(x) BIT(x, 1, 0) - #define v_READ_BUS_ERROR_RAWSTAT(x) BIT(x, 1, 1) - -#define MMU_INT_CLEAR (0x0318) - #define m_PAGE_FAULT_CLEAR BIT(1, 0) - #define m_READ_BUS_ERROR_CLEAR BIT(1, 1) - - #define v_PAGE_FAULT_CLEAR(x) BIT(x, 1, 0) - #define v_READ_BUS_ERROR_CLEAR(x) BIT(x, 1, 1) - -#define MMU_INT_MASK (0x031c) - #define m_PAGE_FAULT_MASK BIT(1, 0) - #define m_READ_BUS_ERROR_MASK BIT(1, 1) - - #define v_PAGE_FAULT_MASK(x) BIT(x, 1, 0) - #define v_READ_BUS_ERROR_MASK(x) BIT(x, 1, 1) - -#define MMU_INT_STATUS (0x0320) - #define m_PAGE_FAULT_STATUS BIT(1, 0) - #define m_READ_BUS_ERROR_STATUS BIT(1, 1) - - #define v_PAGE_FAULT_STATUS(x) BIT(x, 1, 0) - #define v_READ_BUS_ERROR_STATUS(x) BIT(x, 1, 1) - -#define MMU_AUTO_GATING (0x0324) - #define m_MMU_AUTO_GATING BIT(1, 0) - #define v_MMU_AUTO_GATING(x) BIT(x, 1, 0) - - -enum _vop_dma_burst { - DMA_BURST_16 = 0, - DMA_BURST_8, - DMA_BURST_4 -}; - -enum _vop_format_e { - VOP_FORMAT_ARGB888 = 0, - VOP_FORMAT_RGB888, - VOP_FORMAT_RGB565, - VOP_FORMAT_YCBCR420 = 4, - VOP_FORMAT_YCBCR422, - VOP_FORMAT_YCBCR444 -}; - -enum _vop_tv_mode { - TV_NTSC, - TV_PAL, -}; - -enum _vop_csc_mode { - VOP_CSC_BT601 = 0, - VOP_CSC_JPEG, - VOP_CSC_BT709 -}; - -enum _vop_hwc_size { - VOP_HWC_SIZE_32, - VOP_HWC_SIZE_64 -}; - -#define CalScale(x, y) ((((u32)(x - 1)) * 0x1000) / (y - 1)) - -struct rk_lcdc_drvdata { - u8 soc_type; - u32 reserve; -}; - -struct lcdc_device { - int id; - u8 soc_type; - struct rk_lcdc_driver driver; - struct device *dev; - struct rk_screen *screen; - - void __iomem *regs; - void *regsbak; /* back up reg */ - u32 reg_phy_base; /* physical basic address of lcdc register */ - u32 len; /* physical map length of lcdc register */ - spinlock_t reg_lock; /* one time only one process allowed to config the register */ - - int __iomem *dsp_lut_addr_base; - - int prop; /* used for primary or extended display device */ - bool pre_init; - bool pwr18; /* if lcdc use 1.8v power supply */ - bool clk_on; /* if aclk or hclk is closed ,acess to register is not allowed */ - u8 atv_layer_cnt; /* active layer counter,when atv_layer_cnt = 0,lcdc is disable*/ - - unsigned int irq; - - struct clk *pd; /* lcdc power domain */ - struct clk *hclk; /* lcdc AHP clk */ - struct clk *dclk; /* lcdc dclk */ - struct clk *aclk; /* lcdc share memory frequency */ - u32 pixclock; - - u32 standby; /* 1:standby,0:work */ -}; - -static inline void lcdc_writel(struct lcdc_device *lcdc_dev, u32 offset, u32 v) -{ - u32 *_pv = (u32*)lcdc_dev->regsbak; - _pv += (offset >> 2); - *_pv = v; - writel_relaxed(v, lcdc_dev->regs + offset); -} - -static inline u32 lcdc_readl(struct lcdc_device *lcdc_dev, u32 offset) -{ - u32 v; - u32 *_pv = (u32*)lcdc_dev->regsbak; - _pv += (offset >> 2); - v = readl_relaxed(lcdc_dev->regs + offset); - *_pv = v; - return v; -} - -static inline u32 lcdc_read_bit(struct lcdc_device *lcdc_dev, u32 offset, - u32 msk) -{ - u32 _v = readl_relaxed(lcdc_dev->regs + offset); - _v &= msk; - return (_v? 1 : 0); -} - -static inline void lcdc_set_bit(struct lcdc_device *lcdc_dev, u32 offset, - u32 msk) -{ - u32* _pv = (u32*)lcdc_dev->regsbak; - _pv += (offset >> 2); - (*_pv) |= msk; - writel_relaxed(*_pv, lcdc_dev->regs + offset); -} - -static inline void lcdc_clr_bit(struct lcdc_device *lcdc_dev, u32 offset, - u32 msk) -{ - u32* _pv = (u32*)lcdc_dev->regsbak; - _pv += (offset >> 2); - (*_pv) &= (~msk); - writel_relaxed(*_pv, lcdc_dev->regs + offset); -} - -static inline void lcdc_msk_reg(struct lcdc_device *lcdc_dev, u32 offset, - u32 msk, u32 v) -{ - u32 *_pv = (u32*)lcdc_dev->regsbak; - _pv += (offset >> 2); - (*_pv) &= (~msk); - (*_pv) |= v; - writel_relaxed(*_pv, lcdc_dev->regs + offset); -} - -static inline void lcdc_cfg_done(struct lcdc_device *lcdc_dev) -{ - writel_relaxed(0x01, lcdc_dev->regs + REG_CFG_DONE); - dsb(); -} - -#endif /* _RK31XX_LCDC_H_ */ -- 2.34.1