From 483f22d8173be97b6e5f337a46b2bff927682d77 Mon Sep 17 00:00:00 2001
From: Andrew Lenharth <andrewl@lenharth.org>
Date: Wed, 13 Apr 2005 03:47:03 +0000
Subject: [PATCH] added all flavors of zap for anding

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21276 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Target/Alpha/AlphaISelPattern.cpp | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/lib/Target/Alpha/AlphaISelPattern.cpp b/lib/Target/Alpha/AlphaISelPattern.cpp
index 9b07ff77a8f..fbd7bb1911e 100644
--- a/lib/Target/Alpha/AlphaISelPattern.cpp
+++ b/lib/Target/Alpha/AlphaISelPattern.cpp
@@ -1692,6 +1692,26 @@ unsigned ISel::SelectExpr(SDOperand N) {
       }
     //Fall through
   case ISD::AND:
+    //handle zap
+    if (opcode == ISD::AND && N.getOperand(1).getOpcode() == ISD::Constant)
+    {
+      uint64_t k = cast<ConstantSDNode>(N.getOperand(1))->getValue();
+      unsigned int build = 0;
+      for(int i = 0; i < 8; ++i)
+      {
+        if (k & 0xFF == 0xFF)
+          build |= 1 << i;
+        else if (k & 0xFF != 0)
+        { build = 0; break; }
+        k >>= 8;
+      }
+      if (build)
+      {
+        Tmp1 = SelectExpr(N.getOperand(0));
+        BuildMI(BB, Alpha::ZAPNOTi, 2, Result).addReg(Tmp1).addImm(build);
+        return Result;
+      }
+    }
   case ISD::OR:
     //Check operand(0) == Not
     if (N.getOperand(0).getOpcode() == ISD::XOR && 
-- 
2.34.1