From 4be7ca5721ce045492d53652aa9229326c51a5b0 Mon Sep 17 00:00:00 2001 From: Chris Lattner Date: Wed, 7 Apr 2004 04:27:16 +0000 Subject: [PATCH] Add support for shift instructions, wrap some long lines git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12740 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Sparc/InstSelectSimple.cpp | 39 +++++++++++++++--------- lib/Target/Sparc/SparcV8ISelSimple.cpp | 39 +++++++++++++++--------- lib/Target/SparcV8/InstSelectSimple.cpp | 39 +++++++++++++++--------- lib/Target/SparcV8/SparcV8ISelSimple.cpp | 39 +++++++++++++++--------- 4 files changed, 96 insertions(+), 60 deletions(-) diff --git a/lib/Target/Sparc/InstSelectSimple.cpp b/lib/Target/Sparc/InstSelectSimple.cpp index 3bae6a51522..c845bc5d075 100644 --- a/lib/Target/Sparc/InstSelectSimple.cpp +++ b/lib/Target/Sparc/InstSelectSimple.cpp @@ -57,9 +57,10 @@ namespace { BB = MBBMap[&LLVM_BB]; } - void visitBinaryOperator(BinaryOperator &I); - void visitCallInst(CallInst &I); - void visitReturnInst(ReturnInst &RI); + void visitBinaryOperator(Instruction &I); + void visitShiftInstruction(Instruction &I) { visitBinaryOperator(I); } + void visitCallInst(CallInst &I); + void visitReturnInst(ReturnInst &RI); void visitInstruction(Instruction &I) { std::cerr << "Unhandled instruction: " << I; @@ -169,31 +170,36 @@ void V8ISel::copyConstantToRegister(MachineBasicBlock *MBB, Constant *C, unsigned R) { if (ConstantInt *CI = dyn_cast (C)) { unsigned Class = getClass(C->getType()); + uint64_t Val = CI->getRawValue (); switch (Class) { case cByte: - BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (V8::G0).addImm ((uint8_t) CI->getRawValue ()); + BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (V8::G0).addImm((uint8_t)Val); return; case cShort: { unsigned TmpReg = makeAnotherReg (C->getType ()); - BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg).addImm (((uint16_t) CI->getRawValue ()) >> 10); - BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (TmpReg).addImm (((uint16_t) CI->getRawValue ()) & 0x03ff); + BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg) + .addImm (((uint16_t) Val) >> 10); + BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (TmpReg) + .addImm (((uint16_t) Val) & 0x03ff); return; } case cInt: { unsigned TmpReg = makeAnotherReg (C->getType ()); - BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg).addImm (((uint32_t) CI->getRawValue ()) >> 10); - BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (TmpReg).addImm (((uint32_t) CI->getRawValue ()) & 0x03ff); + BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg).addImm(((uint32_t)Val) >> 10); + BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (TmpReg) + .addImm (((uint32_t) Val) & 0x03ff); return; } case cLong: { unsigned TmpReg = makeAnotherReg (Type::UIntTy); - uint32_t topHalf, bottomHalf; - topHalf = (uint32_t) (CI->getRawValue () >> 32); - bottomHalf = (uint32_t) (CI->getRawValue () & 0x0ffffffffULL); + uint32_t topHalf = (uint32_t) (Val >> 32); + uint32_t bottomHalf = (uint32_t)Val; BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg).addImm (topHalf >> 10); - BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (TmpReg).addImm (topHalf & 0x03ff); + BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (TmpReg) + .addImm (topHalf & 0x03ff); BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg).addImm (bottomHalf >> 10); - BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (TmpReg).addImm (bottomHalf & 0x03ff); + BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (TmpReg) + .addImm (bottomHalf & 0x03ff); return; } default: @@ -282,7 +288,7 @@ void V8ISel::visitReturnInst(ReturnInst &I) { return; } -void V8ISel::visitBinaryOperator (BinaryOperator &I) { +void V8ISel::visitBinaryOperator (Instruction &I) { unsigned DestReg = getReg (I); unsigned Op0Reg = getReg (I.getOperand (0)); unsigned Op1Reg = getReg (I.getOperand (1)); @@ -298,6 +304,8 @@ void V8ISel::visitBinaryOperator (BinaryOperator &I) { case Instruction::And: OpCase = 3; break; case Instruction::Or: OpCase = 4; break; case Instruction::Xor: OpCase = 5; break; + case Instruction::Shl: OpCase = 6; break; + case Instruction::Shr: OpCase = 7+I.getType()->isSigned(); break; case Instruction::Div: case Instruction::Rem: { @@ -332,7 +340,8 @@ void V8ISel::visitBinaryOperator (BinaryOperator &I) { if (OpCase != ~0U) { static const unsigned Opcodes[] = { - V8::ADDrr, V8::SUBrr, V8::SMULrr, V8::ANDrr, V8::ORrr, V8::XORrr + V8::ADDrr, V8::SUBrr, V8::SMULrr, V8::ANDrr, V8::ORrr, V8::XORrr, + V8::SLLrr, V8::SRLrr, V8::SRArr }; BuildMI (BB, Opcodes[OpCase], 2, ResultReg).addReg (Op0Reg).addReg (Op1Reg); } diff --git a/lib/Target/Sparc/SparcV8ISelSimple.cpp b/lib/Target/Sparc/SparcV8ISelSimple.cpp index 3bae6a51522..c845bc5d075 100644 --- a/lib/Target/Sparc/SparcV8ISelSimple.cpp +++ b/lib/Target/Sparc/SparcV8ISelSimple.cpp @@ -57,9 +57,10 @@ namespace { BB = MBBMap[&LLVM_BB]; } - void visitBinaryOperator(BinaryOperator &I); - void visitCallInst(CallInst &I); - void visitReturnInst(ReturnInst &RI); + void visitBinaryOperator(Instruction &I); + void visitShiftInstruction(Instruction &I) { visitBinaryOperator(I); } + void visitCallInst(CallInst &I); + void visitReturnInst(ReturnInst &RI); void visitInstruction(Instruction &I) { std::cerr << "Unhandled instruction: " << I; @@ -169,31 +170,36 @@ void V8ISel::copyConstantToRegister(MachineBasicBlock *MBB, Constant *C, unsigned R) { if (ConstantInt *CI = dyn_cast (C)) { unsigned Class = getClass(C->getType()); + uint64_t Val = CI->getRawValue (); switch (Class) { case cByte: - BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (V8::G0).addImm ((uint8_t) CI->getRawValue ()); + BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (V8::G0).addImm((uint8_t)Val); return; case cShort: { unsigned TmpReg = makeAnotherReg (C->getType ()); - BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg).addImm (((uint16_t) CI->getRawValue ()) >> 10); - BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (TmpReg).addImm (((uint16_t) CI->getRawValue ()) & 0x03ff); + BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg) + .addImm (((uint16_t) Val) >> 10); + BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (TmpReg) + .addImm (((uint16_t) Val) & 0x03ff); return; } case cInt: { unsigned TmpReg = makeAnotherReg (C->getType ()); - BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg).addImm (((uint32_t) CI->getRawValue ()) >> 10); - BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (TmpReg).addImm (((uint32_t) CI->getRawValue ()) & 0x03ff); + BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg).addImm(((uint32_t)Val) >> 10); + BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (TmpReg) + .addImm (((uint32_t) Val) & 0x03ff); return; } case cLong: { unsigned TmpReg = makeAnotherReg (Type::UIntTy); - uint32_t topHalf, bottomHalf; - topHalf = (uint32_t) (CI->getRawValue () >> 32); - bottomHalf = (uint32_t) (CI->getRawValue () & 0x0ffffffffULL); + uint32_t topHalf = (uint32_t) (Val >> 32); + uint32_t bottomHalf = (uint32_t)Val; BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg).addImm (topHalf >> 10); - BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (TmpReg).addImm (topHalf & 0x03ff); + BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (TmpReg) + .addImm (topHalf & 0x03ff); BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg).addImm (bottomHalf >> 10); - BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (TmpReg).addImm (bottomHalf & 0x03ff); + BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (TmpReg) + .addImm (bottomHalf & 0x03ff); return; } default: @@ -282,7 +288,7 @@ void V8ISel::visitReturnInst(ReturnInst &I) { return; } -void V8ISel::visitBinaryOperator (BinaryOperator &I) { +void V8ISel::visitBinaryOperator (Instruction &I) { unsigned DestReg = getReg (I); unsigned Op0Reg = getReg (I.getOperand (0)); unsigned Op1Reg = getReg (I.getOperand (1)); @@ -298,6 +304,8 @@ void V8ISel::visitBinaryOperator (BinaryOperator &I) { case Instruction::And: OpCase = 3; break; case Instruction::Or: OpCase = 4; break; case Instruction::Xor: OpCase = 5; break; + case Instruction::Shl: OpCase = 6; break; + case Instruction::Shr: OpCase = 7+I.getType()->isSigned(); break; case Instruction::Div: case Instruction::Rem: { @@ -332,7 +340,8 @@ void V8ISel::visitBinaryOperator (BinaryOperator &I) { if (OpCase != ~0U) { static const unsigned Opcodes[] = { - V8::ADDrr, V8::SUBrr, V8::SMULrr, V8::ANDrr, V8::ORrr, V8::XORrr + V8::ADDrr, V8::SUBrr, V8::SMULrr, V8::ANDrr, V8::ORrr, V8::XORrr, + V8::SLLrr, V8::SRLrr, V8::SRArr }; BuildMI (BB, Opcodes[OpCase], 2, ResultReg).addReg (Op0Reg).addReg (Op1Reg); } diff --git a/lib/Target/SparcV8/InstSelectSimple.cpp b/lib/Target/SparcV8/InstSelectSimple.cpp index 3bae6a51522..c845bc5d075 100644 --- a/lib/Target/SparcV8/InstSelectSimple.cpp +++ b/lib/Target/SparcV8/InstSelectSimple.cpp @@ -57,9 +57,10 @@ namespace { BB = MBBMap[&LLVM_BB]; } - void visitBinaryOperator(BinaryOperator &I); - void visitCallInst(CallInst &I); - void visitReturnInst(ReturnInst &RI); + void visitBinaryOperator(Instruction &I); + void visitShiftInstruction(Instruction &I) { visitBinaryOperator(I); } + void visitCallInst(CallInst &I); + void visitReturnInst(ReturnInst &RI); void visitInstruction(Instruction &I) { std::cerr << "Unhandled instruction: " << I; @@ -169,31 +170,36 @@ void V8ISel::copyConstantToRegister(MachineBasicBlock *MBB, Constant *C, unsigned R) { if (ConstantInt *CI = dyn_cast (C)) { unsigned Class = getClass(C->getType()); + uint64_t Val = CI->getRawValue (); switch (Class) { case cByte: - BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (V8::G0).addImm ((uint8_t) CI->getRawValue ()); + BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (V8::G0).addImm((uint8_t)Val); return; case cShort: { unsigned TmpReg = makeAnotherReg (C->getType ()); - BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg).addImm (((uint16_t) CI->getRawValue ()) >> 10); - BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (TmpReg).addImm (((uint16_t) CI->getRawValue ()) & 0x03ff); + BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg) + .addImm (((uint16_t) Val) >> 10); + BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (TmpReg) + .addImm (((uint16_t) Val) & 0x03ff); return; } case cInt: { unsigned TmpReg = makeAnotherReg (C->getType ()); - BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg).addImm (((uint32_t) CI->getRawValue ()) >> 10); - BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (TmpReg).addImm (((uint32_t) CI->getRawValue ()) & 0x03ff); + BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg).addImm(((uint32_t)Val) >> 10); + BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (TmpReg) + .addImm (((uint32_t) Val) & 0x03ff); return; } case cLong: { unsigned TmpReg = makeAnotherReg (Type::UIntTy); - uint32_t topHalf, bottomHalf; - topHalf = (uint32_t) (CI->getRawValue () >> 32); - bottomHalf = (uint32_t) (CI->getRawValue () & 0x0ffffffffULL); + uint32_t topHalf = (uint32_t) (Val >> 32); + uint32_t bottomHalf = (uint32_t)Val; BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg).addImm (topHalf >> 10); - BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (TmpReg).addImm (topHalf & 0x03ff); + BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (TmpReg) + .addImm (topHalf & 0x03ff); BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg).addImm (bottomHalf >> 10); - BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (TmpReg).addImm (bottomHalf & 0x03ff); + BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (TmpReg) + .addImm (bottomHalf & 0x03ff); return; } default: @@ -282,7 +288,7 @@ void V8ISel::visitReturnInst(ReturnInst &I) { return; } -void V8ISel::visitBinaryOperator (BinaryOperator &I) { +void V8ISel::visitBinaryOperator (Instruction &I) { unsigned DestReg = getReg (I); unsigned Op0Reg = getReg (I.getOperand (0)); unsigned Op1Reg = getReg (I.getOperand (1)); @@ -298,6 +304,8 @@ void V8ISel::visitBinaryOperator (BinaryOperator &I) { case Instruction::And: OpCase = 3; break; case Instruction::Or: OpCase = 4; break; case Instruction::Xor: OpCase = 5; break; + case Instruction::Shl: OpCase = 6; break; + case Instruction::Shr: OpCase = 7+I.getType()->isSigned(); break; case Instruction::Div: case Instruction::Rem: { @@ -332,7 +340,8 @@ void V8ISel::visitBinaryOperator (BinaryOperator &I) { if (OpCase != ~0U) { static const unsigned Opcodes[] = { - V8::ADDrr, V8::SUBrr, V8::SMULrr, V8::ANDrr, V8::ORrr, V8::XORrr + V8::ADDrr, V8::SUBrr, V8::SMULrr, V8::ANDrr, V8::ORrr, V8::XORrr, + V8::SLLrr, V8::SRLrr, V8::SRArr }; BuildMI (BB, Opcodes[OpCase], 2, ResultReg).addReg (Op0Reg).addReg (Op1Reg); } diff --git a/lib/Target/SparcV8/SparcV8ISelSimple.cpp b/lib/Target/SparcV8/SparcV8ISelSimple.cpp index 3bae6a51522..c845bc5d075 100644 --- a/lib/Target/SparcV8/SparcV8ISelSimple.cpp +++ b/lib/Target/SparcV8/SparcV8ISelSimple.cpp @@ -57,9 +57,10 @@ namespace { BB = MBBMap[&LLVM_BB]; } - void visitBinaryOperator(BinaryOperator &I); - void visitCallInst(CallInst &I); - void visitReturnInst(ReturnInst &RI); + void visitBinaryOperator(Instruction &I); + void visitShiftInstruction(Instruction &I) { visitBinaryOperator(I); } + void visitCallInst(CallInst &I); + void visitReturnInst(ReturnInst &RI); void visitInstruction(Instruction &I) { std::cerr << "Unhandled instruction: " << I; @@ -169,31 +170,36 @@ void V8ISel::copyConstantToRegister(MachineBasicBlock *MBB, Constant *C, unsigned R) { if (ConstantInt *CI = dyn_cast (C)) { unsigned Class = getClass(C->getType()); + uint64_t Val = CI->getRawValue (); switch (Class) { case cByte: - BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (V8::G0).addImm ((uint8_t) CI->getRawValue ()); + BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (V8::G0).addImm((uint8_t)Val); return; case cShort: { unsigned TmpReg = makeAnotherReg (C->getType ()); - BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg).addImm (((uint16_t) CI->getRawValue ()) >> 10); - BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (TmpReg).addImm (((uint16_t) CI->getRawValue ()) & 0x03ff); + BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg) + .addImm (((uint16_t) Val) >> 10); + BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (TmpReg) + .addImm (((uint16_t) Val) & 0x03ff); return; } case cInt: { unsigned TmpReg = makeAnotherReg (C->getType ()); - BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg).addImm (((uint32_t) CI->getRawValue ()) >> 10); - BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (TmpReg).addImm (((uint32_t) CI->getRawValue ()) & 0x03ff); + BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg).addImm(((uint32_t)Val) >> 10); + BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (TmpReg) + .addImm (((uint32_t) Val) & 0x03ff); return; } case cLong: { unsigned TmpReg = makeAnotherReg (Type::UIntTy); - uint32_t topHalf, bottomHalf; - topHalf = (uint32_t) (CI->getRawValue () >> 32); - bottomHalf = (uint32_t) (CI->getRawValue () & 0x0ffffffffULL); + uint32_t topHalf = (uint32_t) (Val >> 32); + uint32_t bottomHalf = (uint32_t)Val; BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg).addImm (topHalf >> 10); - BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (TmpReg).addImm (topHalf & 0x03ff); + BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (TmpReg) + .addImm (topHalf & 0x03ff); BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg).addImm (bottomHalf >> 10); - BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (TmpReg).addImm (bottomHalf & 0x03ff); + BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (TmpReg) + .addImm (bottomHalf & 0x03ff); return; } default: @@ -282,7 +288,7 @@ void V8ISel::visitReturnInst(ReturnInst &I) { return; } -void V8ISel::visitBinaryOperator (BinaryOperator &I) { +void V8ISel::visitBinaryOperator (Instruction &I) { unsigned DestReg = getReg (I); unsigned Op0Reg = getReg (I.getOperand (0)); unsigned Op1Reg = getReg (I.getOperand (1)); @@ -298,6 +304,8 @@ void V8ISel::visitBinaryOperator (BinaryOperator &I) { case Instruction::And: OpCase = 3; break; case Instruction::Or: OpCase = 4; break; case Instruction::Xor: OpCase = 5; break; + case Instruction::Shl: OpCase = 6; break; + case Instruction::Shr: OpCase = 7+I.getType()->isSigned(); break; case Instruction::Div: case Instruction::Rem: { @@ -332,7 +340,8 @@ void V8ISel::visitBinaryOperator (BinaryOperator &I) { if (OpCase != ~0U) { static const unsigned Opcodes[] = { - V8::ADDrr, V8::SUBrr, V8::SMULrr, V8::ANDrr, V8::ORrr, V8::XORrr + V8::ADDrr, V8::SUBrr, V8::SMULrr, V8::ANDrr, V8::ORrr, V8::XORrr, + V8::SLLrr, V8::SRLrr, V8::SRArr }; BuildMI (BB, Opcodes[OpCase], 2, ResultReg).addReg (Op0Reg).addReg (Op1Reg); } -- 2.34.1