From 4d93acfd396ef7ac23f8902467f4d864d177b680 Mon Sep 17 00:00:00 2001 From: =?utf8?q?=E9=BB=84=E6=B6=9B?= Date: Wed, 22 Aug 2012 21:21:56 +0800 Subject: [PATCH] rk3066b: rename rk31 to rk3066b --- arch/arm/Kconfig | 13 - arch/arm/Makefile | 1 - arch/arm/configs/rk3066b_fpga_defconfig | 2 +- arch/arm/configs/rk3066b_sdk_defconfig | 338 +++++- arch/arm/mach-rk30/Kconfig | 19 +- arch/arm/mach-rk30/Makefile | 6 +- arch/arm/mach-rk30/board-rk3066b-sdk-camera.c | 443 ++++++++ arch/arm/mach-rk30/board-rk3066b-sdk-sdmmc.c | 98 +- arch/arm/mach-rk30/board-rk3066b-sdk.c | 457 +------- arch/arm/mach-rk30/clock.h | 2 +- arch/arm/mach-rk30/devices.c | 35 + arch/arm/mach-rk30/include/mach/io.h | 12 +- .../mach-rk30/include/mach/iomux-rk3066b.h | 531 ++++++++++ arch/arm/mach-rk30/include/mach/iomux.h | 559 +--------- arch/arm/mach-rk30/include/mach/rk30_camera.h | 12 +- arch/arm/mach-rk30/iomux-rk3066b.c | 147 +++ arch/arm/mach-rk30/iomux.c | 154 +-- arch/arm/plat-rk/Kconfig | 3 + arch/arm/tools/mach-types | 1 - drivers/gpio/Makefile | 1 - drivers/gpio/gpio-rk30.c | 8 +- drivers/i2c/busses/i2c-rk30.h | 2 +- drivers/media/video/Makefile | 4 - drivers/media/video/rk30_camera.c | 996 +++++++++--------- drivers/media/video/rk30_camera_oneframe.c | 11 +- drivers/mmc/host/rk29_sdmmc.c | 14 +- drivers/regulator/rk30-pwm-regulator.c | 2 +- drivers/usb/dwc_otg/dwc_otg_driver.c | 6 +- drivers/video/backlight/rk29_backlight.c | 4 +- drivers/video/rockchip/Kconfig | 10 +- drivers/video/rockchip/rga/Kconfig | 4 +- drivers/video/rockchip/rga/rga.h | 2 - sound/soc/codecs/rk610_codec.c | 8 +- sound/soc/rk29/Kconfig | 2 +- sound/soc/rk29/Makefile | 3 - sound/soc/rk29/rk30_i2s.c | 3 +- 36 files changed, 2064 insertions(+), 1849 deletions(-) create mode 100644 arch/arm/mach-rk30/board-rk3066b-sdk-camera.c create mode 100644 arch/arm/mach-rk30/include/mach/iomux-rk3066b.h create mode 100755 arch/arm/mach-rk30/iomux-rk3066b.c diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 8e04926d8d7a..b73174bedafe 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -895,19 +895,6 @@ config ARCH_RK30 help Support for Rockchip's RK30xx SoCs. -config ARCH_RK31 - bool "Rockchip RK31xx" - select PLAT_RK - select CPU_V7 - select ARM_GIC - select RK_PL330_DMA - select HAVE_SMP - select MIGHT_HAVE_CACHE_L2X0 - select ARM_ERRATA_764369 - select ARM_ERRATA_754322 - help - Support for Rockchip's RK31xx SoCs. - config PLAT_SPEAR bool "ST SPEAr" select ARM_AMBA diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 2e9474688af6..43c17789695f 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -174,7 +174,6 @@ machine-$(CONFIG_ARCH_REALVIEW) := realview machine-$(CONFIG_ARCH_RK29) := rk29 machine-$(CONFIG_ARCH_RK2928) := rk2928 machine-$(CONFIG_ARCH_RK30) := rk30 -machine-$(CONFIG_ARCH_RK31) := rk30 machine-$(CONFIG_ARCH_RPC) := rpc machine-$(CONFIG_ARCH_S3C2410) := s3c2410 s3c2400 s3c2412 s3c2416 s3c2440 s3c2443 machine-$(CONFIG_ARCH_S3C24A0) := s3c24a0 diff --git a/arch/arm/configs/rk3066b_fpga_defconfig b/arch/arm/configs/rk3066b_fpga_defconfig index d6e2dafed4f6..724c6563711f 100644 --- a/arch/arm/configs/rk3066b_fpga_defconfig +++ b/arch/arm/configs/rk3066b_fpga_defconfig @@ -23,7 +23,7 @@ CONFIG_MODULES=y CONFIG_MODULE_FORCE_LOAD=y CONFIG_MODULE_UNLOAD=y CONFIG_MODULE_FORCE_UNLOAD=y -CONFIG_ARCH_RK31=y +CONFIG_ARCH_RK3066B=y # CONFIG_DDR_TEST is not set # CONFIG_RK29_LAST_LOG is not set CONFIG_RK_DEBUG_UART=1 diff --git a/arch/arm/configs/rk3066b_sdk_defconfig b/arch/arm/configs/rk3066b_sdk_defconfig index ac9a01f128b7..5370231af3f3 100644 --- a/arch/arm/configs/rk3066b_sdk_defconfig +++ b/arch/arm/configs/rk3066b_sdk_defconfig @@ -10,9 +10,6 @@ CONFIG_RESOURCE_COUNTERS=y CONFIG_CGROUP_SCHED=y CONFIG_RT_GROUP_SCHED=y CONFIG_BLK_DEV_INITRD=y -CONFIG_INITRAMFS_SOURCE="root" -CONFIG_INITRAMFS_COMPRESSION_GZIP=y -CONFIG_CC_OPTIMIZE_FOR_SIZE=y CONFIG_PANIC_TIMEOUT=1 # CONFIG_SYSCTL_SYSCALL is not set # CONFIG_ELF_CORE is not set @@ -20,67 +17,273 @@ CONFIG_ASHMEM=y # CONFIG_AIO is not set CONFIG_EMBEDDED=y CONFIG_MODULES=y -CONFIG_MODULE_FORCE_LOAD=y CONFIG_MODULE_UNLOAD=y CONFIG_MODULE_FORCE_UNLOAD=y -CONFIG_ARCH_RK31=y +CONFIG_ARCH_RK30=y # CONFIG_DDR_TEST is not set -# CONFIG_RK29_LAST_LOG is not set -CONFIG_RK_DEBUG_UART=1 +CONFIG_ARCH_RK3066B=y CONFIG_MACH_RK3066B_SDK=y -# CONFIG_CACHE_L2X0 is not set CONFIG_FIQ_DEBUGGER=y CONFIG_FIQ_DEBUGGER_NO_SLEEP=y CONFIG_FIQ_DEBUGGER_CONSOLE=y CONFIG_FIQ_DEBUGGER_CONSOLE_DEFAULT_ENABLE=y CONFIG_NO_HZ=y CONFIG_HIGH_RES_TIMERS=y +CONFIG_SMP=y +# CONFIG_SMP_ON_UP is not set +CONFIG_NR_CPUS=2 CONFIG_PREEMPT=y CONFIG_AEABI=y # CONFIG_OABI_COMPAT is not set CONFIG_HIGHMEM=y CONFIG_COMPACTION=y CONFIG_DEFAULT_MMAP_MIN_ADDR=32768 -CONFIG_CMDLINE="console=ttyFIQ0 androidboot.console=ttyFIQ0 init=/init debug" +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CMDLINE="console=ttyFIQ0 androidboot.console=ttyFIQ0 init=/init" +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE=y +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y +CONFIG_CPU_IDLE=y CONFIG_VFP=y +CONFIG_NEON=y CONFIG_WAKELOCK=y CONFIG_PM_RUNTIME=y +CONFIG_PM_DEBUG=y CONFIG_SUSPEND_TIME=y CONFIG_NET=y +CONFIG_PACKET=y CONFIG_UNIX=y -# CONFIG_NET_ACTIVITY_STATS is not set -# CONFIG_WIRELESS is not set +CONFIG_XFRM_USER=y +CONFIG_NET_KEY=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_INET_ESP=y +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_LRO is not set +CONFIG_IPV6=y +CONFIG_IPV6_PRIVACY=y +CONFIG_IPV6_ROUTER_PREF=y +CONFIG_IPV6_OPTIMISTIC_DAD=y +CONFIG_INET6_AH=y +CONFIG_INET6_ESP=y +CONFIG_INET6_IPCOMP=y +CONFIG_IPV6_MIP6=y +CONFIG_IPV6_TUNNEL=y +CONFIG_IPV6_MULTIPLE_TABLES=y +CONFIG_NETFILTER=y +# CONFIG_BRIDGE_NETFILTER is not set +CONFIG_NF_CONNTRACK=y +CONFIG_NF_CONNTRACK_EVENTS=y +CONFIG_NF_CT_PROTO_DCCP=y +CONFIG_NF_CT_PROTO_SCTP=y +CONFIG_NF_CT_PROTO_UDPLITE=y +CONFIG_NF_CONNTRACK_AMANDA=y +CONFIG_NF_CONNTRACK_FTP=y +CONFIG_NF_CONNTRACK_H323=y +CONFIG_NF_CONNTRACK_IRC=y +CONFIG_NF_CONNTRACK_NETBIOS_NS=y +CONFIG_NF_CONNTRACK_PPTP=y +CONFIG_NF_CONNTRACK_SANE=y +CONFIG_NF_CONNTRACK_SIP=y +CONFIG_NF_CONNTRACK_TFTP=y +CONFIG_NF_CT_NETLINK=y +CONFIG_NETFILTER_TPROXY=y +CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y +CONFIG_NETFILTER_XT_TARGET_CONNMARK=y +CONFIG_NETFILTER_XT_TARGET_IDLETIMER=y +CONFIG_NETFILTER_XT_TARGET_MARK=y +CONFIG_NETFILTER_XT_TARGET_NFLOG=y +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y +CONFIG_NETFILTER_XT_TARGET_TPROXY=y +CONFIG_NETFILTER_XT_TARGET_TRACE=y +CONFIG_NETFILTER_XT_MATCH_COMMENT=y +CONFIG_NETFILTER_XT_MATCH_CONNBYTES=y +CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y +CONFIG_NETFILTER_XT_MATCH_CONNMARK=y +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y +CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y +CONFIG_NETFILTER_XT_MATCH_HELPER=y +CONFIG_NETFILTER_XT_MATCH_IPRANGE=y +CONFIG_NETFILTER_XT_MATCH_LENGTH=y +CONFIG_NETFILTER_XT_MATCH_LIMIT=y +CONFIG_NETFILTER_XT_MATCH_MAC=y +CONFIG_NETFILTER_XT_MATCH_MARK=y +CONFIG_NETFILTER_XT_MATCH_POLICY=y +CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y +CONFIG_NETFILTER_XT_MATCH_QTAGUID=y +CONFIG_NETFILTER_XT_MATCH_QUOTA=y +CONFIG_NETFILTER_XT_MATCH_QUOTA2=y +CONFIG_NETFILTER_XT_MATCH_QUOTA2_LOG=y +CONFIG_NETFILTER_XT_MATCH_SOCKET=y +CONFIG_NETFILTER_XT_MATCH_STATE=y +CONFIG_NETFILTER_XT_MATCH_STATISTIC=y +CONFIG_NETFILTER_XT_MATCH_STRING=y +CONFIG_NETFILTER_XT_MATCH_TIME=y +CONFIG_NETFILTER_XT_MATCH_U32=y +CONFIG_NF_CONNTRACK_IPV4=y +CONFIG_IP_NF_IPTABLES=y +CONFIG_IP_NF_MATCH_AH=y +CONFIG_IP_NF_MATCH_ECN=y +CONFIG_IP_NF_MATCH_TTL=y +CONFIG_IP_NF_FILTER=y +CONFIG_IP_NF_TARGET_REJECT=y +CONFIG_IP_NF_TARGET_REJECT_SKERR=y +CONFIG_IP_NF_TARGET_LOG=y +CONFIG_NF_NAT=y +CONFIG_IP_NF_TARGET_MASQUERADE=y +CONFIG_IP_NF_TARGET_NETMAP=y +CONFIG_IP_NF_TARGET_REDIRECT=y +CONFIG_IP_NF_MANGLE=y +CONFIG_IP_NF_RAW=y +CONFIG_IP_NF_ARPTABLES=y +CONFIG_IP_NF_ARPFILTER=y +CONFIG_IP_NF_ARP_MANGLE=y +CONFIG_NF_CONNTRACK_IPV6=y +CONFIG_IP6_NF_IPTABLES=y +CONFIG_IP6_NF_TARGET_LOG=y +CONFIG_IP6_NF_FILTER=y +CONFIG_IP6_NF_TARGET_REJECT=y +CONFIG_IP6_NF_TARGET_REJECT_SKERR=y +CONFIG_IP6_NF_MANGLE=y +CONFIG_IP6_NF_RAW=y +CONFIG_BRIDGE=y +# CONFIG_BRIDGE_IGMP_SNOOPING is not set +CONFIG_PHONET=y +CONFIG_NET_SCHED=y +CONFIG_NET_SCH_HTB=y +CONFIG_NET_SCH_INGRESS=y +CONFIG_NET_CLS_U32=y +CONFIG_NET_EMATCH=y +CONFIG_NET_EMATCH_U32=y +CONFIG_NET_CLS_ACT=y +CONFIG_NET_ACT_POLICE=y +CONFIG_NET_ACT_GACT=y +CONFIG_NET_ACT_MIRRED=y +CONFIG_BT=y +CONFIG_BT_L2CAP=y +CONFIG_BT_SCO=y +CONFIG_BT_RFCOMM=y +CONFIG_BT_RFCOMM_TTY=y +CONFIG_BT_BNEP=y +CONFIG_BT_HIDP=y +CONFIG_BT_HCIUART=y +CONFIG_BT_HCIUART_H4=y +CONFIG_BT_HCIUART_LL=y +CONFIG_BT_HCIBCM4325=y +CONFIG_BT_AUTOSLEEP=y +CONFIG_RFKILL=y +CONFIG_RFKILL_RK=y CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y # CONFIG_FIRMWARE_IN_KERNEL is not set CONFIG_MTD=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_NAND_IDS=y +CONFIG_MTD_RKNAND=y +CONFIG_BLK_DEV_LOOP=y CONFIG_MISC_DEVICES=y -# CONFIG_ANDROID_PMEM is not set -CONFIG_INPUT_POLLDEV=y +CONFIG_UID_STAT=y +CONFIG_APANIC=y +CONFIG_SCSI=y +CONFIG_BLK_DEV_SD=y +CONFIG_SCSI_MULTI_LUN=y +CONFIG_MD=y +CONFIG_BLK_DEV_DM=y +CONFIG_DM_CRYPT=y +CONFIG_DM_UEVENT=y +CONFIG_NETDEVICES=y +CONFIG_PHYLIB=y +# CONFIG_NETDEV_1000 is not set +# CONFIG_NETDEV_10000 is not set +CONFIG_WLAN_80211=y +CONFIG_RKWIFI=y +CONFIG_USB_USBNET=y +CONFIG_PPP=y +CONFIG_PPP_MULTILINK=y +CONFIG_PPP_FILTER=y +CONFIG_PPP_ASYNC=y +CONFIG_PPP_SYNC_TTY=y +CONFIG_PPP_DEFLATE=y +CONFIG_PPP_BSDCOMP=y +CONFIG_PPP_MPPE=y +CONFIG_PPPOLAC=y +CONFIG_PPPOPNS=y # CONFIG_INPUT_MOUSEDEV is not set CONFIG_INPUT_EVDEV=y +CONFIG_INPUT_KEYRESET=y # CONFIG_KEYBOARD_ATKBD is not set # CONFIG_INPUT_MOUSE is not set +CONFIG_INPUT_JOYSTICK=y +CONFIG_JOYSTICK_XPAD=y +CONFIG_JOYSTICK_XPAD_FF=y +CONFIG_JOYSTICK_XPAD_LEDS=y +CONFIG_INPUT_TABLET=y +CONFIG_TABLET_USB_ACECAD=y +CONFIG_TABLET_USB_AIPTEK=y +CONFIG_TABLET_USB_GTCO=y +CONFIG_TABLET_USB_HANWANG=y +CONFIG_TABLET_USB_KBTAB=y +CONFIG_TABLET_USB_WACOM=y +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_TOUCHSCREEN_GT8XX=y +CONFIG_INPUT_MISC=y +CONFIG_INPUT_KEYCHORD=y +CONFIG_INPUT_UINPUT=y +CONFIG_COMPASS_AK8975=y +CONFIG_GS_MMA8452=y +CONFIG_GS_LIS3DH=y +CONFIG_GYRO_L3G4200D=y +CONFIG_LS_CM3217=y +CONFIG_SENSOR_DEVICE=y +CONFIG_GSENSOR_DEVICE=y +CONFIG_GS_KXTIK=y +CONFIG_COMPASS_DEVICE=y +CONFIG_GYROSCOPE_DEVICE=y +CONFIG_LIGHT_DEVICE=y +CONFIG_LS_AL3006=y +CONFIG_LS_STK3171=y +CONFIG_PROXIMITY_DEVICE=y +CONFIG_PS_AL3006=y +CONFIG_PS_STK3171=y # CONFIG_SERIO is not set # CONFIG_CONSOLE_TRANSLATIONS is not set # CONFIG_LEGACY_PTYS is not set +CONFIG_SERIAL_RK29=y +CONFIG_UART0_RK29=y +CONFIG_UART0_CTS_RTS_RK29=y +CONFIG_UART3_RK29=y +CONFIG_UART3_CTS_RTS_RK29=y # CONFIG_HW_RANDOM is not set CONFIG_I2C=y +# CONFIG_I2C_COMPAT is not set CONFIG_I2C0_CONTROLLER_RK30=y CONFIG_I2C1_CONTROLLER_RK30=y CONFIG_I2C2_CONTROLLER_RK30=y -# CONFIG_I2C3_RK30 is not set -# CONFIG_ADC is not set +CONFIG_I2C3_CONTROLLER_RK30=y +CONFIG_I2C4_CONTROLLER_RK30=y +CONFIG_GPIO_SYSFS=y CONFIG_EXPANDED_GPIO_NUM=0 CONFIG_EXPANDED_GPIO_IRQ_NUM=0 CONFIG_SPI_FPGA_GPIO_NUM=0 CONFIG_SPI_FPGA_GPIO_IRQ_NUM=0 +CONFIG_POWER_SUPPLY=y +CONFIG_TEST_POWER=y # CONFIG_HWMON is not set -# CONFIG_MFD_SUPPORT is not set +CONFIG_REGULATOR=y CONFIG_MEDIA_SUPPORT=y CONFIG_VIDEO_DEV=y CONFIG_SOC_CAMERA=y CONFIG_SOC_CAMERA_OV2659=y +CONFIG_SOC_CAMERA_OV5642=y CONFIG_VIDEO_RK29=y CONFIG_VIDEO_RK29_CAMMEM_ION=y CONFIG_ION=y @@ -91,11 +294,10 @@ CONFIG_BACKLIGHT_LCD_SUPPORT=y CONFIG_BACKLIGHT_CLASS_DEVICE=y # CONFIG_BACKLIGHT_GENERIC is not set CONFIG_DISPLAY_SUPPORT=y -CONFIG_LCD_TD043MGEA1=y +CONFIG_LCD_B101EW05=y CONFIG_FB_ROCKCHIP=y CONFIG_LCDC_RK31=y CONFIG_LCDC1_RK31=y -# CONFIG_THREE_FB_BUFFER is not set CONFIG_RGA_RK30=y CONFIG_LOGO=y # CONFIG_LOGO_LINUX_MONO is not set @@ -110,34 +312,116 @@ CONFIG_SND_SOC=y CONFIG_SND_RK29_SOC=y CONFIG_SND_RK29_SOC_I2S_2CH=y CONFIG_SND_I2S_DMA_EVENT_STATIC=y -CONFIG_SND_RK29_SOC_RK1000=y +CONFIG_SND_RK29_SOC_RT5631=y CONFIG_SND_RK29_CODEC_SOC_SLAVE=y -# CONFIG_HID_SUPPORT is not set -# CONFIG_USB_SUPPORT is not set +CONFIG_HID_A4TECH=y +CONFIG_HID_ACRUX=y +CONFIG_HID_ACRUX_FF=y +CONFIG_HID_APPLE=y +CONFIG_HID_BELKIN=y +CONFIG_HID_CHERRY=y +CONFIG_HID_CHICONY=y +CONFIG_HID_CYPRESS=y +CONFIG_HID_DRAGONRISE=y +CONFIG_DRAGONRISE_FF=y +CONFIG_HID_EMS_FF=y +CONFIG_HID_ELECOM=y +CONFIG_HID_EZKEY=y +CONFIG_HID_KEYTOUCH=y +CONFIG_HID_KYE=y +CONFIG_HID_UCLOGIC=y +CONFIG_HID_WALTOP=y +CONFIG_HID_GYRATION=y +CONFIG_HID_TWINHAN=y +CONFIG_HID_KENSINGTON=y +CONFIG_HID_LCPOWER=y +CONFIG_HID_LOGITECH=y +CONFIG_LOGITECH_FF=y +CONFIG_LOGIRUMBLEPAD2_FF=y +CONFIG_LOGIG940_FF=y +CONFIG_LOGIWII_FF=y +CONFIG_HID_MAGICMOUSE=y +CONFIG_HID_MICROSOFT=y +CONFIG_HID_MONTEREY=y +CONFIG_HID_MULTITOUCH=y +CONFIG_HID_NTRIG=y +CONFIG_HID_ORTEK=y +CONFIG_HID_PANTHERLORD=y +CONFIG_PANTHERLORD_FF=y +CONFIG_HID_PETALYNX=y +CONFIG_HID_PICOLCD=y +CONFIG_HID_QUANTA=y +CONFIG_HID_ROCCAT_ARVO=y +CONFIG_HID_ROCCAT_KONE=y +CONFIG_HID_ROCCAT_KONEPLUS=y +CONFIG_HID_ROCCAT_KOVAPLUS=y +CONFIG_HID_ROCCAT_PYRA=y +CONFIG_HID_SAMSUNG=y +CONFIG_HID_SONY=y +CONFIG_HID_SUNPLUS=y +CONFIG_HID_GREENASIA=y +CONFIG_GREENASIA_FF=y +CONFIG_HID_SMARTJOYPLUS=y +CONFIG_SMARTJOYPLUS_FF=y +CONFIG_HID_TOPSEED=y +CONFIG_HID_THRUSTMASTER=y +CONFIG_THRUSTMASTER_FF=y +CONFIG_HID_WACOM=y +CONFIG_HID_ZEROPLUS=y +CONFIG_ZEROPLUS_FF=y +CONFIG_HID_ZYDACRON=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y +CONFIG_USB_DEVICEFS=y +CONFIG_USB_OTG_BLACKLIST_HUB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_SERIAL=y +CONFIG_USB_SERIAL_GENERIC=y +CONFIG_USB_SERIAL_OPTION=y +CONFIG_USB_GADGET=y +CONFIG_USB20_HOST=y +CONFIG_USB20_OTG=y CONFIG_MMC=y CONFIG_MMC_UNSAFE_RESUME=y +CONFIG_MMC_EMBEDDED_SDIO=y CONFIG_MMC_PARANOID_SD_INIT=y CONFIG_SDMMC_RK29=y -# CONFIG_SDMMC1_RK29 is not set +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y +CONFIG_LEDS_GPIO=y +CONFIG_SWITCH=y +CONFIG_SWITCH_GPIO=y CONFIG_RTC_CLASS=y +CONFIG_STAGING=y +CONFIG_ANDROID=y +CONFIG_ANDROID_BINDER_IPC=y +CONFIG_ANDROID_LOGGER=y +CONFIG_ANDROID_TIMED_GPIO=y +CONFIG_ANDROID_LOW_MEMORY_KILLER=y # CONFIG_CMMB is not set +CONFIG_EXT3_FS=y +# CONFIG_EXT3_FS_XATTR is not set +CONFIG_EXT4_FS=y +# CONFIG_EXT4_FS_XATTR is not set # CONFIG_DNOTIFY is not set -CONFIG_MSDOS_FS=y +CONFIG_FUSE_FS=y CONFIG_VFAT_FS=y CONFIG_TMPFS=y # CONFIG_MISC_FILESYSTEMS is not set # CONFIG_NETWORK_FILESYSTEMS is not set CONFIG_PARTITION_ADVANCED=y +CONFIG_EFI_PARTITION=y CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_ASCII=y CONFIG_NLS_ISO8859_1=y CONFIG_PRINTK_TIME=y CONFIG_MAGIC_SYSRQ=y -CONFIG_DEBUG_FS=y CONFIG_DEBUG_KERNEL=y -CONFIG_DETECT_HUNG_TASK=y # CONFIG_SCHED_DEBUG is not set CONFIG_SCHEDSTATS=y -CONFIG_TIMER_STATS=y CONFIG_SLUB_DEBUG_ON=y # CONFIG_DEBUG_PREEMPT is not set -# CONFIG_FTRACE is not set +# CONFIG_EVENT_POWER_TRACING_DEPRECATED is not set +CONFIG_ENABLE_DEFAULT_TRACERS=y +CONFIG_CRYPTO_SHA256=y +CONFIG_CRYPTO_TWOFISH=y +# CONFIG_CRYPTO_ANSI_CPRNG is not set diff --git a/arch/arm/mach-rk30/Kconfig b/arch/arm/mach-rk30/Kconfig index 6dce5758efdb..8157d9844aff 100755 --- a/arch/arm/mach-rk30/Kconfig +++ b/arch/arm/mach-rk30/Kconfig @@ -1,4 +1,10 @@ -if ARCH_RK30 +config ARCH_RK3066B + bool "Rockchip RK3066B" + depends on ARCH_RK30 + help + Support for Rockchip's RK3066B SoCs. + +if ARCH_RK30 && !ARCH_RK3066B choice prompt "RK30xx Board Type" @@ -29,16 +35,17 @@ endchoice endif -if ARCH_RK31 +if ARCH_RK3066B choice - prompt "RK31xx Board Type" + prompt "RK3066B Board Type" -config MACH_RK31_FPGA - bool "RK31 FPGA board" +config MACH_RK3066B_FPGA + bool "RK3066B FPGA board" + select RK_FPGA config MACH_RK3066B_SDK - bool "RK3066B(RK31) SDK board" + bool "RK3066B SDK board" endchoice diff --git a/arch/arm/mach-rk30/Makefile b/arch/arm/mach-rk30/Makefile index f19d13d0f7a5..0e2ff30463b8 100644 --- a/arch/arm/mach-rk30/Makefile +++ b/arch/arm/mach-rk30/Makefile @@ -1,4 +1,4 @@ -ifneq ($(CONFIG_MACH_RK31_FPGA),y) +ifneq ($(CONFIG_RK_FPGA),y) obj-y += clock.o obj-y += clock_data.o endif @@ -31,5 +31,5 @@ obj-$(CONFIG_MACH_RK30_PHONE_LOQUAT) += board-rk30-phone-loquat.o board-rk30-pho obj-$(CONFIG_MACH_RK30_DS1001B) += board-rk30-ds1001b.o board-rk30-ds1001b-key.o board-rk30-ds1001b-rfkill.o obj-$(CONFIG_MACH_RK30_PHONE_A22) += board-rk30-phone-a22.o board-rk30-phone-a22-key.o -obj-$(CONFIG_MACH_RK31_FPGA) += board-rk31-fpga.o -obj-$(CONFIG_MACH_RK3066B_SDK) += board-rk3066b-sdk.o board-rk3066b-sdk-key.o +obj-$(CONFIG_MACH_RK3066B_FPGA) += board-rk3066b-fpga.o +obj-$(CONFIG_MACH_RK3066B_SDK) += board-rk3066b-sdk.o diff --git a/arch/arm/mach-rk30/board-rk3066b-sdk-camera.c b/arch/arm/mach-rk30/board-rk3066b-sdk-camera.c new file mode 100644 index 000000000000..a63577bd23f6 --- /dev/null +++ b/arch/arm/mach-rk30/board-rk3066b-sdk-camera.c @@ -0,0 +1,443 @@ +#ifdef CONFIG_VIDEO_RK29 +/*---------------- Camera Sensor Macro Define Begin ------------------------*/ +/*---------------- Camera Sensor Configuration Macro Begin ------------------------*/ +#define CONFIG_SENSOR_0 RK29_CAM_SENSOR_OV5642 /* back camera sensor */ +#define CONFIG_SENSOR_IIC_ADDR_0 0 +#define CONFIG_SENSOR_IIC_ADAPTER_ID_0 4 +#define CONFIG_SENSOR_ORIENTATION_0 90 +#define CONFIG_SENSOR_POWER_PIN_0 INVALID_GPIO +#define CONFIG_SENSOR_RESET_PIN_0 INVALID_GPIO +#define CONFIG_SENSOR_POWERDN_PIN_0 RK30_PIN1_PD6 +#define CONFIG_SENSOR_FALSH_PIN_0 INVALID_GPIO +#define CONFIG_SENSOR_POWERACTIVE_LEVEL_0 RK29_CAM_POWERACTIVE_L +#define CONFIG_SENSOR_RESETACTIVE_LEVEL_0 RK29_CAM_RESETACTIVE_L +#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_0 RK29_CAM_POWERDNACTIVE_H +#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_0 RK29_CAM_FLASHACTIVE_L + +#define CONFIG_SENSOR_QCIF_FPS_FIXED_0 15000 +#define CONFIG_SENSOR_240X160_FPS_FIXED_0 15000 +#define CONFIG_SENSOR_QVGA_FPS_FIXED_0 15000 +#define CONFIG_SENSOR_CIF_FPS_FIXED_0 15000 +#define CONFIG_SENSOR_VGA_FPS_FIXED_0 15000 +#define CONFIG_SENSOR_480P_FPS_FIXED_0 15000 +#define CONFIG_SENSOR_SVGA_FPS_FIXED_0 15000 +#define CONFIG_SENSOR_720P_FPS_FIXED_0 30000 + +#define CONFIG_SENSOR_01 RK29_CAM_SENSOR_OV5642 /* back camera sensor 1 */ +#define CONFIG_SENSOR_IIC_ADDR_01 0x00 +#define CONFIG_SENSOR_IIC_ADAPTER_ID_01 4 +#define CONFIG_SENSOR_ORIENTATION_01 90 +#define CONFIG_SENSOR_POWER_PIN_01 INVALID_GPIO +#define CONFIG_SENSOR_RESET_PIN_01 INVALID_GPIO +#define CONFIG_SENSOR_POWERDN_PIN_01 RK30_PIN1_PD6 +#define CONFIG_SENSOR_FALSH_PIN_01 INVALID_GPIO +#define CONFIG_SENSOR_POWERACTIVE_LEVEL_01 RK29_CAM_POWERACTIVE_L +#define CONFIG_SENSOR_RESETACTIVE_LEVEL_01 RK29_CAM_RESETACTIVE_L +#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_01 RK29_CAM_POWERDNACTIVE_H +#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_01 RK29_CAM_FLASHACTIVE_L + +#define CONFIG_SENSOR_QCIF_FPS_FIXED_01 15000 +#define CONFIG_SENSOR_240X160_FPS_FIXED_01 15000 +#define CONFIG_SENSOR_QVGA_FPS_FIXED_01 15000 +#define CONFIG_SENSOR_CIF_FPS_FIXED_01 15000 +#define CONFIG_SENSOR_VGA_FPS_FIXED_01 15000 +#define CONFIG_SENSOR_480P_FPS_FIXED_01 15000 +#define CONFIG_SENSOR_SVGA_FPS_FIXED_01 15000 +#define CONFIG_SENSOR_720P_FPS_FIXED_01 30000 + +#define CONFIG_SENSOR_02 RK29_CAM_SENSOR_OV5640 /* back camera sensor 2 */ +#define CONFIG_SENSOR_IIC_ADDR_02 0x00 +#define CONFIG_SENSOR_CIF_INDEX_02 0 +#define CONFIG_SENSOR_IIC_ADAPTER_ID_02 4 +#define CONFIG_SENSOR_ORIENTATION_02 90 +#define CONFIG_SENSOR_POWER_PIN_02 INVALID_GPIO +#define CONFIG_SENSOR_RESET_PIN_02 INVALID_GPIO +#define CONFIG_SENSOR_POWERDN_PIN_02 INVALID_GPIO +#define CONFIG_SENSOR_FALSH_PIN_02 INVALID_GPIO +#define CONFIG_SENSOR_POWERACTIVE_LEVEL_02 RK29_CAM_POWERACTIVE_L +#define CONFIG_SENSOR_RESETACTIVE_LEVEL_02 RK29_CAM_RESETACTIVE_L +#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_02 RK29_CAM_POWERDNACTIVE_H +#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_02 RK29_CAM_FLASHACTIVE_L + +#define CONFIG_SENSOR_QCIF_FPS_FIXED_02 15000 +#define CONFIG_SENSOR_240X160_FPS_FIXED_02 15000 +#define CONFIG_SENSOR_QVGA_FPS_FIXED_02 15000 +#define CONFIG_SENSOR_CIF_FPS_FIXED_02 15000 +#define CONFIG_SENSOR_VGA_FPS_FIXED_02 15000 +#define CONFIG_SENSOR_480P_FPS_FIXED_02 15000 +#define CONFIG_SENSOR_SVGA_FPS_FIXED_02 15000 +#define CONFIG_SENSOR_720P_FPS_FIXED_02 30000 + +#define CONFIG_SENSOR_1 RK29_CAM_SENSOR_OV2659 /* front camera sensor 0 */ +#define CONFIG_SENSOR_IIC_ADDR_1 0x60 +#define CONFIG_SENSOR_IIC_ADAPTER_ID_1 3 +#define CONFIG_SENSOR_ORIENTATION_1 270 +#define CONFIG_SENSOR_POWER_PIN_1 INVALID_GPIO +#define CONFIG_SENSOR_RESET_PIN_1 INVALID_GPIO +#define CONFIG_SENSOR_POWERDN_PIN_1 RK30_PIN2_PC7 +#define CONFIG_SENSOR_FALSH_PIN_1 INVALID_GPIO +#define CONFIG_SENSOR_POWERACTIVE_LEVEL_1 RK29_CAM_POWERACTIVE_L +#define CONFIG_SENSOR_RESETACTIVE_LEVEL_1 RK29_CAM_RESETACTIVE_L +#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_1 RK29_CAM_POWERDNACTIVE_H +#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_1 RK29_CAM_FLASHACTIVE_L + +#define CONFIG_SENSOR_QCIF_FPS_FIXED_1 15000 +#define CONFIG_SENSOR_240X160_FPS_FIXED_1 15000 +#define CONFIG_SENSOR_QVGA_FPS_FIXED_1 15000 +#define CONFIG_SENSOR_CIF_FPS_FIXED_1 15000 +#define CONFIG_SENSOR_VGA_FPS_FIXED_1 15000 +#define CONFIG_SENSOR_480P_FPS_FIXED_1 15000 +#define CONFIG_SENSOR_SVGA_FPS_FIXED_1 15000 +#define CONFIG_SENSOR_720P_FPS_FIXED_1 30000 + +#define CONFIG_SENSOR_11 RK29_CAM_SENSOR_OV2659 /* front camera sensor 1 */ +#define CONFIG_SENSOR_IIC_ADDR_11 0x00 +#define CONFIG_SENSOR_IIC_ADAPTER_ID_11 3 +#define CONFIG_SENSOR_ORIENTATION_11 270 +#define CONFIG_SENSOR_POWER_PIN_11 INVALID_GPIO +#define CONFIG_SENSOR_RESET_PIN_11 INVALID_GPIO +#define CONFIG_SENSOR_POWERDN_PIN_11 INVALID_GPIO//RK30_PIN1_PB7 +#define CONFIG_SENSOR_FALSH_PIN_11 INVALID_GPIO +#define CONFIG_SENSOR_POWERACTIVE_LEVEL_11 RK29_CAM_POWERACTIVE_L +#define CONFIG_SENSOR_RESETACTIVE_LEVEL_11 RK29_CAM_RESETACTIVE_L +#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_11 RK29_CAM_POWERDNACTIVE_H +#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_11 RK29_CAM_FLASHACTIVE_L + +#define CONFIG_SENSOR_QCIF_FPS_FIXED_11 15000 +#define CONFIG_SENSOR_240X160_FPS_FIXED_11 15000 +#define CONFIG_SENSOR_QVGA_FPS_FIXED_11 15000 +#define CONFIG_SENSOR_CIF_FPS_FIXED_11 15000 +#define CONFIG_SENSOR_VGA_FPS_FIXED_11 15000 +#define CONFIG_SENSOR_480P_FPS_FIXED_11 15000 +#define CONFIG_SENSOR_SVGA_FPS_FIXED_11 15000 +#define CONFIG_SENSOR_720P_FPS_FIXED_11 30000 + +#define CONFIG_SENSOR_12 RK29_CAM_SENSOR_OV2659//RK29_CAM_SENSOR_OV2655 /* front camera sensor 2 */ +#define CONFIG_SENSOR_IIC_ADDR_12 0x00 +#define CONFIG_SENSOR_IIC_ADAPTER_ID_12 3 +#define CONFIG_SENSOR_ORIENTATION_12 270 +#define CONFIG_SENSOR_POWER_PIN_12 INVALID_GPIO +#define CONFIG_SENSOR_RESET_PIN_12 INVALID_GPIO +#define CONFIG_SENSOR_POWERDN_PIN_12 INVALID_GPIO//RK30_PIN1_PB7 +#define CONFIG_SENSOR_FALSH_PIN_12 INVALID_GPIO +#define CONFIG_SENSOR_POWERACTIVE_LEVEL_12 RK29_CAM_POWERACTIVE_L +#define CONFIG_SENSOR_RESETACTIVE_LEVEL_12 RK29_CAM_RESETACTIVE_L +#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_12 RK29_CAM_POWERDNACTIVE_H +#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_12 RK29_CAM_FLASHACTIVE_L + +#define CONFIG_SENSOR_QCIF_FPS_FIXED_12 15000 +#define CONFIG_SENSOR_240X160_FPS_FIXED_12 15000 +#define CONFIG_SENSOR_QVGA_FPS_FIXED_12 15000 +#define CONFIG_SENSOR_CIF_FPS_FIXED_12 15000 +#define CONFIG_SENSOR_VGA_FPS_FIXED_12 15000 +#define CONFIG_SENSOR_480P_FPS_FIXED_12 15000 +#define CONFIG_SENSOR_SVGA_FPS_FIXED_12 15000 +#define CONFIG_SENSOR_720P_FPS_FIXED_12 30000 + + +#endif //#ifdef CONFIG_VIDEO_RK29 +/*---------------- Camera Sensor Configuration Macro End------------------------*/ +#include "../../../drivers/media/video/rk30_camera.c" +/*---------------- Camera Sensor Macro Define End ---------*/ + +#define PMEM_CAM_SIZE PMEM_CAM_NECESSARY +/***************************************************************************************** + * camera devices + * author: ddl@rock-chips.com + *****************************************************************************************/ +#ifdef CONFIG_VIDEO_RK29 +#define CONFIG_SENSOR_POWER_IOCTL_USR 1 //define this refer to your board layout +#define CONFIG_SENSOR_RESET_IOCTL_USR 0 +#define CONFIG_SENSOR_POWERDOWN_IOCTL_USR 0 +#define CONFIG_SENSOR_FLASH_IOCTL_USR 0 + +static void rk_cif_power(int on) +{ + struct regulator *ldo_18,*ldo_28; + ldo_28 = regulator_get(NULL, "ldo7"); // vcc28_cif + ldo_18 = regulator_get(NULL, "ldo1"); // vcc18_cif + if (ldo_28 == NULL || IS_ERR(ldo_28) || ldo_18 == NULL || IS_ERR(ldo_18)){ + printk("get cif ldo failed!\n"); + return; + } + if(on == 0){ + regulator_disable(ldo_28); + regulator_put(ldo_28); + regulator_disable(ldo_18); + regulator_put(ldo_18); + mdelay(500); + } + else{ + regulator_set_voltage(ldo_28, 2800000, 2800000); + regulator_enable(ldo_28); + // printk("%s set ldo7 vcc28_cif=%dmV end\n", __func__, regulator_get_voltage(ldo_28)); + regulator_put(ldo_28); + + regulator_set_voltage(ldo_18, 1800000, 1800000); + // regulator_set_suspend_voltage(ldo, 1800000); + regulator_enable(ldo_18); + // printk("%s set ldo1 vcc18_cif=%dmV end\n", __func__, regulator_get_voltage(ldo_18)); + regulator_put(ldo_18); + } +} + +#if CONFIG_SENSOR_POWER_IOCTL_USR +static int sensor_power_usr_cb (struct rk29camera_gpio_res *res,int on) +{ + //#error "CONFIG_SENSOR_POWER_IOCTL_USR is 1, sensor_power_usr_cb function must be writed!!"; + rk_cif_power(on); +} +#endif + +#if CONFIG_SENSOR_RESET_IOCTL_USR +static int sensor_reset_usr_cb (struct rk29camera_gpio_res *res,int on) +{ + #error "CONFIG_SENSOR_RESET_IOCTL_USR is 1, sensor_reset_usr_cb function must be writed!!"; +} +#endif + +#if CONFIG_SENSOR_POWERDOWN_IOCTL_USR +static int sensor_powerdown_usr_cb (struct rk29camera_gpio_res *res,int on) +{ + #error "CONFIG_SENSOR_POWERDOWN_IOCTL_USR is 1, sensor_powerdown_usr_cb function must be writed!!"; +} +#endif + +#if CONFIG_SENSOR_FLASH_IOCTL_USR +static int sensor_flash_usr_cb (struct rk29camera_gpio_res *res,int on) +{ + #error "CONFIG_SENSOR_FLASH_IOCTL_USR is 1, sensor_flash_usr_cb function must be writed!!"; +} +#endif + +static struct rk29camera_platform_ioctl_cb sensor_ioctl_cb = { + #if CONFIG_SENSOR_POWER_IOCTL_USR + .sensor_power_cb = sensor_power_usr_cb, + #else + .sensor_power_cb = NULL, + #endif + + #if CONFIG_SENSOR_RESET_IOCTL_USR + .sensor_reset_cb = sensor_reset_usr_cb, + #else + .sensor_reset_cb = NULL, + #endif + + #if CONFIG_SENSOR_POWERDOWN_IOCTL_USR + .sensor_powerdown_cb = sensor_powerdown_usr_cb, + #else + .sensor_powerdown_cb = NULL, + #endif + + #if CONFIG_SENSOR_FLASH_IOCTL_USR + .sensor_flash_cb = sensor_flash_usr_cb, + #else + .sensor_flash_cb = NULL, + #endif +}; + +#if CONFIG_SENSOR_IIC_ADDR_0 +static struct reginfo_t rk_init_data_sensor_reg_0[] = +{ + {0x0000, 0x00,0,0} + }; +static struct reginfo_t rk_init_data_sensor_winseqreg_0[] ={ + {0x0000, 0x00,0,0} + }; +#endif + +#if CONFIG_SENSOR_IIC_ADDR_1 +static struct reginfo_t rk_init_data_sensor_reg_1[] = +{ + {0x0000, 0x00,0,0} +}; +static struct reginfo_t rk_init_data_sensor_winseqreg_1[] = +{ + {0x0000, 0x00,0,0} +}; +#endif +#if CONFIG_SENSOR_IIC_ADDR_01 +static struct reginfo_t rk_init_data_sensor_reg_01[] = +{ + {0x0000, 0x00,0,0} +}; +static struct reginfo_t rk_init_data_sensor_winseqreg_01[] = +{ + {0x0000, 0x00,0,0} +}; +#endif +#if CONFIG_SENSOR_IIC_ADDR_02 +static struct reginfo_t rk_init_data_sensor_reg_02[] = +{ + {0x0000, 0x00,0,0} +}; +static struct reginfo_t rk_init_data_sensor_winseqreg_02[] = +{ + {0x0000, 0x00,0,0} +}; +#endif +#if CONFIG_SENSOR_IIC_ADDR_11 +static struct reginfo_t rk_init_data_sensor_reg_11[] = +{ + {0x0000, 0x00,0,0} +}; +static struct reginfo_t rk_init_data_sensor_winseqreg_11[] = +{ + {0x0000, 0x00,0,0} +}; +#endif +#if CONFIG_SENSOR_IIC_ADDR_12 +static struct reginfo_t rk_init_data_sensor_reg_12[] = +{ + {0x0000, 0x00,0,0} +}; +static struct reginfo_t rk_init_data_sensor_winseqreg_12[] = +{ + {0x0000, 0x00,0,0} +}; +#endif +static rk_sensor_user_init_data_s rk_init_data_sensor[RK_CAM_NUM] = +{ + #if CONFIG_SENSOR_IIC_ADDR_0 + { + .rk_sensor_init_width = INVALID_VALUE, + .rk_sensor_init_height = INVALID_VALUE, + .rk_sensor_init_bus_param = INVALID_VALUE, + .rk_sensor_init_pixelcode = INVALID_VALUE, + .rk_sensor_init_data = rk_init_data_sensor_reg_0, + .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_0, + .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_0) / sizeof(struct reginfo_t), + .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_0) / sizeof(struct reginfo_t), + }, + #else + { + .rk_sensor_init_width = INVALID_VALUE, + .rk_sensor_init_height = INVALID_VALUE, + .rk_sensor_init_bus_param = INVALID_VALUE, + .rk_sensor_init_pixelcode = INVALID_VALUE, + .rk_sensor_init_data = NULL, + .rk_sensor_init_winseq = NULL, + .rk_sensor_winseq_size = 0, + .rk_sensor_init_data_size = 0, + }, + #endif + #if CONFIG_SENSOR_IIC_ADDR_1 + { + .rk_sensor_init_width = INVALID_VALUE, + .rk_sensor_init_height = INVALID_VALUE, + .rk_sensor_init_bus_param = INVALID_VALUE, + .rk_sensor_init_pixelcode = INVALID_VALUE, + .rk_sensor_init_data = rk_init_data_sensor_reg_1, + .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_1, + .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_1) / sizeof(struct reginfo_t), + .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_1) / sizeof(struct reginfo_t), + }, + #else + { + .rk_sensor_init_width = INVALID_VALUE, + .rk_sensor_init_height = INVALID_VALUE, + .rk_sensor_init_bus_param = INVALID_VALUE, + .rk_sensor_init_pixelcode = INVALID_VALUE, + .rk_sensor_init_data = NULL, + .rk_sensor_init_winseq = NULL, + .rk_sensor_winseq_size = 0, + .rk_sensor_init_data_size = 0, + }, + #endif + #if CONFIG_SENSOR_IIC_ADDR_01 + { + .rk_sensor_init_width = INVALID_VALUE, + .rk_sensor_init_height = INVALID_VALUE, + .rk_sensor_init_bus_param = INVALID_VALUE, + .rk_sensor_init_pixelcode = INVALID_VALUE, + .rk_sensor_init_data = rk_init_data_sensor_reg_01, + .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_01, + .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_01) / sizeof(struct reginfo_t), + .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_01) / sizeof(struct reginfo_t), + }, + #else + { + .rk_sensor_init_width = INVALID_VALUE, + .rk_sensor_init_height = INVALID_VALUE, + .rk_sensor_init_bus_param = INVALID_VALUE, + .rk_sensor_init_pixelcode = INVALID_VALUE, + .rk_sensor_init_data = NULL, + .rk_sensor_init_winseq = NULL, + .rk_sensor_winseq_size = 0, + .rk_sensor_init_data_size = 0, + }, + #endif + #if CONFIG_SENSOR_IIC_ADDR_02 + { + .rk_sensor_init_width = INVALID_VALUE, + .rk_sensor_init_height = INVALID_VALUE, + .rk_sensor_init_bus_param = INVALID_VALUE, + .rk_sensor_init_pixelcode = INVALID_VALUE, + .rk_sensor_init_data = rk_init_data_sensor_reg_02, + .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_02, + .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_02) / sizeof(struct reginfo_t), + .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_02) / sizeof(struct reginfo_t), + }, + #else + { + .rk_sensor_init_width = INVALID_VALUE, + .rk_sensor_init_height = INVALID_VALUE, + .rk_sensor_init_bus_param = INVALID_VALUE, + .rk_sensor_init_pixelcode = INVALID_VALUE, + .rk_sensor_init_data = NULL, + .rk_sensor_init_winseq = NULL, + .rk_sensor_winseq_size = 0, + .rk_sensor_init_data_size = 0, + }, + #endif + #if CONFIG_SENSOR_IIC_ADDR_11 + { + .rk_sensor_init_width = INVALID_VALUE, + .rk_sensor_init_height = INVALID_VALUE, + .rk_sensor_init_bus_param = INVALID_VALUE, + .rk_sensor_init_pixelcode = INVALID_VALUE, + .rk_sensor_init_data = rk_init_data_sensor_reg_11, + .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_11, + .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_11) / sizeof(struct reginfo_t), + .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_11) / sizeof(struct reginfo_t), + }, + #else + { + .rk_sensor_init_width = INVALID_VALUE, + .rk_sensor_init_height = INVALID_VALUE, + .rk_sensor_init_bus_param = INVALID_VALUE, + .rk_sensor_init_pixelcode = INVALID_VALUE, + .rk_sensor_init_data = NULL, + .rk_sensor_init_winseq = NULL, + .rk_sensor_winseq_size = 0, + .rk_sensor_init_data_size = 0, + }, + #endif + #if CONFIG_SENSOR_IIC_ADDR_12 + { + .rk_sensor_init_width = INVALID_VALUE, + .rk_sensor_init_height = INVALID_VALUE, + .rk_sensor_init_bus_param = INVALID_VALUE, + .rk_sensor_init_pixelcode = INVALID_VALUE, + .rk_sensor_init_data = rk_init_data_sensor_reg_12, + .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_12, + .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_12) / sizeof(struct reginfo_t), + .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_12) / sizeof(struct reginfo_t), + }, + #else + { + .rk_sensor_init_width = INVALID_VALUE, + .rk_sensor_init_height = INVALID_VALUE, + .rk_sensor_init_bus_param = INVALID_VALUE, + .rk_sensor_init_pixelcode = INVALID_VALUE, + .rk_sensor_init_data = NULL, + .rk_sensor_init_winseq = NULL, + .rk_sensor_winseq_size = 0, + .rk_sensor_init_data_size = 0, + }, + #endif + + }; +#include "../../../drivers/media/video/rk30_camera.c" + +#endif /* CONFIG_VIDEO_RK29 */ diff --git a/arch/arm/mach-rk30/board-rk3066b-sdk-sdmmc.c b/arch/arm/mach-rk30/board-rk3066b-sdk-sdmmc.c index d444e52d411b..56455828db8a 100644 --- a/arch/arm/mach-rk30/board-rk3066b-sdk-sdmmc.c +++ b/arch/arm/mach-rk30/board-rk3066b-sdk-sdmmc.c @@ -1,4 +1,4 @@ -/* arch/arm/mach-rk30/board-rk30-sdk-sdmmc.c +/* * * Copyright (C) 2012 ROCKCHIP, Inc. * @@ -25,50 +25,16 @@ static void rk29_sdmmc_gpio_open(int device_id, int on) #ifdef CONFIG_SDMMC0_RK29 if(on) { - #if defined(CONFIG_ARCH_RK30) - gpio_direction_output(GPIO3B_GPIO3B0,GPIO_HIGH);//set mmc0-clk to high - gpio_direction_output(GPIO3B_GPIO3B1,GPIO_HIGH);// set mmc0-cmd to high. - gpio_direction_output(GPIO3B_GPIO3B2,GPIO_HIGH);//set mmc0-data0 to high. - gpio_direction_output(GPIO3B_GPIO3B3,GPIO_HIGH);//set mmc0-data1 to high. - gpio_direction_output(GPIO3B_GPIO3B4,GPIO_HIGH);//set mmc0-data2 to high. - gpio_direction_output(GPIO3B_GPIO3B5,GPIO_HIGH);//set mmc0-data3 to high. - #elif defined(CONFIG_ARCH_RK31) gpio_direction_output(RK30_PIN3_PA2,GPIO_HIGH);//set mmc0-clk to high gpio_direction_output(RK30_PIN3_PA3,GPIO_HIGH);// set mmc0-cmd to high. gpio_direction_output(RK30_PIN3_PA4,GPIO_HIGH);//set mmc0-data0 to high. gpio_direction_output(RK30_PIN3_PA5,GPIO_HIGH);//set mmc0-data1 to high. gpio_direction_output(RK30_PIN3_PA6,GPIO_HIGH);//set mmc0-data2 to high. gpio_direction_output(RK30_PIN3_PA7,GPIO_HIGH);//set mmc0-data3 to high. - #endif mdelay(30); } else { - #if defined(CONFIG_ARCH_RK30) - rk30_mux_api_set(GPIO3B0_SDMMC0CLKOUT_NAME, GPIO3B_GPIO3B0); - gpio_request(RK30_PIN3_PB0, "mmc0-clk"); - gpio_direction_output(RK30_PIN3_PB0,GPIO_LOW);//set mmc0-clk to low. - - rk30_mux_api_set(GPIO3B1_SDMMC0CMD_NAME, GPIO3B_GPIO3B1); - gpio_request(RK30_PIN3_PB1, "mmc0-cmd"); - gpio_direction_output(RK30_PIN3_PB1,GPIO_LOW);//set mmc0-cmd to low. - - rk30_mux_api_set(GPIO3B2_SDMMC0DATA0_NAME, GPIO3B_GPIO3B2); - gpio_request(RK30_PIN3_PB2, "mmc0-data0"); - gpio_direction_output(RK30_PIN3_PB2,GPIO_LOW);//set mmc0-data0 to low. - - rk30_mux_api_set(GPIO3B3_SDMMC0DATA1_NAME, GPIO3B_GPIO3B3); - gpio_request(RK30_PIN3_PB3, "mmc0-data1"); - gpio_direction_output(RK30_PIN3_PB3,GPIO_LOW);//set mmc0-data1 to low. - - rk30_mux_api_set(GPIO3B4_SDMMC0DATA2_NAME, GPIO3B_GPIO3B4); - gpio_request(RK30_PIN3_PB4, "mmc0-data2"); - gpio_direction_output(RK30_PIN3_PB4,GPIO_LOW);//set mmc0-data2 to low. - - rk30_mux_api_set(GPIO3B5_SDMMC0DATA3_NAME, GPIO3B_GPIO3B5); - gpio_request(RK30_PIN3_PB5, "mmc0-data3"); - gpio_direction_output(RK30_PIN3_PB5,GPIO_LOW);//set mmc0-data3 to low. - #elif defined(CONFIG_ARCH_RK31) rk30_mux_api_set(GPIO3A2_SDMMC0CLKOUT_NAME, GPIO3A_GPIO3A2); gpio_request(RK30_PIN3_PA2, "mmc0-clk"); gpio_direction_output(RK30_PIN3_PA2,GPIO_LOW);//set mmc0-clk to low. @@ -92,7 +58,6 @@ static void rk29_sdmmc_gpio_open(int device_id, int on) rk30_mux_api_set(GPIO3A7_SDMMC0DATA3_NAME, GPIO3A_GPIO3A7); gpio_request(RK30_PIN3_PA7, "mmc0-data3"); gpio_direction_output(RK30_PIN3_PA7,GPIO_LOW);//set mmc0-data3 to low. - #endif mdelay(30); } #endif @@ -114,19 +79,6 @@ static void rk29_sdmmc_gpio_open(int device_id, int on) } else { - #if defined(CONFIG_ARCH_RK30) - rk30_mux_api_set(GPIO3C5_SDMMC1CLKOUT_NAME, GPIO3C_GPIO3C5); - gpio_request(RK30_PIN3_PC5, "mmc1-clk"); - gpio_direction_output(RK30_PIN3_PC5,GPIO_LOW);//set mmc1-clk to low. - - rk30_mux_api_set(GPIO3C0_SMMC1CMD_NAME, GPIO3C_GPIO3C0); - gpio_request(RK30_PIN3_PC0, "mmc1-cmd"); - gpio_direction_output(RK30_PIN3_PC0,GPIO_LOW);//set mmc1-cmd to low. - - rk30_mux_api_set(GPIO3C1_SDMMC1DATA0_NAME, GPIO3C_GPIO3C1); - gpio_request(RK30_PIN3_PC1, "mmc1-data0"); - gpio_direction_output(RK30_PIN3_PC1,GPIO_LOW);//set mmc1-data0 to low. - #elif defined(CONFIG_ARCH_RK31) rk30_mux_api_set(GPIO3C5_SDMMC1CLKOUT_RMIICLKOUT_RMIICLKIN_NAME, GPIO3C_GPIO3C5); gpio_request(RK30_PIN3_PC5, "mmc1-clk"); gpio_direction_output(RK30_PIN3_PC5,GPIO_LOW);//set mmc1-clk to low. @@ -138,7 +90,6 @@ static void rk29_sdmmc_gpio_open(int device_id, int on) rk30_mux_api_set(GPIO3C1_SDMMC1DATA0_RMIITXD1_NAME, GPIO3C_GPIO3C1); gpio_request(RK30_PIN3_PC1, "mmc1-data0"); gpio_direction_output(RK30_PIN3_PC1,GPIO_LOW);//set mmc1-data0 to low. - #endif mdelay(100); } #endif @@ -160,15 +111,9 @@ static void rk29_sdmmc_set_iomux_mmc0(unsigned int bus_width) case 1://SDMMC_CTYPE_4BIT: { - #if defined(CONFIG_ARCH_RK30) - rk30_mux_api_set(GPIO3B3_SDMMC0DATA1_NAME, GPIO3B_SDMMC0_DATA1); - rk30_mux_api_set(GPIO3B4_SDMMC0DATA2_NAME, GPIO3B_SDMMC0_DATA2); - rk30_mux_api_set(GPIO3B5_SDMMC0DATA3_NAME, GPIO3B_SDMMC0_DATA3); - #elif defined(CONFIG_ARCH_RK31) rk30_mux_api_set(GPIO3A5_SDMMC0DATA1_NAME, GPIO3A_SDMMC0DATA1); rk30_mux_api_set(GPIO3A6_SDMMC0DATA2_NAME, GPIO3A_SDMMC0DATA2); rk30_mux_api_set(GPIO3A7_SDMMC0DATA3_NAME, GPIO3A_SDMMC0DATA3); - #endif } break; @@ -176,17 +121,6 @@ static void rk29_sdmmc_set_iomux_mmc0(unsigned int bus_width) break; case 0xFFFF: //gpio_reset { - #if defined(CONFIG_ARCH_RK30) - rk30_mux_api_set(GPIO3A7_SDMMC0PWREN_NAME, GPIO3A_GPIO3A7); - gpio_request(RK30_PIN3_PA7,"sdmmc-power"); - gpio_direction_output(RK30_PIN3_PA7,GPIO_HIGH); //power-off - - rk29_sdmmc_gpio_open(0, 0); - - gpio_direction_output(RK30_PIN3_PA7,GPIO_LOW); //power-on - - rk29_sdmmc_gpio_open(0, 1); - #elif defined(CONFIG_ARCH_RK31) rk30_mux_api_set(GPIO3A1_SDMMC0PWREN_NAME, GPIO3A_GPIO3A1); gpio_request(RK30_PIN3_PA1,"sdmmc-power"); gpio_direction_output(RK30_PIN3_PA1,GPIO_HIGH); //power-off @@ -196,29 +130,11 @@ static void rk29_sdmmc_set_iomux_mmc0(unsigned int bus_width) gpio_direction_output(RK30_PIN3_PA1,GPIO_LOW); //power-on rk29_sdmmc_gpio_open(0, 1); - #endif } break; default: //case 0://SDMMC_CTYPE_1BIT: { - #if defined(CONFIG_ARCH_RK30) - rk30_mux_api_set(GPIO3B1_SDMMC0CMD_NAME, GPIO3B_SDMMC0_CMD); - rk30_mux_api_set(GPIO3B0_SDMMC0CLKOUT_NAME, GPIO3B_SDMMC0_CLKOUT); - rk30_mux_api_set(GPIO3B2_SDMMC0DATA0_NAME, GPIO3B_SDMMC0_DATA0); - - rk30_mux_api_set(GPIO3B3_SDMMC0DATA1_NAME, GPIO3B_GPIO3B3); - gpio_request(RK30_PIN3_PB3, "mmc0-data1"); - gpio_direction_output(RK30_PIN3_PB3,GPIO_HIGH);//set mmc0-data1 to high. - - rk30_mux_api_set(GPIO3B4_SDMMC0DATA2_NAME, GPIO3B_GPIO3B4); - gpio_request(RK30_PIN3_PB4, "mmc0-data2"); - gpio_direction_output(RK30_PIN3_PB4,GPIO_HIGH);//set mmc0-data2 to high. - - rk30_mux_api_set(GPIO3B5_SDMMC0DATA3_NAME, GPIO3B_GPIO3B5); - gpio_request(RK30_PIN3_PB5, "mmc0-data3"); - gpio_direction_output(RK30_PIN3_PB5,GPIO_HIGH);//set mmc0-data3 to high. - #elif defined(CONFIG_ARCH_RK31) rk30_mux_api_set(GPIO3A3_SDMMC0CMD_NAME, GPIO3A_SDMMC0CMD); rk30_mux_api_set(GPIO3A2_SDMMC0CLKOUT_NAME, GPIO3A_SDMMC0CLKOUT); rk30_mux_api_set(GPIO3A4_SDMMC0DATA0_NAME, GPIO3A_SDMMC0DATA0); @@ -234,7 +150,6 @@ static void rk29_sdmmc_set_iomux_mmc0(unsigned int bus_width) rk30_mux_api_set(GPIO3A7_SDMMC0DATA3_NAME, GPIO3A_GPIO3A7); gpio_request(RK30_PIN3_PA7, "mmc0-data3"); gpio_direction_output(RK30_PIN3_PA7,GPIO_HIGH);//set mmc0-data3 to high. - #endif } break; } @@ -242,21 +157,12 @@ static void rk29_sdmmc_set_iomux_mmc0(unsigned int bus_width) static void rk29_sdmmc_set_iomux_mmc1(unsigned int bus_width) { -#if defined(CONFIG_ARCH_RK30) - rk30_mux_api_set(GPIO3C0_SMMC1CMD_NAME, GPIO3C_SMMC1_CMD); - rk30_mux_api_set(GPIO3C5_SDMMC1CLKOUT_NAME, GPIO3C_SDMMC1_CLKOUT); - rk30_mux_api_set(GPIO3C1_SDMMC1DATA0_NAME, GPIO3C_SDMMC1_DATA0); - rk30_mux_api_set(GPIO3C2_SDMMC1DATA1_NAME, GPIO3C_SDMMC1_DATA1); - rk30_mux_api_set(GPIO3C3_SDMMC1DATA2_NAME, GPIO3C_SDMMC1_DATA2); - rk30_mux_api_set(GPIO3C4_SDMMC1DATA3_NAME, GPIO3C_SDMMC1_DATA3); -#elif defined(CONFIG_ARCH_RK31) rk30_mux_api_set(GPIO3C0_SDMMC1CMD_RMIITXEN_NAME, GPIO3C_SDMMC1CMD); rk30_mux_api_set(GPIO3C5_SDMMC1CLKOUT_RMIICLKOUT_RMIICLKIN_NAME, GPIO3C_SDMMC1CLKOUT); rk30_mux_api_set(GPIO3C1_SDMMC1DATA0_RMIITXD1_NAME, GPIO3C_SDMMC1DATA0); rk30_mux_api_set(GPIO3C2_SDMMC1DATA1_RMIITXD0_NAME, GPIO3C_SDMMC1DATA1); rk30_mux_api_set(GPIO3C3_SDMMC1DATA2_RMIIRXD0_NAME, GPIO3C_SDMMC1DATA2); rk30_mux_api_set(GPIO3C4_SDMMC1DATA3_RMIIRXD1_NAME, GPIO3C_SDMMC1DATA3); -#endif } static void rk29_sdmmc_set_iomux_mmc2(unsigned int bus_width) @@ -397,6 +303,7 @@ static int __init rk29sdk_wifi_bt_gpio_control_init(void) { rk29sdk_init_wifi_mem(); +#ifndef CONFIG_ARCH_RK3066B rk29_mux_api_set(GPIO3D0_SDMMC1PWREN_NAME, GPIO3D_GPIO3D0); if (gpio_request(RK30SDK_WIFI_GPIO_POWER_N, "wifi_power")) { @@ -436,6 +343,7 @@ static int __init rk29sdk_wifi_bt_gpio_control_init(void) rk29_sdmmc_gpio_open(1, 0); //added by xbw at 2011-10-13 #endif +#endif pr_info("%s: init finished\n",__func__); return 0; diff --git a/arch/arm/mach-rk30/board-rk3066b-sdk.c b/arch/arm/mach-rk30/board-rk3066b-sdk.c index 97f86c821884..3878f61ec2ff 100644 --- a/arch/arm/mach-rk30/board-rk3066b-sdk.c +++ b/arch/arm/mach-rk30/board-rk3066b-sdk.c @@ -1,4 +1,4 @@ -/* arch/arm/mach-rk30/board-rk30-sdk.c +/* * * Copyright (C) 2012 ROCKCHIP, Inc. * @@ -70,460 +70,21 @@ #define RK30_FB0_MEM_SIZE 8*SZ_1M #endif -#ifdef CONFIG_VIDEO_RK29 -/*---------------- Camera Sensor Macro Define Begin ------------------------*/ -/*---------------- Camera Sensor Configuration Macro Begin ------------------------*/ -#define CONFIG_SENSOR_0 RK29_CAM_SENSOR_OV5642 /* back camera sensor */ -#define CONFIG_SENSOR_IIC_ADDR_0 0 -#define CONFIG_SENSOR_IIC_ADAPTER_ID_0 4 -#define CONFIG_SENSOR_ORIENTATION_0 90 -#define CONFIG_SENSOR_POWER_PIN_0 INVALID_GPIO -#define CONFIG_SENSOR_RESET_PIN_0 INVALID_GPIO -#define CONFIG_SENSOR_POWERDN_PIN_0 RK30_PIN1_PD6 -#define CONFIG_SENSOR_FALSH_PIN_0 INVALID_GPIO -#define CONFIG_SENSOR_POWERACTIVE_LEVEL_0 RK29_CAM_POWERACTIVE_L -#define CONFIG_SENSOR_RESETACTIVE_LEVEL_0 RK29_CAM_RESETACTIVE_L -#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_0 RK29_CAM_POWERDNACTIVE_H -#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_0 RK29_CAM_FLASHACTIVE_L - -#define CONFIG_SENSOR_QCIF_FPS_FIXED_0 15000 -#define CONFIG_SENSOR_240X160_FPS_FIXED_0 15000 -#define CONFIG_SENSOR_QVGA_FPS_FIXED_0 15000 -#define CONFIG_SENSOR_CIF_FPS_FIXED_0 15000 -#define CONFIG_SENSOR_VGA_FPS_FIXED_0 15000 -#define CONFIG_SENSOR_480P_FPS_FIXED_0 15000 -#define CONFIG_SENSOR_SVGA_FPS_FIXED_0 15000 -#define CONFIG_SENSOR_720P_FPS_FIXED_0 30000 - -#define CONFIG_SENSOR_01 RK29_CAM_SENSOR_OV5642 /* back camera sensor 1 */ -#define CONFIG_SENSOR_IIC_ADDR_01 0x00 -#define CONFIG_SENSOR_IIC_ADAPTER_ID_01 4 -#define CONFIG_SENSOR_ORIENTATION_01 90 -#define CONFIG_SENSOR_POWER_PIN_01 INVALID_GPIO -#define CONFIG_SENSOR_RESET_PIN_01 INVALID_GPIO -#define CONFIG_SENSOR_POWERDN_PIN_01 RK30_PIN1_PD6 -#define CONFIG_SENSOR_FALSH_PIN_01 INVALID_GPIO -#define CONFIG_SENSOR_POWERACTIVE_LEVEL_01 RK29_CAM_POWERACTIVE_L -#define CONFIG_SENSOR_RESETACTIVE_LEVEL_01 RK29_CAM_RESETACTIVE_L -#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_01 RK29_CAM_POWERDNACTIVE_H -#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_01 RK29_CAM_FLASHACTIVE_L - -#define CONFIG_SENSOR_QCIF_FPS_FIXED_01 15000 -#define CONFIG_SENSOR_240X160_FPS_FIXED_01 15000 -#define CONFIG_SENSOR_QVGA_FPS_FIXED_01 15000 -#define CONFIG_SENSOR_CIF_FPS_FIXED_01 15000 -#define CONFIG_SENSOR_VGA_FPS_FIXED_01 15000 -#define CONFIG_SENSOR_480P_FPS_FIXED_01 15000 -#define CONFIG_SENSOR_SVGA_FPS_FIXED_01 15000 -#define CONFIG_SENSOR_720P_FPS_FIXED_01 30000 - -#define CONFIG_SENSOR_02 RK29_CAM_SENSOR_OV5640 /* back camera sensor 2 */ -#define CONFIG_SENSOR_IIC_ADDR_02 0x00 -#define CONFIG_SENSOR_CIF_INDEX_02 0 -#define CONFIG_SENSOR_IIC_ADAPTER_ID_02 4 -#define CONFIG_SENSOR_ORIENTATION_02 90 -#define CONFIG_SENSOR_POWER_PIN_02 INVALID_GPIO -#define CONFIG_SENSOR_RESET_PIN_02 INVALID_GPIO -#define CONFIG_SENSOR_POWERDN_PIN_02 INVALID_GPIO -#define CONFIG_SENSOR_FALSH_PIN_02 INVALID_GPIO -#define CONFIG_SENSOR_POWERACTIVE_LEVEL_02 RK29_CAM_POWERACTIVE_L -#define CONFIG_SENSOR_RESETACTIVE_LEVEL_02 RK29_CAM_RESETACTIVE_L -#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_02 RK29_CAM_POWERDNACTIVE_H -#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_02 RK29_CAM_FLASHACTIVE_L - -#define CONFIG_SENSOR_QCIF_FPS_FIXED_02 15000 -#define CONFIG_SENSOR_240X160_FPS_FIXED_02 15000 -#define CONFIG_SENSOR_QVGA_FPS_FIXED_02 15000 -#define CONFIG_SENSOR_CIF_FPS_FIXED_02 15000 -#define CONFIG_SENSOR_VGA_FPS_FIXED_02 15000 -#define CONFIG_SENSOR_480P_FPS_FIXED_02 15000 -#define CONFIG_SENSOR_SVGA_FPS_FIXED_02 15000 -#define CONFIG_SENSOR_720P_FPS_FIXED_02 30000 - -#define CONFIG_SENSOR_1 RK29_CAM_SENSOR_OV2659 /* front camera sensor 0 */ -#define CONFIG_SENSOR_IIC_ADDR_1 0x60 -#define CONFIG_SENSOR_IIC_ADAPTER_ID_1 3 -#define CONFIG_SENSOR_ORIENTATION_1 270 -#define CONFIG_SENSOR_POWER_PIN_1 INVALID_GPIO -#define CONFIG_SENSOR_RESET_PIN_1 INVALID_GPIO -#define CONFIG_SENSOR_POWERDN_PIN_1 RK30_PIN2_PC7 -#define CONFIG_SENSOR_FALSH_PIN_1 INVALID_GPIO -#define CONFIG_SENSOR_POWERACTIVE_LEVEL_1 RK29_CAM_POWERACTIVE_L -#define CONFIG_SENSOR_RESETACTIVE_LEVEL_1 RK29_CAM_RESETACTIVE_L -#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_1 RK29_CAM_POWERDNACTIVE_H -#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_1 RK29_CAM_FLASHACTIVE_L - -#define CONFIG_SENSOR_QCIF_FPS_FIXED_1 15000 -#define CONFIG_SENSOR_240X160_FPS_FIXED_1 15000 -#define CONFIG_SENSOR_QVGA_FPS_FIXED_1 15000 -#define CONFIG_SENSOR_CIF_FPS_FIXED_1 15000 -#define CONFIG_SENSOR_VGA_FPS_FIXED_1 15000 -#define CONFIG_SENSOR_480P_FPS_FIXED_1 15000 -#define CONFIG_SENSOR_SVGA_FPS_FIXED_1 15000 -#define CONFIG_SENSOR_720P_FPS_FIXED_1 30000 - -#define CONFIG_SENSOR_11 RK29_CAM_SENSOR_OV2659 /* front camera sensor 1 */ -#define CONFIG_SENSOR_IIC_ADDR_11 0x00 -#define CONFIG_SENSOR_IIC_ADAPTER_ID_11 3 -#define CONFIG_SENSOR_ORIENTATION_11 270 -#define CONFIG_SENSOR_POWER_PIN_11 INVALID_GPIO -#define CONFIG_SENSOR_RESET_PIN_11 INVALID_GPIO -#define CONFIG_SENSOR_POWERDN_PIN_11 INVALID_GPIO//RK30_PIN1_PB7 -#define CONFIG_SENSOR_FALSH_PIN_11 INVALID_GPIO -#define CONFIG_SENSOR_POWERACTIVE_LEVEL_11 RK29_CAM_POWERACTIVE_L -#define CONFIG_SENSOR_RESETACTIVE_LEVEL_11 RK29_CAM_RESETACTIVE_L -#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_11 RK29_CAM_POWERDNACTIVE_H -#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_11 RK29_CAM_FLASHACTIVE_L - -#define CONFIG_SENSOR_QCIF_FPS_FIXED_11 15000 -#define CONFIG_SENSOR_240X160_FPS_FIXED_11 15000 -#define CONFIG_SENSOR_QVGA_FPS_FIXED_11 15000 -#define CONFIG_SENSOR_CIF_FPS_FIXED_11 15000 -#define CONFIG_SENSOR_VGA_FPS_FIXED_11 15000 -#define CONFIG_SENSOR_480P_FPS_FIXED_11 15000 -#define CONFIG_SENSOR_SVGA_FPS_FIXED_11 15000 -#define CONFIG_SENSOR_720P_FPS_FIXED_11 30000 - -#define CONFIG_SENSOR_12 RK29_CAM_SENSOR_OV2659//RK29_CAM_SENSOR_OV2655 /* front camera sensor 2 */ -#define CONFIG_SENSOR_IIC_ADDR_12 0x00 -#define CONFIG_SENSOR_IIC_ADAPTER_ID_12 3 -#define CONFIG_SENSOR_ORIENTATION_12 270 -#define CONFIG_SENSOR_POWER_PIN_12 INVALID_GPIO -#define CONFIG_SENSOR_RESET_PIN_12 INVALID_GPIO -#define CONFIG_SENSOR_POWERDN_PIN_12 INVALID_GPIO//RK30_PIN1_PB7 -#define CONFIG_SENSOR_FALSH_PIN_12 INVALID_GPIO -#define CONFIG_SENSOR_POWERACTIVE_LEVEL_12 RK29_CAM_POWERACTIVE_L -#define CONFIG_SENSOR_RESETACTIVE_LEVEL_12 RK29_CAM_RESETACTIVE_L -#define CONFIG_SENSOR_POWERDNACTIVE_LEVEL_12 RK29_CAM_POWERDNACTIVE_H -#define CONFIG_SENSOR_FLASHACTIVE_LEVEL_12 RK29_CAM_FLASHACTIVE_L - -#define CONFIG_SENSOR_QCIF_FPS_FIXED_12 15000 -#define CONFIG_SENSOR_240X160_FPS_FIXED_12 15000 -#define CONFIG_SENSOR_QVGA_FPS_FIXED_12 15000 -#define CONFIG_SENSOR_CIF_FPS_FIXED_12 15000 -#define CONFIG_SENSOR_VGA_FPS_FIXED_12 15000 -#define CONFIG_SENSOR_480P_FPS_FIXED_12 15000 -#define CONFIG_SENSOR_SVGA_FPS_FIXED_12 15000 -#define CONFIG_SENSOR_720P_FPS_FIXED_12 30000 - - -#endif //#ifdef CONFIG_VIDEO_RK29 -/*---------------- Camera Sensor Configuration Macro End------------------------*/ -#include "../../../drivers/media/video/rk30_camera.c" -/*---------------- Camera Sensor Macro Define End ---------*/ - -#define PMEM_CAM_SIZE PMEM_CAM_NECESSARY -/***************************************************************************************** - * camera devices - * author: ddl@rock-chips.com - *****************************************************************************************/ -#ifdef CONFIG_VIDEO_RK29 -#define CONFIG_SENSOR_POWER_IOCTL_USR 1 //define this refer to your board layout -#define CONFIG_SENSOR_RESET_IOCTL_USR 0 -#define CONFIG_SENSOR_POWERDOWN_IOCTL_USR 0 -#define CONFIG_SENSOR_FLASH_IOCTL_USR 0 - -static void rk_cif_power(int on) -{ - struct regulator *ldo_18,*ldo_28; - ldo_28 = regulator_get(NULL, "ldo7"); // vcc28_cif - ldo_18 = regulator_get(NULL, "ldo1"); // vcc18_cif - if (ldo_28 == NULL || IS_ERR(ldo_28) || ldo_18 == NULL || IS_ERR(ldo_18)){ - printk("get cif ldo failed!\n"); - return; - } - if(on == 0){ - regulator_disable(ldo_28); - regulator_put(ldo_28); - regulator_disable(ldo_18); - regulator_put(ldo_18); - mdelay(500); - } - else{ - regulator_set_voltage(ldo_28, 2800000, 2800000); - regulator_enable(ldo_28); - // printk("%s set ldo7 vcc28_cif=%dmV end\n", __func__, regulator_get_voltage(ldo_28)); - regulator_put(ldo_28); - - regulator_set_voltage(ldo_18, 1800000, 1800000); - // regulator_set_suspend_voltage(ldo, 1800000); - regulator_enable(ldo_18); - // printk("%s set ldo1 vcc18_cif=%dmV end\n", __func__, regulator_get_voltage(ldo_18)); - regulator_put(ldo_18); - } -} - -#if CONFIG_SENSOR_POWER_IOCTL_USR -static int sensor_power_usr_cb (struct rk29camera_gpio_res *res,int on) -{ - //#error "CONFIG_SENSOR_POWER_IOCTL_USR is 1, sensor_power_usr_cb function must be writed!!"; - rk_cif_power(on); -} -#endif - -#if CONFIG_SENSOR_RESET_IOCTL_USR -static int sensor_reset_usr_cb (struct rk29camera_gpio_res *res,int on) -{ - #error "CONFIG_SENSOR_RESET_IOCTL_USR is 1, sensor_reset_usr_cb function must be writed!!"; -} -#endif - -#if CONFIG_SENSOR_POWERDOWN_IOCTL_USR -static int sensor_powerdown_usr_cb (struct rk29camera_gpio_res *res,int on) -{ - #error "CONFIG_SENSOR_POWERDOWN_IOCTL_USR is 1, sensor_powerdown_usr_cb function must be writed!!"; -} -#endif - -#if CONFIG_SENSOR_FLASH_IOCTL_USR -static int sensor_flash_usr_cb (struct rk29camera_gpio_res *res,int on) -{ - #error "CONFIG_SENSOR_FLASH_IOCTL_USR is 1, sensor_flash_usr_cb function must be writed!!"; -} -#endif - -static struct rk29camera_platform_ioctl_cb sensor_ioctl_cb = { - #if CONFIG_SENSOR_POWER_IOCTL_USR - .sensor_power_cb = sensor_power_usr_cb, - #else - .sensor_power_cb = NULL, - #endif - - #if CONFIG_SENSOR_RESET_IOCTL_USR - .sensor_reset_cb = sensor_reset_usr_cb, - #else - .sensor_reset_cb = NULL, - #endif - - #if CONFIG_SENSOR_POWERDOWN_IOCTL_USR - .sensor_powerdown_cb = sensor_powerdown_usr_cb, - #else - .sensor_powerdown_cb = NULL, - #endif - - #if CONFIG_SENSOR_FLASH_IOCTL_USR - .sensor_flash_cb = sensor_flash_usr_cb, - #else - .sensor_flash_cb = NULL, - #endif -}; - -#if CONFIG_SENSOR_IIC_ADDR_0 -static struct reginfo_t rk_init_data_sensor_reg_0[] = -{ - {0x0000, 0x00,0,0} - }; -static struct reginfo_t rk_init_data_sensor_winseqreg_0[] ={ - {0x0000, 0x00,0,0} - }; -#endif - -#if CONFIG_SENSOR_IIC_ADDR_1 -static struct reginfo_t rk_init_data_sensor_reg_1[] = -{ - {0x0000, 0x00,0,0} -}; -static struct reginfo_t rk_init_data_sensor_winseqreg_1[] = -{ - {0x0000, 0x00,0,0} -}; -#endif -#if CONFIG_SENSOR_IIC_ADDR_01 -static struct reginfo_t rk_init_data_sensor_reg_01[] = -{ - {0x0000, 0x00,0,0} -}; -static struct reginfo_t rk_init_data_sensor_winseqreg_01[] = -{ - {0x0000, 0x00,0,0} -}; -#endif -#if CONFIG_SENSOR_IIC_ADDR_02 -static struct reginfo_t rk_init_data_sensor_reg_02[] = -{ - {0x0000, 0x00,0,0} -}; -static struct reginfo_t rk_init_data_sensor_winseqreg_02[] = -{ - {0x0000, 0x00,0,0} -}; -#endif -#if CONFIG_SENSOR_IIC_ADDR_11 -static struct reginfo_t rk_init_data_sensor_reg_11[] = -{ - {0x0000, 0x00,0,0} -}; -static struct reginfo_t rk_init_data_sensor_winseqreg_11[] = -{ - {0x0000, 0x00,0,0} -}; -#endif -#if CONFIG_SENSOR_IIC_ADDR_12 -static struct reginfo_t rk_init_data_sensor_reg_12[] = -{ - {0x0000, 0x00,0,0} -}; -static struct reginfo_t rk_init_data_sensor_winseqreg_12[] = -{ - {0x0000, 0x00,0,0} -}; -#endif -static rk_sensor_user_init_data_s rk_init_data_sensor[RK_CAM_NUM] = -{ - #if CONFIG_SENSOR_IIC_ADDR_0 - { - .rk_sensor_init_width = INVALID_VALUE, - .rk_sensor_init_height = INVALID_VALUE, - .rk_sensor_init_bus_param = INVALID_VALUE, - .rk_sensor_init_pixelcode = INVALID_VALUE, - .rk_sensor_init_data = rk_init_data_sensor_reg_0, - .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_0, - .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_0) / sizeof(struct reginfo_t), - .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_0) / sizeof(struct reginfo_t), - }, - #else - { - .rk_sensor_init_width = INVALID_VALUE, - .rk_sensor_init_height = INVALID_VALUE, - .rk_sensor_init_bus_param = INVALID_VALUE, - .rk_sensor_init_pixelcode = INVALID_VALUE, - .rk_sensor_init_data = NULL, - .rk_sensor_init_winseq = NULL, - .rk_sensor_winseq_size = 0, - .rk_sensor_init_data_size = 0, - }, - #endif - #if CONFIG_SENSOR_IIC_ADDR_1 - { - .rk_sensor_init_width = INVALID_VALUE, - .rk_sensor_init_height = INVALID_VALUE, - .rk_sensor_init_bus_param = INVALID_VALUE, - .rk_sensor_init_pixelcode = INVALID_VALUE, - .rk_sensor_init_data = rk_init_data_sensor_reg_1, - .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_1, - .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_1) / sizeof(struct reginfo_t), - .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_1) / sizeof(struct reginfo_t), - }, - #else - { - .rk_sensor_init_width = INVALID_VALUE, - .rk_sensor_init_height = INVALID_VALUE, - .rk_sensor_init_bus_param = INVALID_VALUE, - .rk_sensor_init_pixelcode = INVALID_VALUE, - .rk_sensor_init_data = NULL, - .rk_sensor_init_winseq = NULL, - .rk_sensor_winseq_size = 0, - .rk_sensor_init_data_size = 0, - }, - #endif - #if CONFIG_SENSOR_IIC_ADDR_01 - { - .rk_sensor_init_width = INVALID_VALUE, - .rk_sensor_init_height = INVALID_VALUE, - .rk_sensor_init_bus_param = INVALID_VALUE, - .rk_sensor_init_pixelcode = INVALID_VALUE, - .rk_sensor_init_data = rk_init_data_sensor_reg_01, - .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_01, - .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_01) / sizeof(struct reginfo_t), - .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_01) / sizeof(struct reginfo_t), - }, - #else - { - .rk_sensor_init_width = INVALID_VALUE, - .rk_sensor_init_height = INVALID_VALUE, - .rk_sensor_init_bus_param = INVALID_VALUE, - .rk_sensor_init_pixelcode = INVALID_VALUE, - .rk_sensor_init_data = NULL, - .rk_sensor_init_winseq = NULL, - .rk_sensor_winseq_size = 0, - .rk_sensor_init_data_size = 0, - }, - #endif - #if CONFIG_SENSOR_IIC_ADDR_02 - { - .rk_sensor_init_width = INVALID_VALUE, - .rk_sensor_init_height = INVALID_VALUE, - .rk_sensor_init_bus_param = INVALID_VALUE, - .rk_sensor_init_pixelcode = INVALID_VALUE, - .rk_sensor_init_data = rk_init_data_sensor_reg_02, - .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_02, - .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_02) / sizeof(struct reginfo_t), - .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_02) / sizeof(struct reginfo_t), - }, - #else - { - .rk_sensor_init_width = INVALID_VALUE, - .rk_sensor_init_height = INVALID_VALUE, - .rk_sensor_init_bus_param = INVALID_VALUE, - .rk_sensor_init_pixelcode = INVALID_VALUE, - .rk_sensor_init_data = NULL, - .rk_sensor_init_winseq = NULL, - .rk_sensor_winseq_size = 0, - .rk_sensor_init_data_size = 0, - }, - #endif - #if CONFIG_SENSOR_IIC_ADDR_11 - { - .rk_sensor_init_width = INVALID_VALUE, - .rk_sensor_init_height = INVALID_VALUE, - .rk_sensor_init_bus_param = INVALID_VALUE, - .rk_sensor_init_pixelcode = INVALID_VALUE, - .rk_sensor_init_data = rk_init_data_sensor_reg_11, - .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_11, - .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_11) / sizeof(struct reginfo_t), - .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_11) / sizeof(struct reginfo_t), - }, - #else - { - .rk_sensor_init_width = INVALID_VALUE, - .rk_sensor_init_height = INVALID_VALUE, - .rk_sensor_init_bus_param = INVALID_VALUE, - .rk_sensor_init_pixelcode = INVALID_VALUE, - .rk_sensor_init_data = NULL, - .rk_sensor_init_winseq = NULL, - .rk_sensor_winseq_size = 0, - .rk_sensor_init_data_size = 0, - }, - #endif - #if CONFIG_SENSOR_IIC_ADDR_12 - { - .rk_sensor_init_width = INVALID_VALUE, - .rk_sensor_init_height = INVALID_VALUE, - .rk_sensor_init_bus_param = INVALID_VALUE, - .rk_sensor_init_pixelcode = INVALID_VALUE, - .rk_sensor_init_data = rk_init_data_sensor_reg_12, - .rk_sensor_init_winseq = rk_init_data_sensor_winseqreg_12, - .rk_sensor_winseq_size = sizeof(rk_init_data_sensor_winseqreg_12) / sizeof(struct reginfo_t), - .rk_sensor_init_data_size = sizeof(rk_init_data_sensor_reg_12) / sizeof(struct reginfo_t), - }, - #else - { - .rk_sensor_init_width = INVALID_VALUE, - .rk_sensor_init_height = INVALID_VALUE, - .rk_sensor_init_bus_param = INVALID_VALUE, - .rk_sensor_init_pixelcode = INVALID_VALUE, - .rk_sensor_init_data = NULL, - .rk_sensor_init_winseq = NULL, - .rk_sensor_winseq_size = 0, - .rk_sensor_init_data_size = 0, - }, - #endif - - }; -#include "../../../drivers/media/video/rk30_camera.c" - -#endif /* CONFIG_VIDEO_RK29 */ +#include "board-rk3066b-sdk-camera.c" +#include "board-rk3066b-sdk-key.c" #if defined(CONFIG_TOUCHSCREEN_GT8XX) #define TOUCH_RESET_PIN RK30_PIN2_PC0 #define TOUCH_PWR_PIN INVALID_GPIO -int goodix_init_platform_hw(void) +static int goodix_init_platform_hw(void) { int ret; +#ifndef CONFIG_ARCH_RK3066B rk30_mux_api_set(GPIO4D0_SMCDATA8_TRACEDATA8_NAME, GPIO4D_GPIO4D0); rk30_mux_api_set(GPIO4C2_SMCDATA2_TRACEDATA2_NAME, GPIO4C_GPIO4C2); printk("%s:0x%x,0x%x\n",__func__,rk30_mux_api_get(GPIO4D0_SMCDATA8_TRACEDATA8_NAME),rk30_mux_api_get(GPIO4C2_SMCDATA2_TRACEDATA2_NAME)); +#endif if (TOUCH_PWR_PIN != INVALID_GPIO) { ret = gpio_request(TOUCH_PWR_PIN, "goodix power pin"); @@ -792,7 +353,9 @@ struct platform_device rk29_device_mt6229 = { static int mma8452_init_platform_hw(void) { +#ifndef CONFIG_ARCH_RK3066B rk30_mux_api_set(GPIO4C0_SMCDATA0_TRACEDATA0_NAME, GPIO4C_GPIO4C0); +#endif return 0; } @@ -810,7 +373,9 @@ static struct sensor_platform_data mma8452_info = { static int lis3dh_init_platform_hw(void) { +#ifndef CONFIG_ARCH_RK3066B rk30_mux_api_set(GPIO4C0_SMCDATA0_TRACEDATA0_NAME, GPIO4C_GPIO4C0); +#endif return 0; } @@ -866,7 +431,9 @@ static struct sensor_platform_data akm8975_info = static int l3g4200d_init_platform_hw(void) { +#ifndef CONFIG_ARCH_RK3066B rk30_mux_api_set(GPIO4C3_SMCDATA3_TRACEDATA3_NAME, GPIO4C_GPIO4C3); +#endif return 0; } diff --git a/arch/arm/mach-rk30/clock.h b/arch/arm/mach-rk30/clock.h index a7f2de30c9f8..fdecd15d4975 100644 --- a/arch/arm/mach-rk30/clock.h +++ b/arch/arm/mach-rk30/clock.h @@ -1,7 +1,7 @@ #ifndef __MACH_CLOCK_H__ #define __MACH_CLOCK_H__ -#if (!defined(CONFIG_ARCH_RK30) && !defined(CONFIG_ARCH_RK31)) +#ifndef CONFIG_ARCH_RK30 #define RK30_CLK_OFFBOARD_TEST #endif diff --git a/arch/arm/mach-rk30/devices.c b/arch/arm/mach-rk30/devices.c index c38d07903b1a..b770f0246167 100755 --- a/arch/arm/mach-rk30/devices.c +++ b/arch/arm/mach-rk30/devices.c @@ -373,6 +373,12 @@ static void __init rk30_init_uart(void) static int i2c0_check_idle(void) { int sda_level, scl_level; + +#if defined(CONFIG_ARCH_RK3066B) +#warning fix i2c0_check_idle + scl_level = 1; + sda_level = 1; +#else rk30_mux_api_set(GPIO2D5_I2C0SCL_NAME, GPIO2D_GPIO2D5); rk30_mux_api_set(GPIO2D4_I2C0SDA_NAME, GPIO2D_GPIO2D4); @@ -390,6 +396,7 @@ static int i2c0_check_idle(void) rk30_mux_api_set(GPIO2D5_I2C0SCL_NAME, GPIO2D_I2C0_SCL); rk30_mux_api_set(GPIO2D4_I2C0SDA_NAME, GPIO2D_I2C0_SDA); +#endif if(sda_level == 1 && scl_level == 1) return I2C_IDLE; @@ -436,6 +443,12 @@ static struct platform_device device_i2c0 = { static int i2c1_check_idle(void) { int sda_level, scl_level; + +#if defined(CONFIG_ARCH_RK3066B) +#warning fix i2c1_check_idle + scl_level = 1; + sda_level = 1; +#else rk30_mux_api_set(GPIO2D7_I2C1SCL_NAME, GPIO2D_GPIO2D7); rk30_mux_api_set(GPIO2D6_I2C1SDA_NAME, GPIO2D_GPIO2D6); @@ -453,6 +466,7 @@ static int i2c1_check_idle(void) rk30_mux_api_set(GPIO2D7_I2C1SCL_NAME, GPIO2D_I2C1_SCL); rk30_mux_api_set(GPIO2D6_I2C1SDA_NAME, GPIO2D_I2C1_SDA); +#endif if(sda_level == 1 && scl_level == 1) return I2C_IDLE; @@ -499,6 +513,12 @@ static struct platform_device device_i2c1 = { static int i2c2_check_idle(void) { int sda_level, scl_level; + +#if defined(CONFIG_ARCH_RK3066B) +#warning fix i2c2_check_idle + scl_level = 1; + sda_level = 1; +#else rk30_mux_api_set(GPIO3A1_I2C2SCL_NAME, GPIO3A_GPIO3A1); rk30_mux_api_set(GPIO3A0_I2C2SDA_NAME, GPIO3A_GPIO3A0); @@ -516,6 +536,7 @@ static int i2c2_check_idle(void) rk30_mux_api_set(GPIO3A1_I2C2SCL_NAME, GPIO3A_I2C2_SCL); rk30_mux_api_set(GPIO3A0_I2C2SDA_NAME, GPIO3A_I2C2_SDA); +#endif if(sda_level == 1 && scl_level == 1) return I2C_IDLE; @@ -563,6 +584,12 @@ static struct platform_device device_i2c2 = { static int i2c3_check_idle(void) { int sda_level, scl_level; + +#if defined(CONFIG_ARCH_RK3066B) +#warning fix i2c3_check_idle + scl_level = 1; + sda_level = 1; +#else rk30_mux_api_set(GPIO3A3_I2C3SCL_NAME, GPIO3A_GPIO3A3); rk30_mux_api_set(GPIO3A2_I2C3SDA_NAME, GPIO3A_GPIO3A2); @@ -580,6 +607,7 @@ static int i2c3_check_idle(void) rk30_mux_api_set(GPIO3A3_I2C3SCL_NAME, GPIO3A_I2C3_SCL); rk30_mux_api_set(GPIO3A2_I2C3SDA_NAME, GPIO3A_I2C3_SDA); +#endif if(sda_level == 1 && scl_level == 1) return I2C_IDLE; @@ -627,6 +655,12 @@ static struct platform_device device_i2c3 = { static int i2c4_check_idle(void) { int sda_level, scl_level; + +#if defined(CONFIG_ARCH_RK3066B) +#warning fix i2c4_check_idle + scl_level = 1; + sda_level = 1; +#else rk30_mux_api_set(GPIO3A5_I2C4SCL_NAME, GPIO3A_GPIO3A5); rk30_mux_api_set(GPIO3A4_I2C4SDA_NAME, GPIO3A_GPIO3A4); @@ -644,6 +678,7 @@ static int i2c4_check_idle(void) rk30_mux_api_set(GPIO3A5_I2C4SCL_NAME, GPIO3A_I2C4_SCL); rk30_mux_api_set(GPIO3A4_I2C4SDA_NAME, GPIO3A_I2C4_SDA); +#endif if(sda_level == 1 && scl_level == 1) return I2C_IDLE; diff --git a/arch/arm/mach-rk30/include/mach/io.h b/arch/arm/mach-rk30/include/mach/io.h index a16be19cd662..61901f4e4d81 100755 --- a/arch/arm/mach-rk30/include/mach/io.h +++ b/arch/arm/mach-rk30/include/mach/io.h @@ -26,7 +26,7 @@ #define RK30_IMEM_PHYS 0x10080000 #define RK30_IMEM_BASE IOMEM(0xFEF00000) #define RK30_IMEM_NONCACHED RK30_IO_TO_VIRT0(RK30_IMEM_PHYS) -#ifdef CONFIG_ARCH_RK31 +#if defined(CONFIG_ARCH_RK3066B) #define RK30_IMEM_SIZE SZ_16K #else #define RK30_IMEM_SIZE SZ_64K @@ -164,7 +164,7 @@ #define RK30_PWM01_PHYS 0x20030000 #define RK30_PWM01_BASE RK30_IO_TO_VIRT1(RK30_PWM01_PHYS) #define RK30_PWM01_SIZE SZ_16K -#ifdef CONFIG_ARCH_RK31 +#if defined(CONFIG_ARCH_RK3066B) #define RK30_GPIO0_PHYS 0x2000a000 #else #define RK30_GPIO0_PHYS 0x20034000 @@ -223,10 +223,10 @@ #define RK30_GPIO4_BASE RK30_IO_TO_VIRT1(RK30_GPIO4_PHYS) #define RK30_GPIO4_SIZE SZ_16K -#define RK31_GPS_PHYS 0x10230000 -#define RK31_GPS_SIZE SZ_64K -#define RK31_HSIC_PHYS 0x10240000 -#define RK31_HSIC_SIZE SZ_256K +#define RK30_GPS_PHYS 0x10230000 +#define RK30_GPS_SIZE SZ_64K +#define RK30_HSIC_PHYS 0x10240000 +#define RK30_HSIC_SIZE SZ_256K #if CONFIG_RK_DEBUG_UART == 0 #define DEBUG_UART_PHYS RK30_UART0_PHYS diff --git a/arch/arm/mach-rk30/include/mach/iomux-rk3066b.h b/arch/arm/mach-rk30/include/mach/iomux-rk3066b.h new file mode 100644 index 000000000000..340481d58e24 --- /dev/null +++ b/arch/arm/mach-rk30/include/mach/iomux-rk3066b.h @@ -0,0 +1,531 @@ +//GPIO0C +#define GPIO0C_GPIO0C0 0 +#define GPIO0C_FLASHDATA8 1 +#define GPIO0C_GPIO0C1 0 +#define GPIO0C_FLASHDATA9 1 +#define GPIO0C_GPIO0C2 0 +#define GPIO0C_FLASHDATA10 1 +#define GPIO0C_GPIO0C3 0 +#define GPIO0C_FLASHDATA11 1 +#define GPIO0C_GPIO0C4 0 +#define GPIO0C_FLASHDATA12 1 +#define GPIO0C_GPIO0C5 0 +#define GPIO0C_FLASHDATA13 1 +#define GPIO0C_GPIO0C6 0 +#define GPIO0C_FLASHDATA14 1 +#define GPIO0C_GPIO0C7 0 +#define GPIO0C_FLASHDATA15 1 + +//GPIO0D +#define GPIO0D_GPIO0D0 0 +#define GPIO0D_FLASHDQS 1 +#define GPIO0D_EMMCCLKOUT 2 +#define GPIO0D_GPIO0D1 0 +#define GPIO0D_FLASHCSN1 1 +#define GPIO0D_GPIO0D2 0 +#define GPIO0D_FLASHCSN2 1 +#define GPIO0D_EMMCCMD 2 +#define GPIO0D_GPIO0D3 0 +#define GPIO0D_FLASHCSN3 1 +#define GPIO0D_EMMCRSTNOUT 2 +#define GPIO0D_GPIO0D4 0 +#define GPIO0D_SPI1RXD 1 +#define GPIO0D_GPIO0D5 0 +#define GPIO0D_SPI1TXD 1 +#define GPIO0D_GPIO0D6 0 +#define GPIO0D_SPI1CLK 1 +#define GPIO0D_GPIO0D7 0 +#define GPIO0D_SPI1CSN0 1 + +//GPIO1A +#define GPIO1A_GPIO1A0 0 +#define GPIO1A_UART0SIN 1 +#define GPIO1A_GPIO1A1 0 +#define GPIO1A_UART0SOUT 1 +#define GPIO1A_GPIO1A2 0 +#define GPIO1A_UART0CTSN 1 +#define GPIO1A_GPIO1A3 0 +#define GPIO1A_UART0RTSN 1 +#define GPIO1A_GPIO1A4 0 +#define GPIO1A_UART1SIN 1 +#define GPIO1A_SPI0RXD 2 +#define GPIO1A_GPIO1A5 0 +#define GPIO1A_UART1SOUT 1 +#define GPIO1A_SPI0TXD 2 +#define GPIO1A_GPIO1A6 0 +#define GPIO1A_UART1CTSN 1 +#define GPIO1A_SPI0CLK 2 +#define GPIO1A_GPIO1A7 0 +#define GPIO1A_UART1RTSN 1 +#define GPIO1A_SPI0CSN0 2 + +//GPIO1B +#define GPIO1B_GPIO1B0 0 +#define GPIO1B_UART2SIN 1 +#define GPIO1B_JTAGTDI 2 +#define GPIO1B_GPIO1B1 0 +#define GPIO1B_UART2SOUT 1 +#define GPIO1B_JTAGTDO 2 +#define GPIO1B_GPIO1B2 0 +#define GPIO1B_UART3SIN 1 +#define GPIO1B_GPSMAG 2 +#define GPIO1B_GPIO1B3 0 +#define GPIO1B_UART3SOUT 1 +#define GPIO1B_GPSSIG 2 +#define GPIO1B_GPIO1B4 0 +#define GPIO1B_UART3CTSN 1 +#define GPIO1B_GPSRFCLK 2 +#define GPIO1B_GPIO1B5 0 +#define GPIO1B_UART3RTSN 1 +#define GPIO1B_GPIO1B6 0 +#define GPIO1B_SPDIFTX 1 +#define GPIO1B_SPI1CSN1 2 +#define GPIO1B_GPIO1B7 0 +#define GPIO1B_SPI0CSN1 1 + +//GPIO1C +#define GPIO1C_GPIO1C0 0 +#define GPIO1C_I2SCLK 1 +#define GPIO1C_GPIO1C1 0 +#define GPIO1C_I2SSCLK 1 +#define GPIO1C_GPIO1C2 0 +#define GPIO1C_I2SLRCLKRX 1 +#define GPIO1C_GPIO1C3 0 +#define GPIO1C_I2SLRCLKTX 1 +#define GPIO1C_GPIO1C4 0 +#define GPIO1C_I2SSDI 1 +#define GPIO1C_GPIO1C5 0 +#define GPIO1C_I2SSDO 1 + +//GPIO1D +#define GPIO1D_GPIO1D0 0 +#define GPIO1D_I2C0SDA 1 +#define GPIO1D_GPIO1D1 0 +#define GPIO1D_I2C0SCL 1 +#define GPIO1D_GPIO1D2 0 +#define GPIO1D_I2C1SDA 1 +#define GPIO1D_GPIO1D3 0 +#define GPIO1D_I2C1SCL 1 +#define GPIO1D_GPIO1D4 0 +#define GPIO1D_I2C2SDA 1 +#define GPIO1D_GPIO1D5 0 +#define GPIO1D_I2C2SCL 1 +#define GPIO1D_GPIO1D6 0 +#define GPIO1D_I2C4SDA 1 +#define GPIO1D_GPIO1D7 0 +#define GPIO1D_I2C4SCL 1 + +//GPIO2A +#define GPIO2A_GPIO2A0 0 +#define GPIO2A_LCDC1DATA0 1 +#define GPIO2A_SMCDATA0 2 +#define GPIO2A_TRACEDATA0 3 +#define GPIO2A_GPIO2A1 0 +#define GPIO2A_LCDC1DATA1 1 +#define GPIO2A_SMCDATA1 2 +#define GPIO2A_TRACEDATA1 3 +#define GPIO2A_GPIO2A2 0 +#define GPIO2A_LCDC1DATA2 1 +#define GPIO2A_SMCDATA2 2 +#define GPIO2A_TRACEDATA2 3 +#define GPIO2A_GPIO2A3 0 +#define GPIO2A_LCDC1DATA3 1 +#define GPIO2A_SMCDATA3 2 +#define GPIO2A_TRACEDATA3 3 +#define GPIO2A_GPIO2A4 0 +#define GPIO2A_LCDC1DATA4 1 +#define GPIO2A_SMCDATA4 2 +#define GPIO2A_TRACEDATA4 3 +#define GPIO2A_GPIO2A5 0 +#define GPIO2A_LCDC1DATA5 1 +#define GPIO2A_SMCDATA5 2 +#define GPIO2A_TRACEDATA5 3 +#define GPIO2A_GPIO2A6 0 +#define GPIO2A_LCDC1DATA6 1 +#define GPIO2A_SMCDATA6 2 +#define GPIO2A_TRACEDATA6 3 +#define GPIO2A_GPIO2A7 0 +#define GPIO2A_LCDC1DATA7 1 +#define GPIO2A_SMCDATA7 2 +#define GPIO2A_TRACEDATA7 3 + +//GPIO2B +#define GPIO2B_GPIO2B0 0 +#define GPIO2B_LCDC1DATA8 1 +#define GPIO2B_SMCDATA8 2 +#define GPIO2B_TRACEDATA8 3 +#define GPIO2B_GPIO2B1 0 +#define GPIO2B_LCDC1DATA9 1 +#define GPIO2B_SMCDATA9 2 +#define GPIO2B_TRACEDATA9 3 +#define GPIO2B_GPIO2B2 0 +#define GPIO2B_LCDC1DATA10 1 +#define GPIO2B_SMCDATA10 2 +#define GPIO2B_TRACEDATA10 3 +#define GPIO2B_GPIO2B3 0 +#define GPIO2B_LCDC1DATA11 1 +#define GPIO2B_SMCDATA11 2 +#define GPIO2B_TRACEDATA11 3 +#define GPIO2B_GPIO2B4 0 +#define GPIO2B_LCDC1DATA12 1 +#define GPIO2B_SMCDATA12 2 +#define GPIO2B_TRACEDATA12 3 +#define GPIO2B_GPIO2B5 0 +#define GPIO2B_LCDC1DATA13 1 +#define GPIO2B_SMCDATA13 2 +#define GPIO2B_TRACEDATA13 3 +#define GPIO2B_GPIO2B6 0 +#define GPIO2B_LCDC1DATA14 1 +#define GPIO2B_SMCDATA14 2 +#define GPIO2B_TRACEDATA14 3 +#define GPIO2B_GPIO2B7 0 +#define GPIO2B_LCDC1DATA15 1 +#define GPIO2B_SMCDATA15 2 +#define GPIO2B_TRACEDATA15 3 + +//GPIO2C +#define GPIO2C_GPIO2C0 0 +#define GPIO2C_LCDC1DATA16 1 +#define GPIO2C_SMCADDR0 2 +#define GPIO2C_GPIO2C1 0 +#define GPIO2C_LCDC1DATA17 1 +#define GPIO2C_SMCADDR1 2 +#define GPIO2C_GPIO2C2 0 +#define GPIO2C_LCDC1DATA18 1 +#define GPIO2C_SMCADDR2 2 +#define GPIO2C_GPIO2C3 0 +#define GPIO2C_LCDC1DATA19 1 +#define GPIO2C_SMCADDR3 2 +#define GPIO2C_GPIO2C4 0 +#define GPIO2C_LCDC1DATA20 1 +#define GPIO2C_SMCADDR4 2 +#define GPIO2C_GPIO2C5 0 +#define GPIO2C_LCDC1DATA21 1 +#define GPIO2C_SMCADDR5 2 +#define GPIO2C_GPIO2C6 0 +#define GPIO2C_LCDC1DATA22 1 +#define GPIO2C_SMCADDR6 2 +#define GPIO2C_GPIO2C7 0 +#define GPIO2C_LCDC1DATA23 1 +#define GPIO2C_SMCADDR7 2 + +//GPIO2D +#define GPIO2D_GPIO2D0 0 +#define GPIO2D_LCDC1DCLK 1 +#define GPIO2D_SMCCSN0 2 +#define GPIO2D_GPIO2D1 0 +#define GPIO2D_LCDC1DEN 1 +#define GPIO2D_SMCWEN 2 +#define GPIO2D_GPIO2D2 0 +#define GPIO2D_LCDC1HSYNC 1 +#define GPIO2D_SMCOEN 2 +#define GPIO2D_GPIO2D3 0 +#define GPIO2D_LCDC1VSYNC 1 +#define GPIO2D_SMCADVN 2 +#define GPIO2D_GPIO2D4 0 +#define GPIO2D_SMCBLSN0 1 +#define GPIO2D_GPIO2D5 0 +#define GPIO2D_SMCBLSN1 1 +#define GPIO2D_GPIO2D6 0 +#define GPIO2D_SMCCSN1 1 +#define GPIO2D_GPIO2D7 0 +#define GPIO2D_TESTCLOCKOUT 1 + +//GPIO3A +#define GPIO3A_GPIO3A0 0 +#define GPIO3A_SDMMC0RSTNOUT 1 +#define GPIO3A_GPIO3A1 0 +#define GPIO3A_SDMMC0PWREN 1 +#define GPIO3A_GPIO3A2 0 +#define GPIO3A_SDMMC0CLKOUT 1 +#define GPIO3A_GPIO3A3 0 +#define GPIO3A_SDMMC0CMD 1 +#define GPIO3A_GPIO3A4 0 +#define GPIO3A_SDMMC0DATA0 1 +#define GPIO3A_GPIO3A5 0 +#define GPIO3A_SDMMC0DATA1 1 +#define GPIO3A_GPIO3A6 0 +#define GPIO3A_SDMMC0DATA2 1 +#define GPIO3A_GPIO3A7 0 +#define GPIO3A_SDMMC0DATA3 1 + +//GPIO3B +#define GPIO3B_GPIO3B0 0 +#define GPIO3B_SDMMC0DETECTN 1 +#define GPIO3B_GPIO3B1 0 +#define GPIO3B_SDMMC0WRITEPRT 1 +#define GPIO3B_GPIO3B3 0 +#define GPIO3B_CIFCLKOUT 1 +#define GPIO3B_GPIO3B4 0 +#define GPIO3B_CIFDATA0 1 +#define GPIO3B_HSADCDATA8 2 +#define GPIO3B_GPIO3B5 0 +#define GPIO3B_CIFDATA1 1 +#define GPIO3B_HSADCDATA9 2 +#define GPIO3B_GPIO3B6 0 +#define GPIO3B_CIFDATA10 1 +#define GPIO3B_I2C3SDA 2 +#define GPIO3B_GPIO3B7 0 +#define GPIO3B_CIFDATA11 1 +#define GPIO3B_I2C3SCL 2 + +//GPIO3C +#define GPIO3C_GPIO3C0 0 +#define GPIO3C_SDMMC1CMD 1 +#define GPIO3C_RMIITXEN 2 +#define GPIO3C_GPIO3C1 0 +#define GPIO3C_SDMMC1DATA0 1 +#define GPIO3C_RMIITXD1 2 +#define GPIO3C_GPIO3C2 0 +#define GPIO3C_SDMMC1DATA1 1 +#define GPIO3C_RMIITXD0 2 +#define GPIO3C_GPIO3C3 0 +#define GPIO3C_SDMMC1DATA2 1 +#define GPIO3C_RMIIRXD0 2 +#define GPIO3C_GPIO3C4 0 +#define GPIO3C_SDMMC1DATA3 1 +#define GPIO3C_RMIIRXD1 2 +#define GPIO3C_GPIO3C5 0 +#define GPIO3C_SDMMC1CLKOUT 1 +#define GPIO3C_RMIICLKOUT 2 +#define GPIO3C_RMIICLKIN 3 +#define GPIO3C_GPIO3C6 0 +#define GPIO3C_SDMMC1DETECTN 1 +#define GPIO3C_RMIIRXERR 2 +#define GPIO3C_GPIO3C7 0 +#define GPIO3C_SDMMC1WRITEPRT 1 +#define GPIO3C_RMIICRS 2 + +//GPIO3D +#define GPIO3D_GPIO3D0 0 +#define GPIO3D_SDMMC1PWREN 1 +#define GPIO3D_MIIMD 2 +#define GPIO3D_GPIO3D1 0 +#define GPIO3D_SDMMC1BACKENPWR 1 +#define GPIO3D_MIIMDCLK 2 +#define GPIO3D_GPIO3D2 0 +#define GPIO3D_SDMMC1INTN 1 +#define GPIO3D_GPIO3D3 0 +#define GPIO3D_PWM0 1 +#define GPIO3D_GPIO3D4 0 +#define GPIO3D_PWM1 1 +#define GPIO3D_JTAGTRSTN 2 +#define GPIO3D_GPIO3D5 0 +#define GPIO3D_PWM2 1 +#define GPIO3D_JTAGTCK 2 +#define GPIO3D_OTGDRVVBUS 3 +#define GPIO3D_GPIO3D6 0 +#define GPIO3D_PWM3 1 +#define GPIO3D_JTAGTMS 2 +#define GPIO3D_HOSTDRVVBUS 3 + +#define GRF_GPIO0L_DIR 0x0000 +#define GRF_GPIO0H_DIR 0x0004 +#define GRF_GPIO1L_DIR 0x0008 +#define GRF_GPIO1H_DIR 0x000c +#define GRF_GPIO2L_DIR 0x0010 +#define GRF_GPIO2H_DIR 0x0014 +#define GRF_GPIO3L_DIR 0x0018 +#define GRF_GPIO3H_DIR 0x001c +#define GRF_GPIO0L_DO 0x0020 +#define GRF_GPIO0H_DO 0x0024 +#define GRF_GPIO1L_DO 0x0028 +#define GRF_GPIO1H_DO 0x002c +#define GRF_GPIO2L_DO 0x0030 +#define GRF_GPIO2H_DO 0x0034 +#define GRF_GPIO3L_DO 0x0038 +#define GRF_GPIO3H_DO 0x003c +#define GRF_GPIO0L_EN 0x0040 +#define GRF_GPIO0H_EN 0x0044 +#define GRF_GPIO1L_EN 0x0048 +#define GRF_GPIO1H_EN 0x004c +#define GRF_GPIO2L_EN 0x0050 +#define GRF_GPIO2H_EN 0x0054 +#define GRF_GPIO3L_EN 0x0058 +#define GRF_GPIO3H_EN 0x005c +#define GRF_GPIO0A_IOMUX RK30_GRF_BASE+0x0060 +#define GRF_GPIO0B_IOMUX RK30_GRF_BASE+0x0064 +#define GRF_GPIO0C_IOMUX RK30_GRF_BASE+0x0068 +#define GRF_GPIO0D_IOMUX RK30_GRF_BASE+0x006c +#define GRF_GPIO1A_IOMUX RK30_GRF_BASE+0x0070 +#define GRF_GPIO1B_IOMUX RK30_GRF_BASE+0x0074 +#define GRF_GPIO1C_IOMUX RK30_GRF_BASE+0x0078 +#define GRF_GPIO1D_IOMUX RK30_GRF_BASE+0x007c +#define GRF_GPIO2A_IOMUX RK30_GRF_BASE+0x0080 +#define GRF_GPIO2B_IOMUX RK30_GRF_BASE+0x0084 +#define GRF_GPIO2C_IOMUX RK30_GRF_BASE+0x0088 +#define GRF_GPIO2D_IOMUX RK30_GRF_BASE+0x008c +#define GRF_GPIO3A_IOMUX RK30_GRF_BASE+0x0090 +#define GRF_GPIO3B_IOMUX RK30_GRF_BASE+0x0094 +#define GRF_GPIO3C_IOMUX RK30_GRF_BASE+0x0098 +#define GRF_GPIO3D_IOMUX RK30_GRF_BASE+0x009c +#define GRF_SOC_CON0 0x00a0 +#define GRF_SOC_CON1 0x00a4 +#define GRF_SOC_CON2 0x00a8 +#define GRF_SOC_STATUS0 0x00ac +#define GRF_DMAC1_CON0 0x00b0 +#define GRF_DMAC1_CON1 0x00b4 +#define GRF_DMAC1_CON2 0x00b8 +#define GRF_DMAC2_CON0 0x00bc +#define GRF_DMAC2_CON1 0x00c0 +#define GRF_DMAC2_CON2 0x00c4 +#define GRF_DMAC2_CON3 0x00c8 +#define GRF_UOC0_CON0 0x010c +#define GRF_UOC0_CON1 0x0110 +#define GRF_UOC0_CON2 0x0114 +#define GRF_UOC0_CON3 0x0118 +#define GRF_UOC1_CON0 0x011c +#define GRF_UOC1_CON1 0x0120 +#define GRF_UOC1_CON2 0x0124 +#define GRF_UOC1_CON3 0x0128 +#define GRF_UOC2_CON0 0x012c +#define GRF_UOC2_CON1 0x0130 +#define GRF_UOC3_CON0 0x0138 +#define GRF_UOC3_CON1 0x013c +#define GRF_HSIC_STAT 0x0140 +#define GRF_DDRC_CON0 0x00ec +#define GRF_DDRC_STAT 0x00f0 +#define GRF_OS_REG0 0x0144 +#define GRF_OS_REG1 0x0148 +#define GRF_OS_REG2 0x014c +#define GRF_OS_REG3 0x0150 +#define GRF_OS_REG4 0x0154 +#define GRF_OS_REG5 0x0158 +#define GRF_OS_REG6 0x015c +#define GRF_OS_REG7 0x0160 + +//GPIO0C +#define GPIO0C0_FLASHDATA8_NAME "gpio0c0_flashdata8_name" +#define GPIO0C1_FLASHDATA9_NAME "gpio0c1_flashdata9_name" +#define GPIO0C2_FLASHDATA10_NAME "gpio0c2_flashdata10_name" +#define GPIO0C3_FLASHDATA11_NAME "gpio0c3_flashdata11_name" +#define GPIO0C4_FLASHDATA12_NAME "gpio0c4_flashdata12_name" +#define GPIO0C5_FLASHDATA13_NAME "gpio0c5_flashdata13_name" +#define GPIO0C6_FLASHDATA14_NAME "gpio0c6_flashdata14_name" +#define GPIO0C7_FLASHDATA15_NAME "gpio0c7_flashdata15_name" + +//GPIO0D +#define GPIO0D0_FLASHDQS_EMMCCLKOUT_NAME "gpio0d0_flashdqs_emmcclkout_name" +#define GPIO0D1_FLASHCSN1_NAME "gpio0d1_flashcsn1_name" +#define GPIO0D2_FLASHCSN2_EMMCCMD_NAME "gpio0d2_flashcsn2_emmccmd_name" +#define GPIO0D3_FLASHCSN3_EMMCRSTNOUT_NAME "gpio0d3_flashcsn3_emmcrstnout_name" +#define GPIO0D4_SPI1RXD_NAME "gpio0d4_spi1rxd_name" +#define GPIO0D5_SPI1TXD_NAME "gpio0d5_spi1txd_name" +#define GPIO0D6_SPI1CLK_NAME "gpio0d6_spi1clk_name" +#define GPIO0D7_SPI1CSN0_NAME "gpio0d7_spi1csn0_name" + +//GPIO1A +#define GPIO1A0_UART0SIN_NAME "gpio1a0_uart0sin_name" +#define GPIO1A1_UART0SOUT_NAME "gpio1a1_uart0sout_name" +#define GPIO1A2_UART0CTSN_NAME "gpio1a2_uart0ctsn_name" +#define GPIO1A3_UART0RTSN_NAME "gpio1a3_uart0rtsn_name" +#define GPIO1A4_UART1SIN_SPI0RXD_NAME "gpio1a4_uart1sin_spi0rxd_name" +#define GPIO1A5_UART1SOUT_SPI0TXD_NAME "gpio1a5_uart1sout_spi0txd_name" +#define GPIO1A6_UART1CTSN_SPI0CLK_NAME "gpio1a6_uart1ctsn_spi0clk_name" +#define GPIO1A7_UART1RTSN_SPI0CSN0_NAME "gpio1a7_uart1rtsn_spi0csn0_name" + +//GPIO1B +#define GPIO1B0_UART2SIN_JTAGTDI_NAME "gpio1b0_uart2sin_jtagtdi_name" +#define GPIO1B1_UART2SOUT_JTAGTDO_NAME "gpio1b1_uart2sout_jtagtdo_name" +#define GPIO1B2_UART3SIN_GPSMAG_NAME "gpio1b2_uart3sin_gpsmag_name" +#define GPIO1B3_UART3SOUT_GPSSIG_NAME "gpio1b3_uart3sout_gpssig_name" +#define GPIO1B4_UART3CTSN_GPSRFCLK_NAME "gpio1b4_uart3ctsn_gpsrfclk_name" +#define GPIO1B5_UART3RTSN_NAME "gpio1b5_uart3rtsn_name" +#define GPIO1B6_SPDIFTX_SPI1CSN1_NAME "gpio1b6_spdiftx_spi1csn1_name" +#define GPIO1B7_SPI0CSN1_NAME "gpio1b7_spi0csn1_name" + +//GPIO1C +#define GPIO1C0_I2SCLK_NAME "gpio1c0_i2sclk_name" +#define GPIO1C1_I2SSCLK_NAME "gpio1c1_i2ssclk_name" +#define GPIO1C2_I2SLRCLKRX_NAME "gpio1c2_i2slrclkrx_name" +#define GPIO1C3_I2SLRCLKTX_NAME "gpio1c3_i2slrclktx_name" +#define GPIO1C4_I2SSDI_NAME "gpio1c4_i2ssdi_name" +#define GPIO1C5_I2SSDO_NAME "gpio1c5_i2ssdo_name" + +//GPIO1D +#define GPIO1D0_I2C0SDA_NAME "gpio1d0_i2c0sda_name" +#define GPIO1D1_I2C0SCL_NAME "gpio1d1_i2c0scl_name" +#define GPIO1D2_I2C1SDA_NAME "gpio1d2_i2c1sda_name" +#define GPIO1D3_I2C1SCL_NAME "gpio1d3_i2c1scl_name" +#define GPIO1D4_I2C2SDA_NAME "gpio1d4_i2c2sda_name" +#define GPIO1D5_I2C2SCL_NAME "gpio1d5_i2c2scl_name" +#define GPIO1D6_I2C4SDA_NAME "gpio1d6_i2c4sda_name" +#define GPIO1D7_I2C4SCL_NAME "gpio1d7_i2c4scl_name" + +//GPIO2A +#define GPIO2A0_LCDC1DATA0_SMCDATA0_TRACEDATA0_NAME "gpio2a0_lcdc1data0_smcdata0_tracedata0_name" +#define GPIO2A1_LCDC1DATA1_SMCDATA1_TRACEDATA1_NAME "gpio2a1_lcdc1data1_smcdata1_tracedata1_name" +#define GPIO2A2_LCDC1DATA2_SMCDATA2_TRACEDATA2_NAME "gpio2a2_lcdc1data2_smcdata2_tracedata2_name" +#define GPIO2A3_LCDC1DATA3_SMCDATA3_TRACEDATA3_NAME "gpio2a3_lcdc1data3_smcdata3_tracedata3_name" +#define GPIO2A4_LCDC1DATA4_SMCDATA4_TRACEDATA4_NAME "gpio2a4_lcdc1data4_smcdata4_tracedata4_name" +#define GPIO2A5_LCDC1DATA5_SMCDATA5_TRACEDATA5_NAME "gpio2a5_lcdc1data5_smcdata5_tracedata5_name" +#define GPIO2A6_LCDC1DATA6_SMCDATA6_TRACEDATA6_NAME "gpio2a6_lcdc1data6_smcdata6_tracedata6_name" +#define GPIO2A7_LCDC1DATA7_SMCDATA7_TRACEDATA7_NAME "gpio2a7_lcdc1data7_smcdata7_tracedata7_name" + +//GPIO2B +#define GPIO2B0_LCDC1DATA8_SMCDATA8_TRACEDATA8_NAME "gpio2b0_lcdc1data8_smcdata8_tracedata8_name" +#define GPIO2B1_LCDC1DATA9_SMCDATA9_TRACEDATA9_NAME "gpio2b1_lcdc1data9_smcdata9_tracedata9_name" +#define GPIO2B2_LCDC1DATA10_SMCDATA10_TRACEDATA10_NAME "gpio2b2_lcdc1data10_smcdata10_tracedata10_name" +#define GPIO2B3_LCDC1DATA11_SMCDATA11_TRACEDATA11_NAME "gpio2b3_lcdc1data11_smcdata11_tracedata11_name" +#define GPIO2B4_LCDC1DATA12_SMCDATA12_TRACEDATA12_NAME "gpio2b4_lcdc1data12_smcdata12_tracedata12_name" +#define GPIO2B5_LCDC1DATA13_SMCDATA13_TRACEDATA13_NAME "gpio2b5_lcdc1data13_smcdata13_tracedata13_name" +#define GPIO2B6_LCDC1DATA14_SMCDATA14_TRACEDATA14_NAME "gpio2b6_lcdc1data14_smcdata14_tracedata14_name" +#define GPIO2B7_LCDC1DATA15_SMCDATA15_TRACEDATA15_NAME "gpio2b7_lcdc1data15_smcdata15_tracedata15_name" + +//GPIO2C +#define GPIO2C0_LCDC1DATA16_SMCADDR0_TRACECLK_NAME "gpio2c0_lcdc1data16_smcaddr0_traceclk_name" +#define GPIO2C1_LCDC1DATA17_SMCADDR1_TRACECTL_NAME "gpio2c1_lcdc1data17_smcaddr1_tracectl_name" +#define GPIO2C2_LCDC1DATA18_SMCADDR2_NAME "gpio2c2_lcdc1data18_smcaddr2_name" +#define GPIO2C3_LCDC1DATA19_SMCADDR3_NAME "gpio2c3_lcdc1data19_smcaddr3_name" +#define GPIO2C4_LCDC1DATA20_SMCADDR4_NAME "gpio2c4_lcdc1data20_smcaddr4_name" +#define GPIO2C5_LCDC1DATA21_SMCADDR5_NAME "gpio2c5_lcdc1data21_smcaddr5_name" +#define GPIO2C6_LCDC1DATA22_SMCADDR6_NAME "gpio2c6_lcdc1data22_smcaddr6_name" +#define GPIO2C7_LCDC1DATA23_SMCADDR7_NAME "gpio2c7_lcdc1data23_smcaddr7_name" + +//GPIO2D +#define GPIO2D0_LCDC1DCLK_SMCCSN0_NAME "gpio2d0_lcdc1dclk_smccsn0_name" +#define GPIO2D1_LCDC1DEN_SMCWEN_NAME "gpio2d1_lcdc1den_smcwen_name" +#define GPIO2D2_LCDC1HSYNC_SMCOEN_NAME "gpio2d2_lcdc1hsync_smcoen_name" +#define GPIO2D3_LCDC1VSYNC_SMCADVN_NAME "gpio2d3_lcdc1vsync_smcadvn_name" +#define GPIO2D4_SMCBLSN0_NAME "gpio2d4_smcblsn0_name" +#define GPIO2D5_SMCBLSN1_NAME "gpio2d5_smcblsn1_name" +#define GPIO2D6_SMCCSN1_NAME "gpio2d6_smccsn1_name" +#define GPIO2D7_TESTCLOCKOUT_NAME "gpio2d7_testclockout_name" + +//GPIO3A +#define GPIO3A0_SDMMC0RSTNOUT_NAME "gpio3a0_sdmmc0rstnout_name" +#define GPIO3A1_SDMMC0PWREN_NAME "gpio3a1_sdmmc0pwren_name" +#define GPIO3A2_SDMMC0CLKOUT_NAME "gpio3a2_sdmmc0clkout_name" +#define GPIO3A3_SDMMC0CMD_NAME "gpio3a3_sdmmc0cmd_name" +#define GPIO3A4_SDMMC0DATA0_NAME "gpio3a4_sdmmc0data0_name" +#define GPIO3A5_SDMMC0DATA1_NAME "gpio3a5_sdmmc0data1_name" +#define GPIO3A6_SDMMC0DATA2_NAME "gpio3a6_sdmmc0data2_name" +#define GPIO3A7_SDMMC0DATA3_NAME "gpio3a7_sdmmc0data3_name" + +//GPIO3B +#define GPIO3B0_SDMMC0DETECTN_NAME "gpio3b0_sdmmc0detectn_name" +#define GPIO3B1_SDMMC0WRITEPRT_NAME "gpio3b1_sdmmc0writeprt_name" +#define GPIO3B3_CIFCLKOUT_NAME "gpio3b3_cifclkout_name" +#define GPIO3B4_CIFDATA0_HSADCDATA8_NAME "gpio3b4_cifdata0_hsadcdata8_name" +#define GPIO3B5_CIFDATA1_HSADCDATA9_NAME "gpio3b5_cifdata1_hsadcdata9_name" +#define GPIO3B6_CIFDATA10_I2C3SDA_NAME "gpio3b6_cifdata10_i2c3sda_name" +#define GPIO3B7_CIFDATA11_I2C3SCL_NAME "gpio3b7_cifdata11_i2c3scl_name" + +//GPIO3C +#define GPIO3C0_SDMMC1CMD_RMIITXEN_NAME "gpio3c0_sdmmc1cmd_rmiitxen_name" +#define GPIO3C1_SDMMC1DATA0_RMIITXD1_NAME "gpio3c1_sdmmc1data0_rmiitxd1_name" +#define GPIO3C2_SDMMC1DATA1_RMIITXD0_NAME "gpio3c2_sdmmc1data1_rmiitxd0_name" +#define GPIO3C3_SDMMC1DATA2_RMIIRXD0_NAME "gpio3c3_sdmmc1data2_rmiirxd0_name" +#define GPIO3C4_SDMMC1DATA3_RMIIRXD1_NAME "gpio3c4_sdmmc1data3_rmiirxd1_name" +#define GPIO3C5_SDMMC1CLKOUT_RMIICLKOUT_RMIICLKIN_NAME "gpio3c5_sdmmc1clkout_rmiiclkout_rmiiclkin_name" +#define GPIO3C6_SDMMC1DETECTN_RMIIRXERR_NAME "gpio3c6_sdmmc1detectn_rmiirxerr_name" +#define GPIO3C7_SDMMC1WRITEPRT_RMIICRS_NAME "gpio3c7_sdmmc1writeprt_rmiicrs_name" + +//GPIO3D +#define GPIO3D0_SDMMC1PWREN_MIIMD_NAME "gpio3d0_sdmmc1pwren_miimd_name" +#define GPIO3D1_SDMMC1BACKENDPWR_MIIMDCLK_NAME "gpio3d1_sdmmc1backendpwr_miimdclk_name" +#define GPIO3D2_SDMMC1INTN_NAME "gpio3d2_sdmmc1intn_name" +#define GPIO3D3_PWM0_NAME "gpio3d3_pwm0_name" +#define GPIO3D4_PWM1_JTAGTRSTN_NAME "gpio3d4_pwm1_jtagtrstn_name" +#define GPIO3D5_PWM2_JTAGTCK_OTGDRVVBUS_NAME "gpio3d5_pwm2_jtagtck_otgdrvvbus_name" +#define GPIO3D6_PWM3_JTAGTMS_HOSTDRVVBUS_NAME "gpio3d6_pwm3_jtagtms_hostdrvvbus_name" diff --git a/arch/arm/mach-rk30/include/mach/iomux.h b/arch/arm/mach-rk30/include/mach/iomux.h index 00857dc4c0aa..d5dd631ab4b2 100755 --- a/arch/arm/mach-rk30/include/mach/iomux.h +++ b/arch/arm/mach-rk30/include/mach/iomux.h @@ -1,25 +1,11 @@ -/* - * arch/arm/mach-rk29/include/mach/iomux.h - * - *Copyright (C) 2010 ROCKCHIP, Inc. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __RK29_IOMUX_H__ -#define __RK29_IOMUX_H__ +#ifndef __MACH_IOMUX_H__ +#define __MACH_IOMUX_H__ #include - -#if defined(CONFIG_ARCH_RK30) +#if defined(CONFIG_ARCH_RK3066B) +#include +#elif defined(CONFIG_ARCH_RK30) //GPIO0A #define GPIO0A_GPIO0A7 0 #define GPIO0A_I2S_8CH_SDI 1 @@ -802,541 +788,6 @@ //GPIO6B #define GPIO6B7_TESTCLOCKOUT_NAME "gpio6b7_testclockout_name" - -#elif defined(CONFIG_ARCH_RK31) - -//GPIO0C -#define GPIO0C_GPIO0C0 0 -#define GPIO0C_FLASHDATA8 1 -#define GPIO0C_GPIO0C1 0 -#define GPIO0C_FLASHDATA9 1 -#define GPIO0C_GPIO0C2 0 -#define GPIO0C_FLASHDATA10 1 -#define GPIO0C_GPIO0C3 0 -#define GPIO0C_FLASHDATA11 1 -#define GPIO0C_GPIO0C4 0 -#define GPIO0C_FLASHDATA12 1 -#define GPIO0C_GPIO0C5 0 -#define GPIO0C_FLASHDATA13 1 -#define GPIO0C_GPIO0C6 0 -#define GPIO0C_FLASHDATA14 1 -#define GPIO0C_GPIO0C7 0 -#define GPIO0C_FLASHDATA15 1 - -//GPIO0D -#define GPIO0D_GPIO0D0 0 -#define GPIO0D_FLASHDQS 1 -#define GPIO0D_EMMCCLKOUT 2 -#define GPIO0D_GPIO0D1 0 -#define GPIO0D_FLASHCSN1 1 -#define GPIO0D_GPIO0D2 0 -#define GPIO0D_FLASHCSN2 1 -#define GPIO0D_EMMCCMD 2 -#define GPIO0D_GPIO0D3 0 -#define GPIO0D_FLASHCSN3 1 -#define GPIO0D_EMMCRSTNOUT 2 -#define GPIO0D_GPIO0D4 0 -#define GPIO0D_SPI1RXD 1 -#define GPIO0D_GPIO0D5 0 -#define GPIO0D_SPI1TXD 1 -#define GPIO0D_GPIO0D6 0 -#define GPIO0D_SPI1CLK 1 -#define GPIO0D_GPIO0D7 0 -#define GPIO0D_SPI1CSN0 1 - -//GPIO1A -#define GPIO1A_GPIO1A0 0 -#define GPIO1A_UART0SIN 1 -#define GPIO1A_GPIO1A1 0 -#define GPIO1A_UART0SOUT 1 -#define GPIO1A_GPIO1A2 0 -#define GPIO1A_UART0CTSN 1 -#define GPIO1A_GPIO1A3 0 -#define GPIO1A_UART0RTSN 1 -#define GPIO1A_GPIO1A4 0 -#define GPIO1A_UART1SIN 1 -#define GPIO1A_SPI0RXD 2 -#define GPIO1A_GPIO1A5 0 -#define GPIO1A_UART1SOUT 1 -#define GPIO1A_SPI0TXD 2 -#define GPIO1A_GPIO1A6 0 -#define GPIO1A_UART1CTSN 1 -#define GPIO1A_SPI0CLK 2 -#define GPIO1A_GPIO1A7 0 -#define GPIO1A_UART1RTSN 1 -#define GPIO1A_SPI0CSN0 2 - -//GPIO1B -#define GPIO1B_GPIO1B0 0 -#define GPIO1B_UART2SIN 1 -#define GPIO1B_JTAGTDI 2 -#define GPIO1B_GPIO1B1 0 -#define GPIO1B_UART2SOUT 1 -#define GPIO1B_JTAGTDO 2 -#define GPIO1B_GPIO1B2 0 -#define GPIO1B_UART3SIN 1 -#define GPIO1B_GPSMAG 2 -#define GPIO1B_GPIO1B3 0 -#define GPIO1B_UART3SOUT 1 -#define GPIO1B_GPSSIG 2 -#define GPIO1B_GPIO1B4 0 -#define GPIO1B_UART3CTSN 1 -#define GPIO1B_GPSRFCLK 2 -#define GPIO1B_GPIO1B5 0 -#define GPIO1B_UART3RTSN 1 -#define GPIO1B_GPIO1B6 0 -#define GPIO1B_SPDIFTX 1 -#define GPIO1B_SPI1CSN1 2 -#define GPIO1B_GPIO1B7 0 -#define GPIO1B_SPI0CSN1 1 - -//GPIO1C -#define GPIO1C_GPIO1C0 0 -#define GPIO1C_I2SCLK 1 -#define GPIO1C_GPIO1C1 0 -#define GPIO1C_I2SSCLK 1 -#define GPIO1C_GPIO1C2 0 -#define GPIO1C_I2SLRCLKRX 1 -#define GPIO1C_GPIO1C3 0 -#define GPIO1C_I2SLRCLKTX 1 -#define GPIO1C_GPIO1C4 0 -#define GPIO1C_I2SSDI 1 -#define GPIO1C_GPIO1C5 0 -#define GPIO1C_I2SSDO 1 - -//GPIO1D -#define GPIO1D_GPIO1D0 0 -#define GPIO1D_I2C0SDA 1 -#define GPIO1D_GPIO1D1 0 -#define GPIO1D_I2C0SCL 1 -#define GPIO1D_GPIO1D2 0 -#define GPIO1D_I2C1SDA 1 -#define GPIO1D_GPIO1D3 0 -#define GPIO1D_I2C1SCL 1 -#define GPIO1D_GPIO1D4 0 -#define GPIO1D_I2C2SDA 1 -#define GPIO1D_GPIO1D5 0 -#define GPIO1D_I2C2SCL 1 -#define GPIO1D_GPIO1D6 0 -#define GPIO1D_I2C4SDA 1 -#define GPIO1D_GPIO1D7 0 -#define GPIO1D_I2C4SCL 1 - -//GPIO2A -#define GPIO2A_GPIO2A0 0 -#define GPIO2A_LCDC1DATA0 1 -#define GPIO2A_SMCDATA0 2 -#define GPIO2A_TRACEDATA0 3 -#define GPIO2A_GPIO2A1 0 -#define GPIO2A_LCDC1DATA1 1 -#define GPIO2A_SMCDATA1 2 -#define GPIO2A_TRACEDATA1 3 -#define GPIO2A_GPIO2A2 0 -#define GPIO2A_LCDC1DATA2 1 -#define GPIO2A_SMCDATA2 2 -#define GPIO2A_TRACEDATA2 3 -#define GPIO2A_GPIO2A3 0 -#define GPIO2A_LCDC1DATA3 1 -#define GPIO2A_SMCDATA3 2 -#define GPIO2A_TRACEDATA3 3 -#define GPIO2A_GPIO2A4 0 -#define GPIO2A_LCDC1DATA4 1 -#define GPIO2A_SMCDATA4 2 -#define GPIO2A_TRACEDATA4 3 -#define GPIO2A_GPIO2A5 0 -#define GPIO2A_LCDC1DATA5 1 -#define GPIO2A_SMCDATA5 2 -#define GPIO2A_TRACEDATA5 3 -#define GPIO2A_GPIO2A6 0 -#define GPIO2A_LCDC1DATA6 1 -#define GPIO2A_SMCDATA6 2 -#define GPIO2A_TRACEDATA6 3 -#define GPIO2A_GPIO2A7 0 -#define GPIO2A_LCDC1DATA7 1 -#define GPIO2A_SMCDATA7 2 -#define GPIO2A_TRACEDATA7 3 - -//GPIO2B -#define GPIO2B_GPIO2B0 0 -#define GPIO2B_LCDC1DATA8 1 -#define GPIO2B_SMCDATA8 2 -#define GPIO2B_TRACEDATA8 3 -#define GPIO2B_GPIO2B1 0 -#define GPIO2B_LCDC1DATA9 1 -#define GPIO2B_SMCDATA9 2 -#define GPIO2B_TRACEDATA9 3 -#define GPIO2B_GPIO2B2 0 -#define GPIO2B_LCDC1DATA10 1 -#define GPIO2B_SMCDATA10 2 -#define GPIO2B_TRACEDATA10 3 -#define GPIO2B_GPIO2B3 0 -#define GPIO2B_LCDC1DATA11 1 -#define GPIO2B_SMCDATA11 2 -#define GPIO2B_TRACEDATA11 3 -#define GPIO2B_GPIO2B4 0 -#define GPIO2B_LCDC1DATA12 1 -#define GPIO2B_SMCDATA12 2 -#define GPIO2B_TRACEDATA12 3 -#define GPIO2B_GPIO2B5 0 -#define GPIO2B_LCDC1DATA13 1 -#define GPIO2B_SMCDATA13 2 -#define GPIO2B_TRACEDATA13 3 -#define GPIO2B_GPIO2B6 0 -#define GPIO2B_LCDC1DATA14 1 -#define GPIO2B_SMCDATA14 2 -#define GPIO2B_TRACEDATA14 3 -#define GPIO2B_GPIO2B7 0 -#define GPIO2B_LCDC1DATA15 1 -#define GPIO2B_SMCDATA15 2 -#define GPIO2B_TRACEDATA15 3 - -//GPIO2C -#define GPIO2C_GPIO2C0 0 -#define GPIO2C_LCDC1DATA16 1 -#define GPIO2C_SMCADDR0 2 -#define GPIO2C_GPIO2C1 0 -#define GPIO2C_LCDC1DATA17 1 -#define GPIO2C_SMCADDR1 2 -#define GPIO2C_GPIO2C2 0 -#define GPIO2C_LCDC1DATA18 1 -#define GPIO2C_SMCADDR2 2 -#define GPIO2C_GPIO2C3 0 -#define GPIO2C_LCDC1DATA19 1 -#define GPIO2C_SMCADDR3 2 -#define GPIO2C_GPIO2C4 0 -#define GPIO2C_LCDC1DATA20 1 -#define GPIO2C_SMCADDR4 2 -#define GPIO2C_GPIO2C5 0 -#define GPIO2C_LCDC1DATA21 1 -#define GPIO2C_SMCADDR5 2 -#define GPIO2C_GPIO2C6 0 -#define GPIO2C_LCDC1DATA22 1 -#define GPIO2C_SMCADDR6 2 -#define GPIO2C_GPIO2C7 0 -#define GPIO2C_LCDC1DATA23 1 -#define GPIO2C_SMCADDR7 2 - -//GPIO2D -#define GPIO2D_GPIO2D0 0 -#define GPIO2D_LCDC1DCLK 1 -#define GPIO2D_SMCCSN0 2 -#define GPIO2D_GPIO2D1 0 -#define GPIO2D_LCDC1DEN 1 -#define GPIO2D_SMCWEN 2 -#define GPIO2D_GPIO2D2 0 -#define GPIO2D_LCDC1HSYNC 1 -#define GPIO2D_SMCOEN 2 -#define GPIO2D_GPIO2D3 0 -#define GPIO2D_LCDC1VSYNC 1 -#define GPIO2D_SMCADVN 2 -#define GPIO2D_GPIO2D4 0 -#define GPIO2D_SMCBLSN0 1 -#define GPIO2D_GPIO2D5 0 -#define GPIO2D_SMCBLSN1 1 -#define GPIO2D_GPIO2D6 0 -#define GPIO2D_SMCCSN1 1 -#define GPIO2D_GPIO2D7 0 -#define GPIO2D_TESTCLOCKOUT 1 - -//GPIO3A -#define GPIO3A_GPIO3A0 0 -#define GPIO3A_SDMMC0RSTNOUT 1 -#define GPIO3A_GPIO3A1 0 -#define GPIO3A_SDMMC0PWREN 1 -#define GPIO3A_GPIO3A2 0 -#define GPIO3A_SDMMC0CLKOUT 1 -#define GPIO3A_GPIO3A3 0 -#define GPIO3A_SDMMC0CMD 1 -#define GPIO3A_GPIO3A4 0 -#define GPIO3A_SDMMC0DATA0 1 -#define GPIO3A_GPIO3A5 0 -#define GPIO3A_SDMMC0DATA1 1 -#define GPIO3A_GPIO3A6 0 -#define GPIO3A_SDMMC0DATA2 1 -#define GPIO3A_GPIO3A7 0 -#define GPIO3A_SDMMC0DATA3 1 - -//GPIO3B -#define GPIO3B_GPIO3B0 0 -#define GPIO3B_SDMMC0DETECTN 1 -#define GPIO3B_GPIO3B1 0 -#define GPIO3B_SDMMC0WRITEPRT 1 -#define GPIO3B_GPIO3B3 0 -#define GPIO3B_CIFCLKOUT 1 -#define GPIO3B_GPIO3B4 0 -#define GPIO3B_CIFDATA0 1 -#define GPIO3B_HSADCDATA8 2 -#define GPIO3B_GPIO3B5 0 -#define GPIO3B_CIFDATA1 1 -#define GPIO3B_HSADCDATA9 2 -#define GPIO3B_GPIO3B6 0 -#define GPIO3B_CIFDATA10 1 -#define GPIO3B_I2C3SDA 2 -#define GPIO3B_GPIO3B7 0 -#define GPIO3B_CIFDATA11 1 -#define GPIO3B_I2C3SCL 2 - -//GPIO3C -#define GPIO3C_GPIO3C0 0 -#define GPIO3C_SDMMC1CMD 1 -#define GPIO3C_RMIITXEN 2 -#define GPIO3C_GPIO3C1 0 -#define GPIO3C_SDMMC1DATA0 1 -#define GPIO3C_RMIITXD1 2 -#define GPIO3C_GPIO3C2 0 -#define GPIO3C_SDMMC1DATA1 1 -#define GPIO3C_RMIITXD0 2 -#define GPIO3C_GPIO3C3 0 -#define GPIO3C_SDMMC1DATA2 1 -#define GPIO3C_RMIIRXD0 2 -#define GPIO3C_GPIO3C4 0 -#define GPIO3C_SDMMC1DATA3 1 -#define GPIO3C_RMIIRXD1 2 -#define GPIO3C_GPIO3C5 0 -#define GPIO3C_SDMMC1CLKOUT 1 -#define GPIO3C_RMIICLKOUT 2 -#define GPIO3C_RMIICLKIN 3 -#define GPIO3C_GPIO3C6 0 -#define GPIO3C_SDMMC1DETECTN 1 -#define GPIO3C_RMIIRXERR 2 -#define GPIO3C_GPIO3C7 0 -#define GPIO3C_SDMMC1WRITEPRT 1 -#define GPIO3C_RMIICRS 2 - -//GPIO3D -#define GPIO3D_GPIO3D0 0 -#define GPIO3D_SDMMC1PWREN 1 -#define GPIO3D_MIIMD 2 -#define GPIO3D_GPIO3D1 0 -#define GPIO3D_SDMMC1BACKENPWR 1 -#define GPIO3D_MIIMDCLK 2 -#define GPIO3D_GPIO3D2 0 -#define GPIO3D_SDMMC1INTN 1 -#define GPIO3D_GPIO3D3 0 -#define GPIO3D_PWM0 1 -#define GPIO3D_GPIO3D4 0 -#define GPIO3D_PWM1 1 -#define GPIO3D_JTAGTRSTN 2 -#define GPIO3D_GPIO3D5 0 -#define GPIO3D_PWM2 1 -#define GPIO3D_JTAGTCK 2 -#define GPIO3D_OTGDRVVBUS 3 -#define GPIO3D_GPIO3D6 0 -#define GPIO3D_PWM3 1 -#define GPIO3D_JTAGTMS 2 -#define GPIO3D_HOSTDRVVBUS 3 - -#define GRF_GPIO0L_DIR 0x0000 -#define GRF_GPIO0H_DIR 0x0004 -#define GRF_GPIO1L_DIR 0x0008 -#define GRF_GPIO1H_DIR 0x000c -#define GRF_GPIO2L_DIR 0x0010 -#define GRF_GPIO2H_DIR 0x0014 -#define GRF_GPIO3L_DIR 0x0018 -#define GRF_GPIO3H_DIR 0x001c -#define GRF_GPIO0L_DO 0x0020 -#define GRF_GPIO0H_DO 0x0024 -#define GRF_GPIO1L_DO 0x0028 -#define GRF_GPIO1H_DO 0x002c -#define GRF_GPIO2L_DO 0x0030 -#define GRF_GPIO2H_DO 0x0034 -#define GRF_GPIO3L_DO 0x0038 -#define GRF_GPIO3H_DO 0x003c -#define GRF_GPIO0L_EN 0x0040 -#define GRF_GPIO0H_EN 0x0044 -#define GRF_GPIO1L_EN 0x0048 -#define GRF_GPIO1H_EN 0x004c -#define GRF_GPIO2L_EN 0x0050 -#define GRF_GPIO2H_EN 0x0054 -#define GRF_GPIO3L_EN 0x0058 -#define GRF_GPIO3H_EN 0x005c -#define GRF_GPIO0A_IOMUX RK30_GRF_BASE+0x0060 -#define GRF_GPIO0B_IOMUX RK30_GRF_BASE+0x0064 -#define GRF_GPIO0C_IOMUX RK30_GRF_BASE+0x0068 -#define GRF_GPIO0D_IOMUX RK30_GRF_BASE+0x006c -#define GRF_GPIO1A_IOMUX RK30_GRF_BASE+0x0070 -#define GRF_GPIO1B_IOMUX RK30_GRF_BASE+0x0074 -#define GRF_GPIO1C_IOMUX RK30_GRF_BASE+0x0078 -#define GRF_GPIO1D_IOMUX RK30_GRF_BASE+0x007c -#define GRF_GPIO2A_IOMUX RK30_GRF_BASE+0x0080 -#define GRF_GPIO2B_IOMUX RK30_GRF_BASE+0x0084 -#define GRF_GPIO2C_IOMUX RK30_GRF_BASE+0x0088 -#define GRF_GPIO2D_IOMUX RK30_GRF_BASE+0x008c -#define GRF_GPIO3A_IOMUX RK30_GRF_BASE+0x0090 -#define GRF_GPIO3B_IOMUX RK30_GRF_BASE+0x0094 -#define GRF_GPIO3C_IOMUX RK30_GRF_BASE+0x0098 -#define GRF_GPIO3D_IOMUX RK30_GRF_BASE+0x009c -#define GRF_SOC_CON0 0x00a0 -#define GRF_SOC_CON1 0x00a4 -#define GRF_SOC_CON2 0x00a8 -#define GRF_SOC_STATUS0 0x00ac -#define GRF_DMAC1_CON0 0x00b0 -#define GRF_DMAC1_CON1 0x00b4 -#define GRF_DMAC1_CON2 0x00b8 -#define GRF_DMAC2_CON0 0x00bc -#define GRF_DMAC2_CON1 0x00c0 -#define GRF_DMAC2_CON2 0x00c4 -#define GRF_DMAC2_CON3 0x00c8 -#define GRF_UOC0_CON0 0x010c -#define GRF_UOC0_CON1 0x0110 -#define GRF_UOC0_CON2 0x0114 -#define GRF_UOC0_CON3 0x0118 -#define GRF_UOC1_CON0 0x011c -#define GRF_UOC1_CON1 0x0120 -#define GRF_UOC1_CON2 0x0124 -#define GRF_UOC1_CON3 0x0128 -#define GRF_UOC2_CON0 0x012c -#define GRF_UOC2_CON1 0x0130 -#define GRF_UOC3_CON0 0x0138 -#define GRF_UOC3_CON1 0x013c -#define GRF_HSIC_STAT 0x0140 -#define GRF_DDRC_CON0 0x00ec -#define GRF_DDRC_STAT 0x00f0 -#define GRF_OS_REG0 0x0144 -#define GRF_OS_REG1 0x0148 -#define GRF_OS_REG2 0x014c -#define GRF_OS_REG3 0x0150 -#define GRF_OS_REG4 0x0154 -#define GRF_OS_REG5 0x0158 -#define GRF_OS_REG6 0x015c -#define GRF_OS_REG7 0x0160 - -//GPIO0C -#define GPIO0C0_FLASHDATA8_NAME "gpio0c0_flashdata8_name" -#define GPIO0C1_FLASHDATA9_NAME "gpio0c1_flashdata9_name" -#define GPIO0C2_FLASHDATA10_NAME "gpio0c2_flashdata10_name" -#define GPIO0C3_FLASHDATA11_NAME "gpio0c3_flashdata11_name" -#define GPIO0C4_FLASHDATA12_NAME "gpio0c4_flashdata12_name" -#define GPIO0C5_FLASHDATA13_NAME "gpio0c5_flashdata13_name" -#define GPIO0C6_FLASHDATA14_NAME "gpio0c6_flashdata14_name" -#define GPIO0C7_FLASHDATA15_NAME "gpio0c7_flashdata15_name" - -//GPIO0D -#define GPIO0D0_FLASHDQS_EMMCCLKOUT_NAME "gpio0d0_flashdqs_emmcclkout_name" -#define GPIO0D1_FLASHCSN1_NAME "gpio0d1_flashcsn1_name" -#define GPIO0D2_FLASHCSN2_EMMCCMD_NAME "gpio0d2_flashcsn2_emmccmd_name" -#define GPIO0D3_FLASHCSN3_EMMCRSTNOUT_NAME "gpio0d3_flashcsn3_emmcrstnout_name" -#define GPIO0D4_SPI1RXD_NAME "gpio0d4_spi1rxd_name" -#define GPIO0D5_SPI1TXD_NAME "gpio0d5_spi1txd_name" -#define GPIO0D6_SPI1CLK_NAME "gpio0d6_spi1clk_name" -#define GPIO0D7_SPI1CSN0_NAME "gpio0d7_spi1csn0_name" - -//GPIO1A -#define GPIO1A0_UART0SIN_NAME "gpio1a0_uart0sin_name" -#define GPIO1A1_UART0SOUT_NAME "gpio1a1_uart0sout_name" -#define GPIO1A2_UART0CTSN_NAME "gpio1a2_uart0ctsn_name" -#define GPIO1A3_UART0RTSN_NAME "gpio1a3_uart0rtsn_name" -#define GPIO1A4_UART1SIN_SPI0RXD_NAME "gpio1a4_uart1sin_spi0rxd_name" -#define GPIO1A5_UART1SOUT_SPI0TXD_NAME "gpio1a5_uart1sout_spi0txd_name" -#define GPIO1A6_UART1CTSN_SPI0CLK_NAME "gpio1a6_uart1ctsn_spi0clk_name" -#define GPIO1A7_UART1RTSN_SPI0CSN0_NAME "gpio1a7_uart1rtsn_spi0csn0_name" - -//GPIO1B -#define GPIO1B0_UART2SIN_JTAGTDI_NAME "gpio1b0_uart2sin_jtagtdi_name" -#define GPIO1B1_UART2SOUT_JTAGTDO_NAME "gpio1b1_uart2sout_jtagtdo_name" -#define GPIO1B2_UART3SIN_GPSMAG_NAME "gpio1b2_uart3sin_gpsmag_name" -#define GPIO1B3_UART3SOUT_GPSSIG_NAME "gpio1b3_uart3sout_gpssig_name" -#define GPIO1B4_UART3CTSN_GPSRFCLK_NAME "gpio1b4_uart3ctsn_gpsrfclk_name" -#define GPIO1B5_UART3RTSN_NAME "gpio1b5_uart3rtsn_name" -#define GPIO1B6_SPDIFTX_SPI1CSN1_NAME "gpio1b6_spdiftx_spi1csn1_name" -#define GPIO1B7_SPI0CSN1_NAME "gpio1b7_spi0csn1_name" - -//GPIO1C -#define GPIO1C0_I2SCLK_NAME "gpio1c0_i2sclk_name" -#define GPIO1C1_I2SSCLK_NAME "gpio1c1_i2ssclk_name" -#define GPIO1C2_I2SLRCLKRX_NAME "gpio1c2_i2slrclkrx_name" -#define GPIO1C3_I2SLRCLKTX_NAME "gpio1c3_i2slrclktx_name" -#define GPIO1C4_I2SSDI_NAME "gpio1c4_i2ssdi_name" -#define GPIO1C5_I2SSDO_NAME "gpio1c5_i2ssdo_name" - -//GPIO1D -#define GPIO1D0_I2C0SDA_NAME "gpio1d0_i2c0sda_name" -#define GPIO1D1_I2C0SCL_NAME "gpio1d1_i2c0scl_name" -#define GPIO1D2_I2C1SDA_NAME "gpio1d2_i2c1sda_name" -#define GPIO1D3_I2C1SCL_NAME "gpio1d3_i2c1scl_name" -#define GPIO1D4_I2C2SDA_NAME "gpio1d4_i2c2sda_name" -#define GPIO1D5_I2C2SCL_NAME "gpio1d5_i2c2scl_name" -#define GPIO1D6_I2C4SDA_NAME "gpio1d6_i2c4sda_name" -#define GPIO1D7_I2C4SCL_NAME "gpio1d7_i2c4scl_name" - -//GPIO2A -#define GPIO2A0_LCDC1DATA0_SMCDATA0_TRACEDATA0_NAME "gpio2a0_lcdc1data0_smcdata0_tracedata0_name" -#define GPIO2A1_LCDC1DATA1_SMCDATA1_TRACEDATA1_NAME "gpio2a1_lcdc1data1_smcdata1_tracedata1_name" -#define GPIO2A2_LCDC1DATA2_SMCDATA2_TRACEDATA2_NAME "gpio2a2_lcdc1data2_smcdata2_tracedata2_name" -#define GPIO2A3_LCDC1DATA3_SMCDATA3_TRACEDATA3_NAME "gpio2a3_lcdc1data3_smcdata3_tracedata3_name" -#define GPIO2A4_LCDC1DATA4_SMCDATA4_TRACEDATA4_NAME "gpio2a4_lcdc1data4_smcdata4_tracedata4_name" -#define GPIO2A5_LCDC1DATA5_SMCDATA5_TRACEDATA5_NAME "gpio2a5_lcdc1data5_smcdata5_tracedata5_name" -#define GPIO2A6_LCDC1DATA6_SMCDATA6_TRACEDATA6_NAME "gpio2a6_lcdc1data6_smcdata6_tracedata6_name" -#define GPIO2A7_LCDC1DATA7_SMCDATA7_TRACEDATA7_NAME "gpio2a7_lcdc1data7_smcdata7_tracedata7_name" - -//GPIO2B -#define GPIO2B0_LCDC1DATA8_SMCDATA8_TRACEDATA8_NAME "gpio2b0_lcdc1data8_smcdata8_tracedata8_name" -#define GPIO2B1_LCDC1DATA9_SMCDATA9_TRACEDATA9_NAME "gpio2b1_lcdc1data9_smcdata9_tracedata9_name" -#define GPIO2B2_LCDC1DATA10_SMCDATA10_TRACEDATA10_NAME "gpio2b2_lcdc1data10_smcdata10_tracedata10_name" -#define GPIO2B3_LCDC1DATA11_SMCDATA11_TRACEDATA11_NAME "gpio2b3_lcdc1data11_smcdata11_tracedata11_name" -#define GPIO2B4_LCDC1DATA12_SMCDATA12_TRACEDATA12_NAME "gpio2b4_lcdc1data12_smcdata12_tracedata12_name" -#define GPIO2B5_LCDC1DATA13_SMCDATA13_TRACEDATA13_NAME "gpio2b5_lcdc1data13_smcdata13_tracedata13_name" -#define GPIO2B6_LCDC1DATA14_SMCDATA14_TRACEDATA14_NAME "gpio2b6_lcdc1data14_smcdata14_tracedata14_name" -#define GPIO2B7_LCDC1DATA15_SMCDATA15_TRACEDATA15_NAME "gpio2b7_lcdc1data15_smcdata15_tracedata15_name" - -//GPIO2C -#define GPIO2C0_LCDC1DATA16_SMCADDR0_TRACECLK_NAME "gpio2c0_lcdc1data16_smcaddr0_traceclk_name" -#define GPIO2C1_LCDC1DATA17_SMCADDR1_TRACECTL_NAME "gpio2c1_lcdc1data17_smcaddr1_tracectl_name" -#define GPIO2C2_LCDC1DATA18_SMCADDR2_NAME "gpio2c2_lcdc1data18_smcaddr2_name" -#define GPIO2C3_LCDC1DATA19_SMCADDR3_NAME "gpio2c3_lcdc1data19_smcaddr3_name" -#define GPIO2C4_LCDC1DATA20_SMCADDR4_NAME "gpio2c4_lcdc1data20_smcaddr4_name" -#define GPIO2C5_LCDC1DATA21_SMCADDR5_NAME "gpio2c5_lcdc1data21_smcaddr5_name" -#define GPIO2C6_LCDC1DATA22_SMCADDR6_NAME "gpio2c6_lcdc1data22_smcaddr6_name" -#define GPIO2C7_LCDC1DATA23_SMCADDR7_NAME "gpio2c7_lcdc1data23_smcaddr7_name" - -//GPIO2D -#define GPIO2D0_LCDC1DCLK_SMCCSN0_NAME "gpio2d0_lcdc1dclk_smccsn0_name" -#define GPIO2D1_LCDC1DEN_SMCWEN_NAME "gpio2d1_lcdc1den_smcwen_name" -#define GPIO2D2_LCDC1HSYNC_SMCOEN_NAME "gpio2d2_lcdc1hsync_smcoen_name" -#define GPIO2D3_LCDC1VSYNC_SMCADVN_NAME "gpio2d3_lcdc1vsync_smcadvn_name" -#define GPIO2D4_SMCBLSN0_NAME "gpio2d4_smcblsn0_name" -#define GPIO2D5_SMCBLSN1_NAME "gpio2d5_smcblsn1_name" -#define GPIO2D6_SMCCSN1_NAME "gpio2d6_smccsn1_name" -#define GPIO2D7_TESTCLOCKOUT_NAME "gpio2d7_testclockout_name" - -//GPIO3A -#define GPIO3A0_SDMMC0RSTNOUT_NAME "gpio3a0_sdmmc0rstnout_name" -#define GPIO3A1_SDMMC0PWREN_NAME "gpio3a1_sdmmc0pwren_name" -#define GPIO3A2_SDMMC0CLKOUT_NAME "gpio3a2_sdmmc0clkout_name" -#define GPIO3A3_SDMMC0CMD_NAME "gpio3a3_sdmmc0cmd_name" -#define GPIO3A4_SDMMC0DATA0_NAME "gpio3a4_sdmmc0data0_name" -#define GPIO3A5_SDMMC0DATA1_NAME "gpio3a5_sdmmc0data1_name" -#define GPIO3A6_SDMMC0DATA2_NAME "gpio3a6_sdmmc0data2_name" -#define GPIO3A7_SDMMC0DATA3_NAME "gpio3a7_sdmmc0data3_name" - -//GPIO3B -#define GPIO3B0_SDMMC0DETECTN_NAME "gpio3b0_sdmmc0detectn_name" -#define GPIO3B1_SDMMC0WRITEPRT_NAME "gpio3b1_sdmmc0writeprt_name" -#define GPIO3B3_CIFCLKOUT_NAME "gpio3b3_cifclkout_name" -#define GPIO3B4_CIFDATA0_HSADCDATA8_NAME "gpio3b4_cifdata0_hsadcdata8_name" -#define GPIO3B5_CIFDATA1_HSADCDATA9_NAME "gpio3b5_cifdata1_hsadcdata9_name" -#define GPIO3B6_CIFDATA10_I2C3SDA_NAME "gpio3b6_cifdata10_i2c3sda_name" -#define GPIO3B7_CIFDATA11_I2C3SCL_NAME "gpio3b7_cifdata11_i2c3scl_name" - -//GPIO3C -#define GPIO3C0_SDMMC1CMD_RMIITXEN_NAME "gpio3c0_sdmmc1cmd_rmiitxen_name" -#define GPIO3C1_SDMMC1DATA0_RMIITXD1_NAME "gpio3c1_sdmmc1data0_rmiitxd1_name" -#define GPIO3C2_SDMMC1DATA1_RMIITXD0_NAME "gpio3c2_sdmmc1data1_rmiitxd0_name" -#define GPIO3C3_SDMMC1DATA2_RMIIRXD0_NAME "gpio3c3_sdmmc1data2_rmiirxd0_name" -#define GPIO3C4_SDMMC1DATA3_RMIIRXD1_NAME "gpio3c4_sdmmc1data3_rmiirxd1_name" -#define GPIO3C5_SDMMC1CLKOUT_RMIICLKOUT_RMIICLKIN_NAME "gpio3c5_sdmmc1clkout_rmiiclkout_rmiiclkin_name" -#define GPIO3C6_SDMMC1DETECTN_RMIIRXERR_NAME "gpio3c6_sdmmc1detectn_rmiirxerr_name" -#define GPIO3C7_SDMMC1WRITEPRT_RMIICRS_NAME "gpio3c7_sdmmc1writeprt_rmiicrs_name" - -//GPIO3D -#define GPIO3D0_SDMMC1PWREN_MIIMD_NAME "gpio3d0_sdmmc1pwren_miimd_name" -#define GPIO3D1_SDMMC1BACKENDPWR_MIIMDCLK_NAME "gpio3d1_sdmmc1backendpwr_miimdclk_name" -#define GPIO3D2_SDMMC1INTN_NAME "gpio3d2_sdmmc1intn_name" -#define GPIO3D3_PWM0_NAME "gpio3d3_pwm0_name" -#define GPIO3D4_PWM1_JTAGTRSTN_NAME "gpio3d4_pwm1_jtagtrstn_name" -#define GPIO3D5_PWM2_JTAGTCK_OTGDRVVBUS_NAME "gpio3d5_pwm2_jtagtck_otgdrvvbus_name" -#define GPIO3D6_PWM3_JTAGTMS_HOSTDRVVBUS_NAME "gpio3d6_pwm3_jtagtms_hostdrvvbus_name" - #endif #define DEFAULT 0 diff --git a/arch/arm/mach-rk30/include/mach/rk30_camera.h b/arch/arm/mach-rk30/include/mach/rk30_camera.h index b8539fe86357..7cc7cb23e2d0 100755 --- a/arch/arm/mach-rk30/include/mach/rk30_camera.h +++ b/arch/arm/mach-rk30/include/mach/rk30_camera.h @@ -21,18 +21,16 @@ #ifndef __ASM_ARCH_CAMERA_RK30_H_ #define __ASM_ARCH_CAMERA_RK30_H_ -#ifdef CONFIG_ARCH_RK30 +#if defined(CONFIG_ARCH_RK3066B) +#define RK29_CAM_DRV_NAME "rk-camera-rk3066b" +#define RK_SUPPORT_CIF0 1 +#define RK_SUPPORT_CIF1 0 +#elif defined(CONFIG_ARCH_RK30) #define RK29_CAM_DRV_NAME "rk-camera-rk30" #define RK_SUPPORT_CIF0 1 #define RK_SUPPORT_CIF1 1 #endif -#ifdef CONFIG_ARCH_RK31 -#define RK29_CAM_DRV_NAME "rk-camera-rk31" -#define RK_SUPPORT_CIF0 1 -#define RK_SUPPORT_CIF1 0 -#endif - #include #define CONFIG_CAMERA_SCALE_CROP_MACHINE RK_CAM_SCALE_CROP_IPP diff --git a/arch/arm/mach-rk30/iomux-rk3066b.c b/arch/arm/mach-rk30/iomux-rk3066b.c new file mode 100755 index 000000000000..00673576939e --- /dev/null +++ b/arch/arm/mach-rk30/iomux-rk3066b.c @@ -0,0 +1,147 @@ +static struct mux_config rk30_muxs[] = { +/* + * description mux mode mux mux + * reg offset inter mode + */ + +//GPIO0C +MUX_CFG(GPIO0C7_FLASHDATA15_NAME, GPIO0C, 14, 1, 0, DEFAULT) +MUX_CFG(GPIO0C6_FLASHDATA14_NAME, GPIO0C, 12, 1, 0, DEFAULT) +MUX_CFG(GPIO0C5_FLASHDATA13_NAME, GPIO0C, 10, 1, 0, DEFAULT) +MUX_CFG(GPIO0C4_FLASHDATA12_NAME, GPIO0C, 8, 1, 0, DEFAULT) +MUX_CFG(GPIO0C3_FLASHDATA11_NAME, GPIO0C, 6, 1, 0, DEFAULT) +MUX_CFG(GPIO0C2_FLASHDATA10_NAME, GPIO0C, 4, 1, 0, DEFAULT) +MUX_CFG(GPIO0C1_FLASHDATA9_NAME, GPIO0C, 2, 1, 0, DEFAULT) +MUX_CFG(GPIO0C0_FLASHDATA8_NAME, GPIO0C, 0, 1, 0, DEFAULT) + +//GPIO0D +MUX_CFG(GPIO0D7_SPI1CSN0_NAME, GPIO0D, 14, 1, 0, DEFAULT) +MUX_CFG(GPIO0D6_SPI1CLK_NAME, GPIO0D, 12, 1, 0, DEFAULT) +MUX_CFG(GPIO0D5_SPI1TXD_NAME, GPIO0D, 10, 1, 0, DEFAULT) +MUX_CFG(GPIO0D4_SPI1RXD_NAME, GPIO0D, 8, 1, 0, DEFAULT) +MUX_CFG(GPIO0D3_FLASHCSN3_EMMCRSTNOUT_NAME, GPIO0D, 6, 2, 0, DEFAULT) +MUX_CFG(GPIO0D2_FLASHCSN2_EMMCCMD_NAME, GPIO0D, 4, 2, 0, DEFAULT) +MUX_CFG(GPIO0D1_FLASHCSN1_NAME, GPIO0D, 2, 2, 0, DEFAULT) +MUX_CFG(GPIO0D0_FLASHDQS_EMMCCLKOUT_NAME, GPIO0D, 0, 2, 0, DEFAULT) + +//GPIO1A +MUX_CFG(GPIO1A7_UART1RTSN_SPI0CSN0_NAME, GPIO1A, 14, 2, 0, DEFAULT) +MUX_CFG(GPIO1A6_UART1CTSN_SPI0CLK_NAME, GPIO1A, 12, 2, 0, DEFAULT) +MUX_CFG(GPIO1A5_UART1SOUT_SPI0TXD_NAME, GPIO1A, 10, 2, 0, DEFAULT) +MUX_CFG(GPIO1A4_UART1SIN_SPI0RXD_NAME, GPIO1A, 8, 2, 0, DEFAULT) +MUX_CFG(GPIO1A3_UART0RTSN_NAME, GPIO1A, 6, 1, 0, DEFAULT) +MUX_CFG(GPIO1A2_UART0CTSN_NAME, GPIO1A, 4, 1, 0, DEFAULT) +MUX_CFG(GPIO1A1_UART0SOUT_NAME, GPIO1A, 2, 1, 0, DEFAULT) +MUX_CFG(GPIO1A0_UART0SIN_NAME, GPIO1A, 0, 1, 0, DEFAULT) + +//GPIO1B +MUX_CFG(GPIO1B7_SPI0CSN1_NAME, GPIO1B, 14, 1, 0, DEFAULT) +MUX_CFG(GPIO1B6_SPDIFTX_SPI1CSN1_NAME, GPIO1B, 12, 2, 0, DEFAULT) +MUX_CFG(GPIO1B5_UART3RTSN_NAME, GPIO1B, 10, 2, 0, DEFAULT) +MUX_CFG(GPIO1B4_UART3CTSN_GPSRFCLK_NAME, GPIO1B, 8, 2, 0, DEFAULT) +MUX_CFG(GPIO1B3_UART3SOUT_GPSSIG_NAME, GPIO1B, 6, 2, 0, DEFAULT) +MUX_CFG(GPIO1B2_UART3SIN_GPSMAG_NAME, GPIO1B, 4, 2, 0, DEFAULT) +MUX_CFG(GPIO1B1_UART2SOUT_JTAGTDO_NAME, GPIO1B, 2, 2, 0, DEFAULT) +MUX_CFG(GPIO1B0_UART2SIN_JTAGTDI_NAME, GPIO1B, 0, 2, 0, DEFAULT) + +//GPIO1C +MUX_CFG(GPIO1C5_I2SSDO_NAME, GPIO1C, 10, 1, 0, DEFAULT) +MUX_CFG(GPIO1C4_I2SSDI_NAME, GPIO1C, 8, 1, 0, DEFAULT) +MUX_CFG(GPIO1C3_I2SLRCLKTX_NAME, GPIO1C, 6, 1, 0, DEFAULT) +MUX_CFG(GPIO1C2_I2SLRCLKRX_NAME, GPIO1C, 4, 1, 0, DEFAULT) +MUX_CFG(GPIO1C1_I2SSCLK_NAME, GPIO1C, 2, 1, 0, DEFAULT) +MUX_CFG(GPIO1C0_I2SCLK_NAME, GPIO1C, 0, 1, 0, DEFAULT) + +//GPIO1D +MUX_CFG(GPIO1D7_I2C4SCL_NAME, GPIO1D, 14, 1, 0, DEFAULT) +MUX_CFG(GPIO1D6_I2C4SDA_NAME, GPIO1D, 12, 1, 0, DEFAULT) +MUX_CFG(GPIO1D5_I2C2SCL_NAME, GPIO1D, 10, 1, 0, DEFAULT) +MUX_CFG(GPIO1D4_I2C2SDA_NAME, GPIO1D, 8, 1, 0, DEFAULT) +MUX_CFG(GPIO1D3_I2C1SCL_NAME, GPIO1D, 6, 1, 0, DEFAULT) +MUX_CFG(GPIO1D2_I2C1SDA_NAME, GPIO1D, 4, 1, 0, DEFAULT) +MUX_CFG(GPIO1D1_I2C0SCL_NAME, GPIO1D, 2, 1, 0, DEFAULT) +MUX_CFG(GPIO1D0_I2C0SDA_NAME, GPIO1D, 0, 1, 0, DEFAULT) + +//GPIO2A +MUX_CFG(GPIO2A7_LCDC1DATA7_SMCDATA7_TRACEDATA7_NAME, GPIO2A, 14, 2, 0, DEFAULT) +MUX_CFG(GPIO2A6_LCDC1DATA6_SMCDATA6_TRACEDATA6_NAME, GPIO2A, 12, 2, 0, DEFAULT) +MUX_CFG(GPIO2A5_LCDC1DATA5_SMCDATA5_TRACEDATA5_NAME, GPIO2A, 10, 2, 0, DEFAULT) +MUX_CFG(GPIO2A4_LCDC1DATA4_SMCDATA4_TRACEDATA4_NAME, GPIO2A, 8, 2, 0, DEFAULT) +MUX_CFG(GPIO2A3_LCDC1DATA3_SMCDATA3_TRACEDATA3_NAME, GPIO2A, 6, 2, 0, DEFAULT) +MUX_CFG(GPIO2A2_LCDC1DATA2_SMCDATA2_TRACEDATA2_NAME, GPIO2A, 4, 2, 0, DEFAULT) +MUX_CFG(GPIO2A1_LCDC1DATA1_SMCDATA1_TRACEDATA1_NAME, GPIO2A, 2, 2, 0, DEFAULT) +MUX_CFG(GPIO2A0_LCDC1DATA0_SMCDATA0_TRACEDATA0_NAME, GPIO2A, 0, 2, 0, DEFAULT) + +//GPIO2B +MUX_CFG(GPIO2B7_LCDC1DATA15_SMCDATA15_TRACEDATA15_NAME, GPIO2B, 14, 2, 0, DEFAULT) +MUX_CFG(GPIO2B6_LCDC1DATA14_SMCDATA14_TRACEDATA14_NAME, GPIO2B, 12, 2, 0, DEFAULT) +MUX_CFG(GPIO2B5_LCDC1DATA13_SMCDATA13_TRACEDATA13_NAME, GPIO2B, 10, 2, 0, DEFAULT) +MUX_CFG(GPIO2B4_LCDC1DATA12_SMCDATA12_TRACEDATA12_NAME, GPIO2B, 8, 2, 0, DEFAULT) +MUX_CFG(GPIO2B3_LCDC1DATA11_SMCDATA11_TRACEDATA11_NAME, GPIO2B, 6, 2, 0, DEFAULT) +MUX_CFG(GPIO2B2_LCDC1DATA10_SMCDATA10_TRACEDATA10_NAME, GPIO2B, 4, 2, 0, DEFAULT) +MUX_CFG(GPIO2B1_LCDC1DATA9_SMCDATA9_TRACEDATA9_NAME, GPIO2B, 2, 2, 0, DEFAULT) +MUX_CFG(GPIO2B0_LCDC1DATA8_SMCDATA8_TRACEDATA8_NAME, GPIO2B, 0, 2, 0, DEFAULT) + +//GPIO2C +MUX_CFG(GPIO2C7_LCDC1DATA23_SMCADDR7_NAME, GPIO2C, 14, 2, 0, DEFAULT) +MUX_CFG(GPIO2C6_LCDC1DATA22_SMCADDR6_NAME, GPIO2C, 12, 2, 0, DEFAULT) +MUX_CFG(GPIO2C5_LCDC1DATA21_SMCADDR5_NAME, GPIO2C, 10, 2, 0, DEFAULT) +MUX_CFG(GPIO2C4_LCDC1DATA20_SMCADDR4_NAME, GPIO2C, 8, 2, 0, DEFAULT) +MUX_CFG(GPIO2C3_LCDC1DATA19_SMCADDR3_NAME, GPIO2C, 6, 2, 0, DEFAULT) +MUX_CFG(GPIO2C2_LCDC1DATA18_SMCADDR2_NAME, GPIO2C, 4, 2, 0, DEFAULT) +MUX_CFG(GPIO2C1_LCDC1DATA17_SMCADDR1_TRACECTL_NAME, GPIO2C, 2, 2, 0, DEFAULT) +MUX_CFG(GPIO2C0_LCDC1DATA16_SMCADDR0_TRACECLK_NAME, GPIO2C, 0, 2, 0, DEFAULT) + +//GPIO2D +MUX_CFG(GPIO2D7_TESTCLOCKOUT_NAME, GPIO2D, 14, 1, 0, DEFAULT) +MUX_CFG(GPIO2D6_SMCCSN1_NAME, GPIO2D, 12, 1, 0, DEFAULT) +MUX_CFG(GPIO2D5_SMCBLSN1_NAME, GPIO2D, 10, 1, 0, DEFAULT) +MUX_CFG(GPIO2D4_SMCBLSN0_NAME, GPIO2D, 8, 1, 0, DEFAULT) +MUX_CFG(GPIO2D3_LCDC1VSYNC_SMCADVN_NAME, GPIO2D, 6, 2, 0, DEFAULT) +MUX_CFG(GPIO2D2_LCDC1HSYNC_SMCOEN_NAME, GPIO2D, 4, 2, 0, DEFAULT) +MUX_CFG(GPIO2D1_LCDC1DEN_SMCWEN_NAME, GPIO2D, 2, 2, 0, DEFAULT) +MUX_CFG(GPIO2D0_LCDC1DCLK_SMCCSN0_NAME, GPIO2D, 0, 2, 0, DEFAULT) + +//GPIO3A +MUX_CFG(GPIO3A7_SDMMC0DATA3_NAME, GPIO3A, 14, 1, 0, DEFAULT) +MUX_CFG(GPIO3A6_SDMMC0DATA2_NAME, GPIO3A, 12, 1, 0, DEFAULT) +MUX_CFG(GPIO3A5_SDMMC0DATA1_NAME, GPIO3A, 10, 1, 0, DEFAULT) +MUX_CFG(GPIO3A4_SDMMC0DATA0_NAME, GPIO3A, 8, 1, 0, DEFAULT) +MUX_CFG(GPIO3A3_SDMMC0CMD_NAME, GPIO3A, 6, 1, 0, DEFAULT) +MUX_CFG(GPIO3A2_SDMMC0CLKOUT_NAME, GPIO3A, 4, 1, 0, DEFAULT) +MUX_CFG(GPIO3A1_SDMMC0PWREN_NAME, GPIO3A, 2, 1, 0, DEFAULT) +MUX_CFG(GPIO3A0_SDMMC0RSTNOUT_NAME, GPIO3A, 0, 1, 0, DEFAULT) + +//GPIO3B +MUX_CFG(GPIO3B7_CIFDATA11_I2C3SCL_NAME, GPIO3B, 14, 2, 0, DEFAULT) +MUX_CFG(GPIO3B6_CIFDATA10_I2C3SDA_NAME, GPIO3B, 12, 2, 0, DEFAULT) +MUX_CFG(GPIO3B5_CIFDATA1_HSADCDATA9_NAME, GPIO3B, 10, 2, 0, DEFAULT) +MUX_CFG(GPIO3B4_CIFDATA0_HSADCDATA8_NAME, GPIO3B, 8, 2, 0, DEFAULT) +MUX_CFG(GPIO3B3_CIFCLKOUT_NAME, GPIO3B, 6, 1, 0, DEFAULT) +MUX_CFG(GPIO3B1_SDMMC0WRITEPRT_NAME, GPIO3B, 2, 1, 0, DEFAULT) +MUX_CFG(GPIO3B0_SDMMC0DETECTN_NAME, GPIO3B, 0, 1, 0, DEFAULT) + +//GPIO3C +MUX_CFG(GPIO3C7_SDMMC1WRITEPRT_RMIICRS_NAME, GPIO3C, 14, 2, 0, DEFAULT) +MUX_CFG(GPIO3C6_SDMMC1DETECTN_RMIIRXERR_NAME, GPIO3C, 12, 2, 0, DEFAULT) +MUX_CFG(GPIO3C5_SDMMC1CLKOUT_RMIICLKOUT_RMIICLKIN_NAME, GPIO3C, 10, 2, 0, DEFAULT) +MUX_CFG(GPIO3C4_SDMMC1DATA3_RMIIRXD1_NAME, GPIO3C, 8, 2, 0, DEFAULT) +MUX_CFG(GPIO3C3_SDMMC1DATA2_RMIIRXD0_NAME, GPIO3C, 6, 2, 0, DEFAULT) +MUX_CFG(GPIO3C2_SDMMC1DATA1_RMIITXD0_NAME, GPIO3C, 4, 2, 0, DEFAULT) +MUX_CFG(GPIO3C1_SDMMC1DATA0_RMIITXD1_NAME, GPIO3C, 2, 2, 0, DEFAULT) +MUX_CFG(GPIO3C0_SDMMC1CMD_RMIITXEN_NAME, GPIO3C, 0, 2, 0, DEFAULT) + +//GPIO3D +MUX_CFG(GPIO3D6_PWM3_JTAGTMS_HOSTDRVVBUS_NAME, GPIO3D, 12, 2, 0, DEFAULT) +MUX_CFG(GPIO3D5_PWM2_JTAGTCK_OTGDRVVBUS_NAME, GPIO3D, 10, 2, 0, DEFAULT) +MUX_CFG(GPIO3D4_PWM1_JTAGTRSTN_NAME, GPIO3D, 8, 2, 0, DEFAULT) +MUX_CFG(GPIO3D3_PWM0_NAME, GPIO3D, 6, 1, 0, DEFAULT) +MUX_CFG(GPIO3D2_SDMMC1INTN_NAME, GPIO3D, 4, 1, 0, DEFAULT) +MUX_CFG(GPIO3D1_SDMMC1BACKENDPWR_MIIMDCLK_NAME, GPIO3D, 2, 2, 0, DEFAULT) +MUX_CFG(GPIO3D0_SDMMC1PWREN_MIIMD_NAME, GPIO3D, 0, 2, 0, DEFAULT) +}; + +static int __init rk3066b_iomux_init(void) +{ + return 0; +} diff --git a/arch/arm/mach-rk30/iomux.c b/arch/arm/mach-rk30/iomux.c index c38cc27660c2..4a11c438c533 100755 --- a/arch/arm/mach-rk30/iomux.c +++ b/arch/arm/mach-rk30/iomux.c @@ -1,7 +1,5 @@ /* - * arch/arm/mach-rk29/iomux.c - * - *Copyright (C) 2010 ROCKCHIP, Inc. + * Copyright (C) 2012 ROCKCHIP, Inc. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and @@ -24,12 +22,14 @@ //#define IOMUX_DBG +#if defined(CONFIG_ARCH_RK3066B) +#include "iomux-rk3066b.c" +#else static struct mux_config rk30_muxs[] = { /* * description mux mode mux mux * reg offset inter mode */ -#if defined(CONFIG_ARCH_RK30) //GPIO0A MUX_CFG(GPIO0A7_I2S8CHSDI_NAME, GPIO0A, 14, 1, 0, DEFAULT) MUX_CFG(GPIO0A6_HOSTDRVVBUS_NAME, GPIO0A, 12, 1, 0, DEFAULT) @@ -233,146 +233,8 @@ MUX_CFG(GPIO4D0_SMCDATA8_TRACEDATA8_NAME, GPIO4D, 0, 2, 0, DEFAULT) //GPIO6B MUX_CFG(GPIO6B7_TESTCLOCKOUT_NAME, GPIO6B, 14, 1, 0, DEFAULT) -#elif defined(CONFIG_ARCH_RK31) - -//GPIO0C -MUX_CFG(GPIO0C7_FLASHDATA15_NAME, GPIO0C, 14, 1, 0, DEFAULT) -MUX_CFG(GPIO0C6_FLASHDATA14_NAME, GPIO0C, 12, 1, 0, DEFAULT) -MUX_CFG(GPIO0C5_FLASHDATA13_NAME, GPIO0C, 10, 1, 0, DEFAULT) -MUX_CFG(GPIO0C4_FLASHDATA12_NAME, GPIO0C, 8, 1, 0, DEFAULT) -MUX_CFG(GPIO0C3_FLASHDATA11_NAME, GPIO0C, 6, 1, 0, DEFAULT) -MUX_CFG(GPIO0C2_FLASHDATA10_NAME, GPIO0C, 4, 1, 0, DEFAULT) -MUX_CFG(GPIO0C1_FLASHDATA9_NAME, GPIO0C, 2, 1, 0, DEFAULT) -MUX_CFG(GPIO0C0_FLASHDATA8_NAME, GPIO0C, 0, 1, 0, DEFAULT) - -//GPIO0D -MUX_CFG(GPIO0D7_SPI1CSN0_NAME, GPIO0D, 14, 1, 0, DEFAULT) -MUX_CFG(GPIO0D6_SPI1CLK_NAME, GPIO0D, 12, 1, 0, DEFAULT) -MUX_CFG(GPIO0D5_SPI1TXD_NAME, GPIO0D, 10, 1, 0, DEFAULT) -MUX_CFG(GPIO0D4_SPI1RXD_NAME, GPIO0D, 8, 1, 0, DEFAULT) -MUX_CFG(GPIO0D3_FLASHCSN3_EMMCRSTNOUT_NAME, GPIO0D, 6, 2, 0, DEFAULT) -MUX_CFG(GPIO0D2_FLASHCSN2_EMMCCMD_NAME, GPIO0D, 4, 2, 0, DEFAULT) -MUX_CFG(GPIO0D1_FLASHCSN1_NAME, GPIO0D, 2, 2, 0, DEFAULT) -MUX_CFG(GPIO0D0_FLASHDQS_EMMCCLKOUT_NAME, GPIO0D, 0, 2, 0, DEFAULT) - -//GPIO1A -MUX_CFG(GPIO1A7_UART1RTSN_SPI0CSN0_NAME, GPIO1A, 14, 2, 0, DEFAULT) -MUX_CFG(GPIO1A6_UART1CTSN_SPI0CLK_NAME, GPIO1A, 12, 2, 0, DEFAULT) -MUX_CFG(GPIO1A5_UART1SOUT_SPI0TXD_NAME, GPIO1A, 10, 2, 0, DEFAULT) -MUX_CFG(GPIO1A4_UART1SIN_SPI0RXD_NAME, GPIO1A, 8, 2, 0, DEFAULT) -MUX_CFG(GPIO1A3_UART0RTSN_NAME, GPIO1A, 6, 1, 0, DEFAULT) -MUX_CFG(GPIO1A2_UART0CTSN_NAME, GPIO1A, 4, 1, 0, DEFAULT) -MUX_CFG(GPIO1A1_UART0SOUT_NAME, GPIO1A, 2, 1, 0, DEFAULT) -MUX_CFG(GPIO1A0_UART0SIN_NAME, GPIO1A, 0, 1, 0, DEFAULT) - -//GPIO1B -MUX_CFG(GPIO1B7_SPI0CSN1_NAME, GPIO1B, 14, 1, 0, DEFAULT) -MUX_CFG(GPIO1B6_SPDIFTX_SPI1CSN1_NAME, GPIO1B, 12, 2, 0, DEFAULT) -MUX_CFG(GPIO1B5_UART3RTSN_NAME, GPIO1B, 10, 2, 0, DEFAULT) -MUX_CFG(GPIO1B4_UART3CTSN_GPSRFCLK_NAME, GPIO1B, 8, 2, 0, DEFAULT) -MUX_CFG(GPIO1B3_UART3SOUT_GPSSIG_NAME, GPIO1B, 6, 2, 0, DEFAULT) -MUX_CFG(GPIO1B2_UART3SIN_GPSMAG_NAME, GPIO1B, 4, 2, 0, DEFAULT) -MUX_CFG(GPIO1B1_UART2SOUT_JTAGTDO_NAME, GPIO1B, 2, 2, 0, DEFAULT) -MUX_CFG(GPIO1B0_UART2SIN_JTAGTDI_NAME, GPIO1B, 0, 2, 0, DEFAULT) - -//GPIO1C -MUX_CFG(GPIO1C5_I2SSDO_NAME, GPIO1C, 10, 1, 0, DEFAULT) -MUX_CFG(GPIO1C4_I2SSDI_NAME, GPIO1C, 8, 1, 0, DEFAULT) -MUX_CFG(GPIO1C3_I2SLRCLKTX_NAME, GPIO1C, 6, 1, 0, DEFAULT) -MUX_CFG(GPIO1C2_I2SLRCLKRX_NAME, GPIO1C, 4, 1, 0, DEFAULT) -MUX_CFG(GPIO1C1_I2SSCLK_NAME, GPIO1C, 2, 1, 0, DEFAULT) -MUX_CFG(GPIO1C0_I2SCLK_NAME, GPIO1C, 0, 1, 0, DEFAULT) - -//GPIO1D -MUX_CFG(GPIO1D7_I2C4SCL_NAME, GPIO1D, 14, 1, 0, DEFAULT) -MUX_CFG(GPIO1D6_I2C4SDA_NAME, GPIO1D, 12, 1, 0, DEFAULT) -MUX_CFG(GPIO1D5_I2C2SCL_NAME, GPIO1D, 10, 1, 0, DEFAULT) -MUX_CFG(GPIO1D4_I2C2SDA_NAME, GPIO1D, 8, 1, 0, DEFAULT) -MUX_CFG(GPIO1D3_I2C1SCL_NAME, GPIO1D, 6, 1, 0, DEFAULT) -MUX_CFG(GPIO1D2_I2C1SDA_NAME, GPIO1D, 4, 1, 0, DEFAULT) -MUX_CFG(GPIO1D1_I2C0SCL_NAME, GPIO1D, 2, 1, 0, DEFAULT) -MUX_CFG(GPIO1D0_I2C0SDA_NAME, GPIO1D, 0, 1, 0, DEFAULT) - -//GPIO2A -MUX_CFG(GPIO2A7_LCDC1DATA7_SMCDATA7_TRACEDATA7_NAME, GPIO2A, 14, 2, 0, DEFAULT) -MUX_CFG(GPIO2A6_LCDC1DATA6_SMCDATA6_TRACEDATA6_NAME, GPIO2A, 12, 2, 0, DEFAULT) -MUX_CFG(GPIO2A5_LCDC1DATA5_SMCDATA5_TRACEDATA5_NAME, GPIO2A, 10, 2, 0, DEFAULT) -MUX_CFG(GPIO2A4_LCDC1DATA4_SMCDATA4_TRACEDATA4_NAME, GPIO2A, 8, 2, 0, DEFAULT) -MUX_CFG(GPIO2A3_LCDC1DATA3_SMCDATA3_TRACEDATA3_NAME, GPIO2A, 6, 2, 0, DEFAULT) -MUX_CFG(GPIO2A2_LCDC1DATA2_SMCDATA2_TRACEDATA2_NAME, GPIO2A, 4, 2, 0, DEFAULT) -MUX_CFG(GPIO2A1_LCDC1DATA1_SMCDATA1_TRACEDATA1_NAME, GPIO2A, 2, 2, 0, DEFAULT) -MUX_CFG(GPIO2A0_LCDC1DATA0_SMCDATA0_TRACEDATA0_NAME, GPIO2A, 0, 2, 0, DEFAULT) - -//GPIO2B -MUX_CFG(GPIO2B7_LCDC1DATA15_SMCDATA15_TRACEDATA15_NAME, GPIO2B, 14, 2, 0, DEFAULT) -MUX_CFG(GPIO2B6_LCDC1DATA14_SMCDATA14_TRACEDATA14_NAME, GPIO2B, 12, 2, 0, DEFAULT) -MUX_CFG(GPIO2B5_LCDC1DATA13_SMCDATA13_TRACEDATA13_NAME, GPIO2B, 10, 2, 0, DEFAULT) -MUX_CFG(GPIO2B4_LCDC1DATA12_SMCDATA12_TRACEDATA12_NAME, GPIO2B, 8, 2, 0, DEFAULT) -MUX_CFG(GPIO2B3_LCDC1DATA11_SMCDATA11_TRACEDATA11_NAME, GPIO2B, 6, 2, 0, DEFAULT) -MUX_CFG(GPIO2B2_LCDC1DATA10_SMCDATA10_TRACEDATA10_NAME, GPIO2B, 4, 2, 0, DEFAULT) -MUX_CFG(GPIO2B1_LCDC1DATA9_SMCDATA9_TRACEDATA9_NAME, GPIO2B, 2, 2, 0, DEFAULT) -MUX_CFG(GPIO2B0_LCDC1DATA8_SMCDATA8_TRACEDATA8_NAME, GPIO2B, 0, 2, 0, DEFAULT) - -//GPIO2C -MUX_CFG(GPIO2C7_LCDC1DATA23_SMCADDR7_NAME, GPIO2C, 14, 2, 0, DEFAULT) -MUX_CFG(GPIO2C6_LCDC1DATA22_SMCADDR6_NAME, GPIO2C, 12, 2, 0, DEFAULT) -MUX_CFG(GPIO2C5_LCDC1DATA21_SMCADDR5_NAME, GPIO2C, 10, 2, 0, DEFAULT) -MUX_CFG(GPIO2C4_LCDC1DATA20_SMCADDR4_NAME, GPIO2C, 8, 2, 0, DEFAULT) -MUX_CFG(GPIO2C3_LCDC1DATA19_SMCADDR3_NAME, GPIO2C, 6, 2, 0, DEFAULT) -MUX_CFG(GPIO2C2_LCDC1DATA18_SMCADDR2_NAME, GPIO2C, 4, 2, 0, DEFAULT) -MUX_CFG(GPIO2C1_LCDC1DATA17_SMCADDR1_TRACECTL_NAME, GPIO2C, 2, 2, 0, DEFAULT) -MUX_CFG(GPIO2C0_LCDC1DATA16_SMCADDR0_TRACECLK_NAME, GPIO2C, 0, 2, 0, DEFAULT) - -//GPIO2D -MUX_CFG(GPIO2D7_TESTCLOCKOUT_NAME, GPIO2D, 14, 1, 0, DEFAULT) -MUX_CFG(GPIO2D6_SMCCSN1_NAME, GPIO2D, 12, 1, 0, DEFAULT) -MUX_CFG(GPIO2D5_SMCBLSN1_NAME, GPIO2D, 10, 1, 0, DEFAULT) -MUX_CFG(GPIO2D4_SMCBLSN0_NAME, GPIO2D, 8, 1, 0, DEFAULT) -MUX_CFG(GPIO2D3_LCDC1VSYNC_SMCADVN_NAME, GPIO2D, 6, 2, 0, DEFAULT) -MUX_CFG(GPIO2D2_LCDC1HSYNC_SMCOEN_NAME, GPIO2D, 4, 2, 0, DEFAULT) -MUX_CFG(GPIO2D1_LCDC1DEN_SMCWEN_NAME, GPIO2D, 2, 2, 0, DEFAULT) -MUX_CFG(GPIO2D0_LCDC1DCLK_SMCCSN0_NAME, GPIO2D, 0, 2, 0, DEFAULT) - -//GPIO3A -MUX_CFG(GPIO3A7_SDMMC0DATA3_NAME, GPIO3A, 14, 1, 0, DEFAULT) -MUX_CFG(GPIO3A6_SDMMC0DATA2_NAME, GPIO3A, 12, 1, 0, DEFAULT) -MUX_CFG(GPIO3A5_SDMMC0DATA1_NAME, GPIO3A, 10, 1, 0, DEFAULT) -MUX_CFG(GPIO3A4_SDMMC0DATA0_NAME, GPIO3A, 8, 1, 0, DEFAULT) -MUX_CFG(GPIO3A3_SDMMC0CMD_NAME, GPIO3A, 6, 1, 0, DEFAULT) -MUX_CFG(GPIO3A2_SDMMC0CLKOUT_NAME, GPIO3A, 4, 1, 0, DEFAULT) -MUX_CFG(GPIO3A1_SDMMC0PWREN_NAME, GPIO3A, 2, 1, 0, DEFAULT) -MUX_CFG(GPIO3A0_SDMMC0RSTNOUT_NAME, GPIO3A, 0, 1, 0, DEFAULT) - -//GPIO3B -MUX_CFG(GPIO3B7_CIFDATA11_I2C3SCL_NAME, GPIO3B, 14, 2, 0, DEFAULT) -MUX_CFG(GPIO3B6_CIFDATA10_I2C3SDA_NAME, GPIO3B, 12, 2, 0, DEFAULT) -MUX_CFG(GPIO3B5_CIFDATA1_HSADCDATA9_NAME, GPIO3B, 10, 2, 0, DEFAULT) -MUX_CFG(GPIO3B4_CIFDATA0_HSADCDATA8_NAME, GPIO3B, 8, 2, 0, DEFAULT) -MUX_CFG(GPIO3B3_CIFCLKOUT_NAME, GPIO3B, 6, 1, 0, DEFAULT) -MUX_CFG(GPIO3B1_SDMMC0WRITEPRT_NAME, GPIO3B, 2, 1, 0, DEFAULT) -MUX_CFG(GPIO3B0_SDMMC0DETECTN_NAME, GPIO3B, 0, 1, 0, DEFAULT) - -//GPIO3C -MUX_CFG(GPIO3C7_SDMMC1WRITEPRT_RMIICRS_NAME, GPIO3C, 14, 2, 0, DEFAULT) -MUX_CFG(GPIO3C6_SDMMC1DETECTN_RMIIRXERR_NAME, GPIO3C, 12, 2, 0, DEFAULT) -MUX_CFG(GPIO3C5_SDMMC1CLKOUT_RMIICLKOUT_RMIICLKIN_NAME, GPIO3C, 10, 2, 0, DEFAULT) -MUX_CFG(GPIO3C4_SDMMC1DATA3_RMIIRXD1_NAME, GPIO3C, 8, 2, 0, DEFAULT) -MUX_CFG(GPIO3C3_SDMMC1DATA2_RMIIRXD0_NAME, GPIO3C, 6, 2, 0, DEFAULT) -MUX_CFG(GPIO3C2_SDMMC1DATA1_RMIITXD0_NAME, GPIO3C, 4, 2, 0, DEFAULT) -MUX_CFG(GPIO3C1_SDMMC1DATA0_RMIITXD1_NAME, GPIO3C, 2, 2, 0, DEFAULT) -MUX_CFG(GPIO3C0_SDMMC1CMD_RMIITXEN_NAME, GPIO3C, 0, 2, 0, DEFAULT) - -//GPIO3D -MUX_CFG(GPIO3D6_PWM3_JTAGTMS_HOSTDRVVBUS_NAME, GPIO3D, 12, 2, 0, DEFAULT) -MUX_CFG(GPIO3D5_PWM2_JTAGTCK_OTGDRVVBUS_NAME, GPIO3D, 10, 2, 0, DEFAULT) -MUX_CFG(GPIO3D4_PWM1_JTAGTRSTN_NAME, GPIO3D, 8, 2, 0, DEFAULT) -MUX_CFG(GPIO3D3_PWM0_NAME, GPIO3D, 6, 1, 0, DEFAULT) -MUX_CFG(GPIO3D2_SDMMC1INTN_NAME, GPIO3D, 4, 1, 0, DEFAULT) -MUX_CFG(GPIO3D1_SDMMC1BACKENDPWR_MIIMDCLK_NAME, GPIO3D, 2, 2, 0, DEFAULT) -MUX_CFG(GPIO3D0_SDMMC1PWREN_MIIMD_NAME, GPIO3D, 0, 2, 0, DEFAULT) - -#endif }; +#endif void rk30_mux_set(struct mux_config *cfg) @@ -403,7 +265,9 @@ int __init rk30_iomux_init(void) rk30_mux_set(&rk30_muxs[i]); } -#if defined(CONFIG_ARCH_RK30) +#if defined(CONFIG_ARCH_RK3066B) + return rk3066b_iomux_init(); +#elif defined(CONFIG_ARCH_RK30) #if defined(CONFIG_UART0_RK29) || (CONFIG_RK_DEBUG_UART == 0) rk30_mux_api_set(GPIO1A1_UART0SOUT_NAME, GPIO1A_UART0_SOUT); @@ -489,8 +353,6 @@ int __init rk30_iomux_init(void) rk30_mux_api_set(GPIO1D0_CIF1VSYNC_MIIMD_NAME, GPIO1D_MII_MD); #endif -#elif defined(CONFIG_ARCH_RK31) - #endif return 0; diff --git a/arch/arm/plat-rk/Kconfig b/arch/arm/plat-rk/Kconfig index 5aa49d777a93..841a698a6d5a 100755 --- a/arch/arm/plat-rk/Kconfig +++ b/arch/arm/plat-rk/Kconfig @@ -189,4 +189,7 @@ config RK_PL330_DMA_TEST bool "pl330 DMA memcpy test" depends on RK_PL330_DMA +config RK_FPGA + bool + endif diff --git a/arch/arm/tools/mach-types b/arch/arm/tools/mach-types index 04d13dd8b8bc..5bb762af6c1d 100644 --- a/arch/arm/tools/mach-types +++ b/arch/arm/tools/mach-types @@ -572,7 +572,6 @@ ventana MACH_VENTANA VENTANA 2927 rk29 MACH_RK29 RK29 2929 rk2928 ARCH_RK2928 RK2928 2928 rk30 ARCH_RK30 RK30 3066 -rk31 ARCH_RK31 RK31 3066 #ec4350sdb MACH_EC4350SDB EC4350SDB 2929 mimas MACH_MIMAS MIMAS 2930 titan MACH_TITAN TITAN 2931 diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 9a470d2235f7..75f17f004a9f 100755 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -48,7 +48,6 @@ obj-$(CONFIG_GPIO_RDC321X) += rdc321x-gpio.o obj-$(CONFIG_ARCH_RK29) += gpio-rk29.o obj-$(CONFIG_ARCH_RK2928) += gpio-rk30.o obj-$(CONFIG_ARCH_RK30) += gpio-rk30.o -obj-$(CONFIG_ARCH_RK31) += gpio-rk30.o obj-$(CONFIG_GPIO_JANZ_TTL) += janz-ttl.o obj-$(CONFIG_GPIO_SX150X) += sx150x.o obj-$(CONFIG_GPIO_VX855) += vx855_gpio.o diff --git a/drivers/gpio/gpio-rk30.c b/drivers/gpio/gpio-rk30.c index 911636cf49c1..6cea67673cc8 100755 --- a/drivers/gpio/gpio-rk30.c +++ b/drivers/gpio/gpio-rk30.c @@ -32,10 +32,10 @@ #include #include -#ifdef CONFIG_ARCH_RK30 -#define MAX_PIN RK30_PIN6_PB7 -#elif defined(CONFIG_ARCH_RK31) +#if defined(CONFIG_ARCH_RK3066B) #define MAX_PIN RK30_PIN3_PD7 +#elif defined(CONFIG_ARCH_RK30) +#define MAX_PIN RK30_PIN6_PB7 #elif defined(CONFIG_ARCH_RK2928) #define MAX_PIN RK2928_PIN3_PD7 #define RK30_GPIO0_PHYS RK2928_GPIO0_PHYS @@ -320,7 +320,7 @@ static void rk30_gpiolib_set(struct gpio_chip *chip, unsigned offset, int val) static int rk30_gpiolib_pull_updown(struct gpio_chip *chip, unsigned offset, unsigned enable) { -#if defined(CONFIG_ARCH_RK30) || defined(CONFIG_ARCH_RK2928) +#if !defined(CONFIG_ARCH_RK3066B) struct rk30_gpio_bank *bank = to_rk30_gpio_bank(chip); unsigned long flags; diff --git a/drivers/i2c/busses/i2c-rk30.h b/drivers/i2c/busses/i2c-rk30.h index d826d5eac4d1..e6b0bbb37b9b 100755 --- a/drivers/i2c/busses/i2c-rk30.h +++ b/drivers/i2c/busses/i2c-rk30.h @@ -44,7 +44,7 @@ #define rk30_ceil(x, y) \ ({ unsigned long __x = (x), __y = (y); (__x + __y - 1) / __y; }) -#if defined(CONFIG_ARCH_RK30) || defined(CONFIG_ARCH_RK31) +#if defined(CONFIG_ARCH_RK30) #define GRF_I2C_CON_BASE (RK30_GRF_BASE + GRF_SOC_CON1) #endif #ifdef CONFIG_ARCH_RK2928 diff --git a/drivers/media/video/Makefile b/drivers/media/video/Makefile index e36039690178..9965c8eee908 100755 --- a/drivers/media/video/Makefile +++ b/drivers/media/video/Makefile @@ -199,10 +199,6 @@ ifeq ($(CONFIG_ARCH_RK30),y) obj-$(CONFIG_VIDEO_RK29_WORK_ONEFRAME) += rk30_camera_oneframe.o obj-$(CONFIG_VIDEO_RK29_WORK_PINGPONG) += rk30_camera_pingpong.o endif -ifeq ($(CONFIG_ARCH_RK31),y) -obj-$(CONFIG_VIDEO_RK29_WORK_ONEFRAME) += rk30_camera_oneframe.o -obj-$(CONFIG_VIDEO_RK29_WORK_PINGPONG) += rk30_camera_pingpong.o -endif ifeq ($(CONFIG_ARCH_RK2928),y) obj-$(CONFIG_VIDEO_RK29_WORK_ONEFRAME) += rk30_camera_oneframe.o obj-$(CONFIG_VIDEO_RK29_WORK_PINGPONG) += rk30_camera_pingpong.o diff --git a/drivers/media/video/rk30_camera.c b/drivers/media/video/rk30_camera.c index 31e8a5bfa746..a8aaa9d164b1 100755 --- a/drivers/media/video/rk30_camera.c +++ b/drivers/media/video/rk30_camera.c @@ -14,167 +14,103 @@ static int rk_sensor_iomux(int pin) { -#if defined(CONFIG_ARCH_RK30) +#if defined(CONFIG_ARCH_RK3066B) switch (pin) { - case RK30_PIN0_PA0: - { - rk30_mux_api_set(GPIO0A0_HDMIHOTPLUGIN_NAME,0); - break; - } + case RK30_PIN0_PA0: case RK30_PIN0_PA1: - { - rk30_mux_api_set(GPIO0A1_HDMII2CSCL_NAME,0); - break; - } - case RK30_PIN0_PA2: - { - rk30_mux_api_set(GPIO0A2_HDMII2CSDA_NAME,0); - break; - } - case RK30_PIN0_PA3: - { - rk30_mux_api_set(GPIO0A3_PWM0_NAME,0); - break; - } - case RK30_PIN0_PA4: - { - rk30_mux_api_set(GPIO0A4_PWM1_NAME,0); - break; - } - case RK30_PIN0_PA5: - { - rk30_mux_api_set(GPIO0A5_OTGDRVVBUS_NAME,0); - break; - } - case RK30_PIN0_PA6: - { - rk30_mux_api_set(GPIO0A6_HOSTDRVVBUS_NAME,0); - break; - } + case RK30_PIN0_PA2: + case RK30_PIN0_PA3: + case RK30_PIN0_PA4: + case RK30_PIN0_PA5: + case RK30_PIN0_PA6: case RK30_PIN0_PA7: - { - rk30_mux_api_set(GPIO0A7_I2S8CHSDI_NAME,0); - break; - } case RK30_PIN0_PB0: - { - rk30_mux_api_set(GPIO0B0_I2S8CHCLK_NAME,0); - break; - } case RK30_PIN0_PB1: - { - rk30_mux_api_set(GPIO0B1_I2S8CHSCLK_NAME,0); - break; - } case RK30_PIN0_PB2: - { - rk30_mux_api_set(GPIO0B2_I2S8CHLRCKRX_NAME,0); - break; - } case RK30_PIN0_PB3: - { - rk30_mux_api_set(GPIO0B3_I2S8CHLRCKTX_NAME,0); - break; - } case RK30_PIN0_PB4: - { - rk30_mux_api_set(GPIO0B4_I2S8CHSDO0_NAME,0); - break; - } case RK30_PIN0_PB5: - { - rk30_mux_api_set(GPIO0B5_I2S8CHSDO1_NAME,0); - break; - } case RK30_PIN0_PB6: - { - rk30_mux_api_set(GPIO0B6_I2S8CHSDO2_NAME,0); - break; - } case RK30_PIN0_PB7: - { - rk30_mux_api_set(GPIO0B7_I2S8CHSDO3_NAME,0); - break; - } case RK30_PIN0_PC0: { - rk30_mux_api_set(GPIO0C0_I2S12CHCLK_NAME,0); + rk30_mux_api_set(GPIO0C0_FLASHDATA8_NAME,0); break; } case RK30_PIN0_PC1: { - rk30_mux_api_set(GPIO0C1_I2S12CHSCLK_NAME,0); + rk30_mux_api_set(GPIO0C1_FLASHDATA9_NAME,0); break; } case RK30_PIN0_PC2: { - rk30_mux_api_set(GPIO0C2_I2S12CHLRCKRX_NAME,0); + rk30_mux_api_set(GPIO0C2_FLASHDATA10_NAME,0); break; } case RK30_PIN0_PC3: { - rk30_mux_api_set(GPIO0C3_I2S12CHLRCKTX_NAME,0); + rk30_mux_api_set(GPIO0C3_FLASHDATA11_NAME,0); break; } case RK30_PIN0_PC4: { - rk30_mux_api_set(GPIO0C4_I2S12CHSDI_NAME,0); + rk30_mux_api_set(GPIO0C4_FLASHDATA12_NAME,0); break; } case RK30_PIN0_PC5: { - rk30_mux_api_set(GPIO0C5_I2S12CHSDO_NAME,0); + rk30_mux_api_set(GPIO0C5_FLASHDATA13_NAME,0); break; } case RK30_PIN0_PC6: { - rk30_mux_api_set(GPIO0C6_TRACECLK_SMCADDR2_NAME,0); + rk30_mux_api_set(GPIO0C6_FLASHDATA14_NAME,0); break; } case RK30_PIN0_PC7: { - rk30_mux_api_set(GPIO0C7_TRACECTL_SMCADDR3_NAME,0); + rk30_mux_api_set(GPIO0C7_FLASHDATA15_NAME,0); break; } case RK30_PIN0_PD0: { - rk30_mux_api_set(GPIO0D0_I2S22CHCLK_SMCCSN0_NAME,0); + rk30_mux_api_set(GPIO0D0_FLASHDQS_EMMCCLKOUT_NAME,0); break; } case RK30_PIN0_PD1: { - rk30_mux_api_set(GPIO0D1_I2S22CHSCLK_SMCWEN_NAME,0); + rk30_mux_api_set(GPIO0D1_FLASHCSN1_NAME,0); break; } case RK30_PIN0_PD2: { - rk30_mux_api_set(GPIO0D2_I2S22CHLRCKRX_SMCOEN_NAME,0); + rk30_mux_api_set(GPIO0D2_FLASHCSN2_EMMCCMD_NAME,0); break; } case RK30_PIN0_PD3: { - rk30_mux_api_set(GPIO0D3_I2S22CHLRCKTX_SMCADVN_NAME,0); + rk30_mux_api_set(GPIO0D3_FLASHCSN3_EMMCRSTNOUT_NAME,0); break; } case RK30_PIN0_PD4: { - rk30_mux_api_set(GPIO0D4_I2S22CHSDI_SMCADDR0_NAME,0); + rk30_mux_api_set(GPIO0D4_SPI1RXD_NAME,0); break; } case RK30_PIN0_PD5: { - rk30_mux_api_set(GPIO0D5_I2S22CHSDO_SMCADDR1_NAME,0); + rk30_mux_api_set(GPIO0D5_SPI1TXD_NAME,0); break; } case RK30_PIN0_PD6: { - rk30_mux_api_set(GPIO0D6_PWM2_NAME,0); + rk30_mux_api_set(GPIO0D6_SPI1CLK_NAME,0); break; } case RK30_PIN0_PD7: { - rk30_mux_api_set(GPIO0D7_PWM3_NAME,0); + rk30_mux_api_set(GPIO0D7_SPI1CSN0_NAME,0); break; } case RK30_PIN1_PA0: @@ -199,432 +135,418 @@ static int rk_sensor_iomux(int pin) } case RK30_PIN1_PA4: { - rk30_mux_api_set(GPIO1A4_UART1SIN_SPI0CSN0_NAME,0); + rk30_mux_api_set(GPIO1A4_UART1SIN_SPI0RXD_NAME,0); break; } case RK30_PIN1_PA5: { - rk30_mux_api_set(GPIO1A5_UART1SOUT_SPI0CLK_NAME,0); + rk30_mux_api_set(GPIO1A5_UART1SOUT_SPI0TXD_NAME,0); break; } case RK30_PIN1_PA6: { - rk30_mux_api_set(GPIO1A6_UART1CTSN_SPI0RXD_NAME,0); + rk30_mux_api_set(GPIO1A6_UART1CTSN_SPI0CLK_NAME,0); break; } case RK30_PIN1_PA7: { - rk30_mux_api_set(GPIO1A7_UART1RTSN_SPI0TXD_NAME,0); + rk30_mux_api_set(GPIO1A7_UART1RTSN_SPI0CSN0_NAME,0); break; } case RK30_PIN1_PB0: { - rk30_mux_api_set(GPIO1B0_UART2SIN_NAME,0); + rk30_mux_api_set(GPIO1B0_UART2SIN_JTAGTDI_NAME,0); break; } case RK30_PIN1_PB1: { - rk30_mux_api_set(GPIO1B1_UART2SOUT_NAME,0); + rk30_mux_api_set(GPIO1B1_UART2SOUT_JTAGTDO_NAME,0); break; } case RK30_PIN1_PB2: { - rk30_mux_api_set(GPIO1B2_SPDIFTX_NAME,0); + rk30_mux_api_set(GPIO1B2_UART3SIN_GPSMAG_NAME,0); break; } case RK30_PIN1_PB3: { - rk30_mux_api_set(GPIO1B3_CIF0CLKOUT_NAME,0); + rk30_mux_api_set(GPIO1B3_UART3SOUT_GPSSIG_NAME,0); break; } case RK30_PIN1_PB4: { - rk30_mux_api_set(GPIO1B4_CIF0DATA0_NAME,0); + rk30_mux_api_set(GPIO1B4_UART3CTSN_GPSRFCLK_NAME,0); break; } case RK30_PIN1_PB5: { - rk30_mux_api_set(GPIO1B5_CIF0DATA1_NAME,0); + rk30_mux_api_set(GPIO1B5_UART3RTSN_NAME,0); break; } case RK30_PIN1_PB6: { - rk30_mux_api_set(GPIO1B6_CIFDATA10_NAME,0); + rk30_mux_api_set(GPIO1B6_SPDIFTX_SPI1CSN1_NAME,0); break; } case RK30_PIN1_PB7: { - rk30_mux_api_set(GPIO1B7_CIFDATA11_NAME,0); + rk30_mux_api_set(GPIO1B7_SPI0CSN1_NAME,0); break; } case RK30_PIN1_PC0: { - rk30_mux_api_set(GPIO1C0_CIF1DATA2_RMIICLKOUT_RMIICLKIN_NAME,0); + rk30_mux_api_set(GPIO1C0_I2SCLK_NAME,0); break; } case RK30_PIN1_PC1: { - rk30_mux_api_set(GPIO1C1_CIFDATA3_RMIITXEN_NAME,0); + rk30_mux_api_set(GPIO1C1_I2SSCLK_NAME,0); break; } case RK30_PIN1_PC2: { - rk30_mux_api_set(GPIO1C2_CIF1DATA4_RMIITXD1_NAME,0); + rk30_mux_api_set(GPIO1C2_I2SLRCLKRX_NAME,0); break; } case RK30_PIN1_PC3: { - rk30_mux_api_set(GPIO1C3_CIFDATA5_RMIITXD0_NAME,0); + rk30_mux_api_set(GPIO1C3_I2SLRCLKTX_NAME,0); break; } case RK30_PIN1_PC4: { - rk30_mux_api_set(GPIO1C4_CIFDATA6_RMIIRXERR_NAME,0); + rk30_mux_api_set(GPIO1C4_I2SSDI_NAME,0); break; } case RK30_PIN1_PC5: - { - rk29_mux_api_set(GPIO1C5_CIFDATA7_RMIICRSDVALID_NAME,0); - break; - } case RK30_PIN1_PC6: - { - rk30_mux_api_set(GPIO1C6_CIFDATA8_RMIIRXD1_NAME,0); - break; - } case RK30_PIN1_PC7: - { - rk30_mux_api_set(GPIO1C7_CIFDATA9_RMIIRXD0_NAME,0); break; - } case RK30_PIN1_PD0: { - rk30_mux_api_set(GPIO1D0_CIF1VSYNC_MIIMD_NAME,0); + rk30_mux_api_set(GPIO1D0_I2C0SDA_NAME,0); break; } case RK30_PIN1_PD1: { - rk30_mux_api_set(GPIO1D1_CIF1HREF_MIIMDCLK_NAME,0); + rk30_mux_api_set(GPIO1D1_I2C0SCL_NAME,0); break; } case RK30_PIN1_PD2: { - rk30_mux_api_set(GPIO1D2_CIF1CLKIN_NAME,0); + rk30_mux_api_set(GPIO1D2_I2C1SDA_NAME,0); break; } case RK30_PIN1_PD3: { - rk30_mux_api_set(GPIO1D3_CIF1DATA0_NAME,0); + rk30_mux_api_set(GPIO1D3_I2C1SCL_NAME,0); break; } case RK30_PIN1_PD4: { - rk30_mux_api_set(GPIO1D4_CIF1DATA1_NAME,0); + rk30_mux_api_set(GPIO1D4_I2C2SDA_NAME,0); break; } case RK30_PIN1_PD5: { - rk30_mux_api_set(GPIO1D5_CIF1DATA10_NAME,0); + rk30_mux_api_set(GPIO1D5_I2C2SCL_NAME,0); break; } case RK30_PIN1_PD6: { - rk30_mux_api_set(GPIO1D6_CIF1DATA11_NAME,0); + rk30_mux_api_set(GPIO1D6_I2C4SDA_NAME,0); break; } case RK30_PIN1_PD7: { - rk30_mux_api_set(GPIO1D7_CIF1CLKOUT_NAME,0); + rk30_mux_api_set(GPIO1D7_I2C4SCL_NAME,0); break; } case RK30_PIN2_PA0: { - rk30_mux_api_set(GPIO2A0_LCDC1DATA0_SMCADDR4_NAME,0); + rk30_mux_api_set(GPIO2A0_LCDC1DATA0_SMCDATA0_TRACEDATA0_NAME,0); break; } case RK30_PIN2_PA1: { - rk30_mux_api_set(GPIO2A1_LCDC1DATA1_SMCADDR5_NAME,0); + rk30_mux_api_set(GPIO2A1_LCDC1DATA1_SMCDATA1_TRACEDATA1_NAME,0); break; } case RK30_PIN2_PA2: { - rk30_mux_api_set(GPIO2A2_LCDCDATA2_SMCADDR6_NAME,0); + rk30_mux_api_set(GPIO2A2_LCDC1DATA2_SMCDATA2_TRACEDATA2_NAME,0); break; } case RK30_PIN2_PA3: { - rk30_mux_api_set(GPIO2A3_LCDCDATA3_SMCADDR7_NAME,0); + rk30_mux_api_set(GPIO2A3_LCDC1DATA3_SMCDATA3_TRACEDATA3_NAME,0); break; } case RK30_PIN2_PA4: { - rk30_mux_api_set(GPIO2A4_LCDC1DATA4_SMCADDR8_NAME,0); + rk30_mux_api_set(GPIO2A4_LCDC1DATA4_SMCDATA4_TRACEDATA4_NAME,0); break; } case RK30_PIN2_PA5: { - rk30_mux_api_set(GPIO2A5_LCDC1DATA5_SMCADDR9_NAME,0); + rk30_mux_api_set(GPIO2A5_LCDC1DATA5_SMCDATA5_TRACEDATA5_NAME,0); break; } case RK30_PIN2_PA6: { - rk30_mux_api_set(GPIO2A6_LCDC1DATA6_SMCADDR10_NAME,0); + rk30_mux_api_set(GPIO2A6_LCDC1DATA6_SMCDATA6_TRACEDATA6_NAME,0); break; } case RK30_PIN2_PA7: { - rk30_mux_api_set(GPIO2A7_LCDC1DATA7_SMCADDR11_NAME,0); + rk30_mux_api_set(GPIO2A7_LCDC1DATA7_SMCDATA7_TRACEDATA7_NAME,0); break; } case RK30_PIN2_PB0: { - rk30_mux_api_set(GPIO2B0_LCDC1DATA8_SMCADDR12_NAME,0); + rk30_mux_api_set(GPIO2B0_LCDC1DATA8_SMCDATA8_TRACEDATA8_NAME,0); break; } case RK30_PIN2_PB1: { - rk30_mux_api_set(GPIO2B1_LCDC1DATA9_SMCADDR13_NAME,0); + rk30_mux_api_set(GPIO2B1_LCDC1DATA9_SMCDATA9_TRACEDATA9_NAME,0); break; } case RK30_PIN2_PB2: { - rk30_mux_api_set(GPIO2B2_LCDC1DATA10_SMCADDR14_NAME,0); + rk30_mux_api_set(GPIO2B2_LCDC1DATA10_SMCDATA10_TRACEDATA10_NAME,0); break; } case RK30_PIN2_PB3: { - rk30_mux_api_set(GPIO2B3_LCDC1DATA11_SMCADDR15_NAME,0); + rk30_mux_api_set(GPIO2B3_LCDC1DATA11_SMCDATA11_TRACEDATA11_NAME,0); break; } case RK30_PIN2_PB4: { - rk30_mux_api_set(GPIO2B4_LCDC1DATA12_SMCADDR16_HSADCDATA9_NAME,0); + rk30_mux_api_set(GPIO2B4_LCDC1DATA12_SMCDATA12_TRACEDATA12_NAME,0); break; } case RK30_PIN2_PB5: { - rk30_mux_api_set(GPIO2B5_LCDC1DATA13_SMCADDR17_HSADCDATA8_NAME,0); + rk30_mux_api_set(GPIO2B5_LCDC1DATA13_SMCDATA13_TRACEDATA13_NAME,0); break; } case RK30_PIN2_PB6: { - rk30_mux_api_set(GPIO2B6_LCDC1DATA14_SMCADDR18_TSSYNC_NAME,0); + rk30_mux_api_set(GPIO2B6_LCDC1DATA14_SMCDATA14_TRACEDATA14_NAME,0); break; } case RK30_PIN2_PB7: { - rk30_mux_api_set(GPIO2B7_LCDC1DATA15_SMCADDR19_HSADCDATA7_NAME,0); + rk30_mux_api_set(GPIO2B7_LCDC1DATA15_SMCDATA15_TRACEDATA15_NAME,0); break; } case RK30_PIN2_PC0: { - rk30_mux_api_set(GPIO2C0_LCDCDATA16_GPSCLK_HSADCCLKOUT_NAME,0); + rk30_mux_api_set(GPIO2C0_LCDC1DATA16_SMCADDR0_TRACECLK_NAME,0); break; } case RK30_PIN2_PC1: { - rk30_mux_api_set(GPIO2C1_LCDC1DATA17_SMCBLSN0_HSADCDATA6_NAME,0); + rk30_mux_api_set(GPIO2C1_LCDC1DATA17_SMCADDR1_TRACECTL_NAME,0); break; } case RK30_PIN2_PC2: { - rk30_mux_api_set(GPIO2C2_LCDC1DATA18_SMCBLSN1_HSADCDATA5_NAME,0); + rk30_mux_api_set(GPIO2C2_LCDC1DATA18_SMCADDR2_NAME,0); break; } case RK30_PIN2_PC3: { - rk29_mux_api_set(GPIO2C3_LCDC1DATA19_SPI1CLK_HSADCDATA0_NAME,0); + rk29_mux_api_set(GPIO2C3_LCDC1DATA19_SMCADDR3_NAME,0); break; } case RK30_PIN2_PC4: { - rk30_mux_api_set(GPIO2C4_LCDC1DATA20_SPI1CSN0_HSADCDATA1_NAME,0); + rk30_mux_api_set(GPIO2C4_LCDC1DATA20_SMCADDR4_NAME,0); break; } case RK30_PIN2_PC5: { - rk30_mux_api_set(GPIO2C5_LCDC1DATA21_SPI1TXD_HSADCDATA2_NAME,0); + rk30_mux_api_set(GPIO2C5_LCDC1DATA21_SMCADDR5_NAME,0); break; } case RK30_PIN2_PC6: { - rk30_mux_api_set(GPIO2C6_LCDC1DATA22_SPI1RXD_HSADCDATA3_NAME,0); + rk30_mux_api_set(GPIO2C6_LCDC1DATA22_SMCADDR6_NAME,0); break; } case RK30_PIN2_PC7: { - rk30_mux_api_set(GPIO2C7_LCDC1DATA23_SPI1CSN1_HSADCDATA4_NAME,0); + rk30_mux_api_set(GPIO2C7_LCDC1DATA23_SMCADDR7_NAME,0); break; } case RK30_PIN2_PD0: { - rk30_mux_api_set(GPIO2D0_LCDC1DCLK_NAME,0); + rk30_mux_api_set(GPIO2D0_LCDC1DCLK_SMCCSN0_NAME,0); break; } case RK30_PIN2_PD1: { - rk30_mux_api_set(GPIO2D1_LCDC1DEN_SMCCSN1_NAME,0); + rk30_mux_api_set(GPIO2D1_LCDC1DEN_SMCWEN_NAME,0); break; } case RK30_PIN2_PD2: { - rk30_mux_api_set(GPIO2D2_LCDC1HSYNC_NAME,0); + rk30_mux_api_set(GPIO2D2_LCDC1HSYNC_SMCOEN_NAME,0); break; } case RK30_PIN2_PD3: { - rk30_mux_api_set(GPIO2D3_LCDC1VSYNC_NAME,0); + rk30_mux_api_set(GPIO2D3_LCDC1VSYNC_SMCADVN_NAME,0); break; } case RK30_PIN2_PD4: { - rk30_mux_api_set(GPIO2D4_I2C0SDA_NAME,0); + rk30_mux_api_set(GPIO2D4_SMCBLSN0_NAME,0); break; } case RK30_PIN2_PD5: { - rk30_mux_api_set(GPIO2D5_I2C0SCL_NAME,0); + rk30_mux_api_set(GPIO2D5_SMCBLSN1_NAME,0); break; } case RK30_PIN2_PD6: { - rk30_mux_api_set(GPIO2D6_I2C1SDA_NAME,0); + rk30_mux_api_set(GPIO2D6_SMCCSN1_NAME,0); break; } case RK30_PIN2_PD7: { - rk30_mux_api_set(GPIO2D7_I2C1SCL_NAME,0); + rk30_mux_api_set(GPIO2D7_TESTCLOCKOUT_NAME,0); break; } case RK30_PIN3_PA0: { - rk30_mux_api_set(GPIO3A0_I2C2SDA_NAME,0); + rk30_mux_api_set(GPIO3A0_SDMMC0RSTNOUT_NAME,0); break; } case RK30_PIN3_PA1: { - rk30_mux_api_set(GPIO3A1_I2C2SCL_NAME,0); + rk30_mux_api_set(GPIO3A1_SDMMC0PWREN_NAME,0); break; } case RK30_PIN3_PA2: { - rk30_mux_api_set(GPIO3A2_I2C3SDA_NAME,0); + rk30_mux_api_set(GPIO3A2_SDMMC0CLKOUT_NAME,0); break; } case RK30_PIN3_PA3: { - rk30_mux_api_set(GPIO3A3_I2C3SCL_NAME,0); + rk30_mux_api_set(GPIO3A3_SDMMC0CMD_NAME,0); break; } case RK30_PIN3_PA4: { - rk30_mux_api_set(GPIO3A4_I2C4SDA_NAME,0); + rk30_mux_api_set(GPIO3A4_SDMMC0DATA0_NAME,0); break; } case RK30_PIN3_PA5: { - rk30_mux_api_set(GPIO3A5_I2C4SCL_NAME,0); + rk30_mux_api_set(GPIO3A5_SDMMC0DATA1_NAME,0); break; } case RK30_PIN3_PA6: { - rk30_mux_api_set(GPIO3A6_SDMMC0RSTNOUT_NAME,0); + rk30_mux_api_set(GPIO3A6_SDMMC0DATA2_NAME,0); break; } case RK30_PIN3_PA7: { - rk30_mux_api_set(GPIO3A7_SDMMC0PWREN_NAME,0); + rk30_mux_api_set(GPIO3A7_SDMMC0DATA3_NAME,0); break; } case RK30_PIN3_PB0: { - rk30_mux_api_set(GPIO3B0_SDMMC0CLKOUT_NAME,0); + rk30_mux_api_set(GPIO3B0_SDMMC0DETECTN_NAME,0); break; } case RK30_PIN3_PB1: { - rk30_mux_api_set(GPIO3B1_SDMMC0CMD_NAME,0); - break; - } - case RK30_PIN3_PB2: - { - rk30_mux_api_set(GPIO3B2_SDMMC0DATA0_NAME,0); + rk30_mux_api_set(GPIO3B1_SDMMC0WRITEPRT_NAME,0); break; } + case RK30_PIN3_PB2: + break; case RK30_PIN3_PB3: { - rk30_mux_api_set(GPIO3B3_SDMMC0DATA1_NAME,0); + rk30_mux_api_set(GPIO3B3_CIFCLKOUT_NAME,0); break; } case RK30_PIN3_PB4: { - rk30_mux_api_set(GPIO3B4_SDMMC0DATA2_NAME,0); + rk30_mux_api_set(GPIO3B4_CIFDATA0_HSADCDATA8_NAME,0); break; } case RK30_PIN3_PB5: { - rk30_mux_api_set(GPIO3B5_SDMMC0DATA3_NAME,0); + rk30_mux_api_set(GPIO3B5_CIFDATA1_HSADCDATA9_NAME,0); break; } case RK30_PIN3_PB6: { - rk30_mux_api_set(GPIO3B6_SDMMC0DETECTN_NAME,0); + rk30_mux_api_set(GPIO3B6_CIFDATA10_I2C3SDA_NAME,0); break; } case RK30_PIN3_PB7: { - rk30_mux_api_set(GPIO3B7_SDMMC0WRITEPRT_NAME,0); + rk30_mux_api_set(GPIO3B7_CIFDATA11_I2C3SCL_NAME,0); break; } case RK30_PIN3_PC0: { - rk30_mux_api_set(GPIO3C0_SMMC1CMD_NAME,0); + rk30_mux_api_set(GPIO3C0_SDMMC1CMD_RMIITXEN_NAME,0); break; } case RK30_PIN3_PC1: { - rk30_mux_api_set(GPIO3C1_SDMMC1DATA0_NAME,0); + rk30_mux_api_set(GPIO3C1_SDMMC1DATA0_RMIITXD1_NAME,0); break; } case RK30_PIN3_PC2: { - rk30_mux_api_set(GPIO3C2_SDMMC1DATA1_NAME,0); + rk30_mux_api_set(GPIO3C2_SDMMC1DATA1_RMIITXD0_NAME,0); break; } case RK30_PIN3_PC3: { - rk30_mux_api_set(GPIO3C3_SDMMC1DATA2_NAME,0); + rk30_mux_api_set(GPIO3C3_SDMMC1DATA2_RMIIRXD0_NAME,0); break; } case RK30_PIN3_PC4: { - rk30_mux_api_set(GPIO3C4_SDMMC1DATA3_NAME,0); + rk30_mux_api_set(GPIO3C4_SDMMC1DATA3_RMIIRXD1_NAME,0); break; } case RK30_PIN3_PC5: { - rk30_mux_api_set(GPIO3C5_SDMMC1CLKOUT_NAME,0); + rk30_mux_api_set(GPIO3C5_SDMMC1CLKOUT_RMIICLKOUT_RMIICLKIN_NAME,0); break; } case RK30_PIN3_PC6: { - rk30_mux_api_set(GPIO3C6_SDMMC1DETECTN_NAME,0); + rk30_mux_api_set(GPIO3C6_SDMMC1DETECTN_RMIIRXERR_NAME,0); break; } case RK30_PIN3_PC7: { - rk30_mux_api_set(GPIO3C7_SDMMC1WRITEPRT_NAME,0); + rk30_mux_api_set(GPIO3C7_SDMMC1WRITEPRT_RMIICRS_NAME,0); break; } case RK30_PIN3_PD0: { - rk30_mux_api_set(GPIO3D0_SDMMC1PWREN_NAME,0); + rk30_mux_api_set(GPIO3D0_SDMMC1PWREN_MIIMD_NAME,0); break; } case RK30_PIN3_PD1: { - rk30_mux_api_set(GPIO3D1_SDMMC1BACKENDPWR_NAME,0); + rk30_mux_api_set(GPIO3D1_SDMMC1BACKENDPWR_MIIMDCLK_NAME,0); break; } case RK30_PIN3_PD2: @@ -634,317 +556,195 @@ static int rk_sensor_iomux(int pin) } case RK30_PIN3_PD3: { - rk30_mux_api_set(GPIO3D3_UART3SIN_NAME,0); + rk30_mux_api_set(GPIO3D3_PWM0_NAME,0); break; } case RK30_PIN3_PD4: { - rk30_mux_api_set(GPIO3D4_UART3SOUT_NAME,0); + rk30_mux_api_set(GPIO3D4_PWM1_JTAGTRSTN_NAME,0); break; } case RK30_PIN3_PD5: { - rk30_mux_api_set(GPIO3D5_UART3CTSN_NAME,0); + rk30_mux_api_set(GPIO3D5_PWM2_JTAGTCK_OTGDRVVBUS_NAME,0); break; } case RK30_PIN3_PD6: { - rk30_mux_api_set(GPIO3D6_UART3RTSN_NAME,0); + rk30_mux_api_set(GPIO3D6_PWM3_JTAGTMS_HOSTDRVVBUS_NAME,0); break; } - case RK30_PIN3_PD7: + case RK30_PIN3_PD7: + break; + default: { - rk30_mux_api_set(GPIO3D7_FLASHDQS_EMMCCLKOUT_NAME,0); - break; + printk("Pin=%d isn't RK GPIO, Please init it's iomux yourself!",pin); + break; } - case RK30_PIN4_PA0: - { - rk30_mux_api_set(GPIO4A0_FLASHDATA8_NAME,0); - break; - } - case RK30_PIN4_PA1: - { - rk30_mux_api_set(GPIO4A1_FLASHDATA9_NAME,0); - break; - } - case RK30_PIN4_PA2: - { - rk30_mux_api_set(GPIO4A2_FLASHDATA10_NAME,0); - break; - } - - case RK30_PIN4_PA3: - { - rk30_mux_api_set(GPIO4A3_FLASHDATA11_NAME,0); - break; - } - case RK30_PIN4_PA4: - { - rk30_mux_api_set(GPIO4A4_FLASHDATA12_NAME,0); - break; - } - case RK30_PIN4_PA5: + } + +#elif defined(CONFIG_ARCH_RK30) + switch (pin) + { + case RK30_PIN0_PA0: + { + rk30_mux_api_set(GPIO0A0_HDMIHOTPLUGIN_NAME,0); + break; + } + case RK30_PIN0_PA1: + { + rk30_mux_api_set(GPIO0A1_HDMII2CSCL_NAME,0); + break; + } + case RK30_PIN0_PA2: + { + rk30_mux_api_set(GPIO0A2_HDMII2CSDA_NAME,0); + break; + } + case RK30_PIN0_PA3: + { + rk30_mux_api_set(GPIO0A3_PWM0_NAME,0); + break; + } + case RK30_PIN0_PA4: + { + rk30_mux_api_set(GPIO0A4_PWM1_NAME,0); + break; + } + case RK30_PIN0_PA5: + { + rk30_mux_api_set(GPIO0A5_OTGDRVVBUS_NAME,0); + break; + } + case RK30_PIN0_PA6: { - rk30_mux_api_set(GPIO4A5_FLASHDATA13_NAME,0); + rk30_mux_api_set(GPIO0A6_HOSTDRVVBUS_NAME,0); break; } - case RK30_PIN4_PA6: + case RK30_PIN0_PA7: { - rk30_mux_api_set(GPIO4A6_FLASHDATA14_NAME,0); + rk30_mux_api_set(GPIO0A7_I2S8CHSDI_NAME,0); break; } - case RK30_PIN4_PA7: + case RK30_PIN0_PB0: { - rk30_mux_api_set(GPIO4A7_FLASHDATA15_NAME,0); + rk30_mux_api_set(GPIO0B0_I2S8CHCLK_NAME,0); break; } - case RK30_PIN4_PB0: + case RK30_PIN0_PB1: { - rk30_mux_api_set(GPIO4B0_FLASHCSN1_NAME,0); + rk30_mux_api_set(GPIO0B1_I2S8CHSCLK_NAME,0); break; } - case RK30_PIN4_PB1: + case RK30_PIN0_PB2: { - rk30_mux_api_set(GPIO4B1_FLASHCSN2_EMMCCMD_NAME,0); + rk30_mux_api_set(GPIO0B2_I2S8CHLRCKRX_NAME,0); break; } - case RK30_PIN4_PB2: + case RK30_PIN0_PB3: { - rk30_mux_api_set(GPIO4B2_FLASHCSN3_EMMCRSTNOUT_NAME,0); + rk30_mux_api_set(GPIO0B3_I2S8CHLRCKTX_NAME,0); break; } - case RK30_PIN4_PB3: + case RK30_PIN0_PB4: { - rk30_mux_api_set(GPIO4B3_FLASHCSN4_NAME,0); + rk30_mux_api_set(GPIO0B4_I2S8CHSDO0_NAME,0); break; } - case RK30_PIN4_PB4: + case RK30_PIN0_PB5: { - rk30_mux_api_set(GPIO4B4_FLASHCSN5_NAME,0); + rk30_mux_api_set(GPIO0B5_I2S8CHSDO1_NAME,0); break; } - case RK30_PIN4_PB5: + case RK30_PIN0_PB6: { - rk30_mux_api_set(GPIO4B5_FLASHCSN6_NAME,0); + rk30_mux_api_set(GPIO0B6_I2S8CHSDO2_NAME,0); break; } - case RK30_PIN4_PB6: + case RK30_PIN0_PB7: { - rk30_mux_api_set(GPIO4B6_FLASHCSN7_NAME ,0); + rk30_mux_api_set(GPIO0B7_I2S8CHSDO3_NAME,0); break; } - case RK30_PIN4_PB7: + case RK30_PIN0_PC0: { - rk30_mux_api_set(GPIO4B7_SPI0CSN1_NAME,0); + rk30_mux_api_set(GPIO0C0_I2S12CHCLK_NAME,0); break; } - case RK30_PIN4_PC0: + case RK30_PIN0_PC1: { - rk30_mux_api_set(GPIO4C0_SMCDATA0_TRACEDATA0_NAME,0); + rk30_mux_api_set(GPIO0C1_I2S12CHSCLK_NAME,0); break; } - case RK30_PIN4_PC1: + case RK30_PIN0_PC2: { - rk30_mux_api_set(GPIO4C1_SMCDATA1_TRACEDATA1_NAME,0); + rk30_mux_api_set(GPIO0C2_I2S12CHLRCKRX_NAME,0); break; } - case RK30_PIN4_PC2: + case RK30_PIN0_PC3: { - rk30_mux_api_set(GPIO4C2_SMCDATA2_TRACEDATA2_NAME,0); + rk30_mux_api_set(GPIO0C3_I2S12CHLRCKTX_NAME,0); break; } - case RK30_PIN4_PC3: + case RK30_PIN0_PC4: { - rk30_mux_api_set(GPIO4C3_SMCDATA3_TRACEDATA3_NAME,0); + rk30_mux_api_set(GPIO0C4_I2S12CHSDI_NAME,0); break; } - case RK30_PIN4_PC4: + case RK30_PIN0_PC5: { - rk30_mux_api_set(GPIO4C4_SMCDATA4_TRACEDATA4_NAME,0); + rk30_mux_api_set(GPIO0C5_I2S12CHSDO_NAME,0); break; } - case RK30_PIN4_PC5: + case RK30_PIN0_PC6: { - rk30_mux_api_set(GPIO4C5_SMCDATA5_TRACEDATA5_NAME,0); + rk30_mux_api_set(GPIO0C6_TRACECLK_SMCADDR2_NAME,0); break; } - case RK30_PIN4_PC6: + case RK30_PIN0_PC7: { - rk30_mux_api_set(GPIO4C6_SMCDATA6_TRACEDATA6_NAME,0); + rk30_mux_api_set(GPIO0C7_TRACECTL_SMCADDR3_NAME,0); break; } - - - case RK30_PIN4_PC7: + case RK30_PIN0_PD0: { - rk30_mux_api_set(GPIO4C7_SMCDATA7_TRACEDATA7_NAME,0); + rk30_mux_api_set(GPIO0D0_I2S22CHCLK_SMCCSN0_NAME,0); break; } - case RK30_PIN4_PD0: - { - rk30_mux_api_set(GPIO4D0_SMCDATA8_TRACEDATA8_NAME,0); - break; - } - case RK30_PIN4_PD1: + case RK30_PIN0_PD1: { - rk30_mux_api_set(GPIO4D1_SMCDATA9_TRACEDATA9_NAME,0); - break; + rk30_mux_api_set(GPIO0D1_I2S22CHSCLK_SMCWEN_NAME,0); + break; } - case RK30_PIN4_PD2: - { - rk30_mux_api_set(GPIO4D2_SMCDATA10_TRACEDATA10_NAME,0); - break; - } - case RK30_PIN4_PD3: + case RK30_PIN0_PD2: { - rk30_mux_api_set(GPIO4D3_SMCDATA11_TRACEDATA11_NAME,0); - break; + rk30_mux_api_set(GPIO0D2_I2S22CHLRCKRX_SMCOEN_NAME,0); + break; } - case RK30_PIN4_PD4: + case RK30_PIN0_PD3: { - rk30_mux_api_set(GPIO4D4_SMCDATA12_TRACEDATA12_NAME,0); + rk30_mux_api_set(GPIO0D3_I2S22CHLRCKTX_SMCADVN_NAME,0); break; } - case RK30_PIN4_PD5: + case RK30_PIN0_PD4: { - rk30_mux_api_set(GPIO4D5_SMCDATA13_TRACEDATA13_NAME,0); + rk30_mux_api_set(GPIO0D4_I2S22CHSDI_SMCADDR0_NAME,0); break; } - case RK30_PIN4_PD6: + case RK30_PIN0_PD5: { - rk30_mux_api_set(GPIO4D6_SMCDATA14_TRACEDATA14_NAME,0); + rk30_mux_api_set(GPIO0D5_I2S22CHSDO_SMCADDR1_NAME,0); break; } - case RK30_PIN4_PD7: + case RK30_PIN0_PD6: { - rk30_mux_api_set(GPIO4D7_SMCDATA15_TRACEDATA15_NAME,0); + rk30_mux_api_set(GPIO0D6_PWM2_NAME,0); break; - } - case RK30_PIN6_PA0: - case RK30_PIN6_PA1: - case RK30_PIN6_PA2: - case RK30_PIN6_PA3: - case RK30_PIN6_PA4: - case RK30_PIN6_PA5: - case RK30_PIN6_PA6: - case RK30_PIN6_PA7: - case RK30_PIN6_PB0: - case RK30_PIN6_PB1: - case RK30_PIN6_PB2: - case RK30_PIN6_PB3: - case RK30_PIN6_PB4: - case RK30_PIN6_PB5: - case RK30_PIN6_PB6: - break; - case RK30_PIN6_PB7: - { - rk30_mux_api_set(GPIO6B7_TESTCLOCKOUT_NAME,0); - break; - } - default: + } + case RK30_PIN0_PD7: { - printk("Pin=%d isn't RK GPIO, Please init it's iomux yourself!",pin); - break; - } - } -#elif defined(CONFIG_ARCH_RK31) - switch (pin) - { - case RK30_PIN0_PA0: - case RK30_PIN0_PA1: - case RK30_PIN0_PA2: - case RK30_PIN0_PA3: - case RK30_PIN0_PA4: - case RK30_PIN0_PA5: - case RK30_PIN0_PA6: - case RK30_PIN0_PA7: - case RK30_PIN0_PB0: - case RK30_PIN0_PB1: - case RK30_PIN0_PB2: - case RK30_PIN0_PB3: - case RK30_PIN0_PB4: - case RK30_PIN0_PB5: - case RK30_PIN0_PB6: - case RK30_PIN0_PB7: - case RK30_PIN0_PC0: - { - rk30_mux_api_set(GPIO0C0_FLASHDATA8_NAME,0); - break; - } - case RK30_PIN0_PC1: - { - rk30_mux_api_set(GPIO0C1_FLASHDATA9_NAME,0); - break; - } - case RK30_PIN0_PC2: - { - rk30_mux_api_set(GPIO0C2_FLASHDATA10_NAME,0); - break; - } - case RK30_PIN0_PC3: - { - rk30_mux_api_set(GPIO0C3_FLASHDATA11_NAME,0); - break; - } - case RK30_PIN0_PC4: - { - rk30_mux_api_set(GPIO0C4_FLASHDATA12_NAME,0); - break; - } - case RK30_PIN0_PC5: - { - rk30_mux_api_set(GPIO0C5_FLASHDATA13_NAME,0); - break; - } - case RK30_PIN0_PC6: - { - rk30_mux_api_set(GPIO0C6_FLASHDATA14_NAME,0); - break; - } - case RK30_PIN0_PC7: - { - rk30_mux_api_set(GPIO0C7_FLASHDATA15_NAME,0); - break; - } - case RK30_PIN0_PD0: - { - rk30_mux_api_set(GPIO0D0_FLASHDQS_EMMCCLKOUT_NAME,0); - break; - } - case RK30_PIN0_PD1: - { - rk30_mux_api_set(GPIO0D1_FLASHCSN1_NAME,0); - break; - } - case RK30_PIN0_PD2: - { - rk30_mux_api_set(GPIO0D2_FLASHCSN2_EMMCCMD_NAME,0); - break; - } - case RK30_PIN0_PD3: - { - rk30_mux_api_set(GPIO0D3_FLASHCSN3_EMMCRSTNOUT_NAME,0); - break; - } - case RK30_PIN0_PD4: - { - rk30_mux_api_set(GPIO0D4_SPI1RXD_NAME,0); - break; - } - case RK30_PIN0_PD5: - { - rk30_mux_api_set(GPIO0D5_SPI1TXD_NAME,0); - break; - } - case RK30_PIN0_PD6: - { - rk30_mux_api_set(GPIO0D6_SPI1CLK_NAME,0); - break; - } - case RK30_PIN0_PD7: - { - rk30_mux_api_set(GPIO0D7_SPI1CSN0_NAME,0); - break; + rk30_mux_api_set(GPIO0D7_PWM3_NAME,0); + break; } case RK30_PIN1_PA0: { @@ -968,418 +768,432 @@ static int rk_sensor_iomux(int pin) } case RK30_PIN1_PA4: { - rk30_mux_api_set(GPIO1A4_UART1SIN_SPI0RXD_NAME,0); + rk30_mux_api_set(GPIO1A4_UART1SIN_SPI0CSN0_NAME,0); break; } case RK30_PIN1_PA5: { - rk30_mux_api_set(GPIO1A5_UART1SOUT_SPI0TXD_NAME,0); + rk30_mux_api_set(GPIO1A5_UART1SOUT_SPI0CLK_NAME,0); break; } case RK30_PIN1_PA6: { - rk30_mux_api_set(GPIO1A6_UART1CTSN_SPI0CLK_NAME,0); + rk30_mux_api_set(GPIO1A6_UART1CTSN_SPI0RXD_NAME,0); break; } case RK30_PIN1_PA7: { - rk30_mux_api_set(GPIO1A7_UART1RTSN_SPI0CSN0_NAME,0); + rk30_mux_api_set(GPIO1A7_UART1RTSN_SPI0TXD_NAME,0); break; } case RK30_PIN1_PB0: { - rk30_mux_api_set(GPIO1B0_UART2SIN_JTAGTDI_NAME,0); + rk30_mux_api_set(GPIO1B0_UART2SIN_NAME,0); break; } case RK30_PIN1_PB1: { - rk30_mux_api_set(GPIO1B1_UART2SOUT_JTAGTDO_NAME,0); + rk30_mux_api_set(GPIO1B1_UART2SOUT_NAME,0); break; } case RK30_PIN1_PB2: { - rk30_mux_api_set(GPIO1B2_UART3SIN_GPSMAG_NAME,0); + rk30_mux_api_set(GPIO1B2_SPDIFTX_NAME,0); break; } case RK30_PIN1_PB3: { - rk30_mux_api_set(GPIO1B3_UART3SOUT_GPSSIG_NAME,0); + rk30_mux_api_set(GPIO1B3_CIF0CLKOUT_NAME,0); break; } case RK30_PIN1_PB4: { - rk30_mux_api_set(GPIO1B4_UART3CTSN_GPSRFCLK_NAME,0); + rk30_mux_api_set(GPIO1B4_CIF0DATA0_NAME,0); break; } case RK30_PIN1_PB5: { - rk30_mux_api_set(GPIO1B5_UART3RTSN_NAME,0); + rk30_mux_api_set(GPIO1B5_CIF0DATA1_NAME,0); break; } case RK30_PIN1_PB6: { - rk30_mux_api_set(GPIO1B6_SPDIFTX_SPI1CSN1_NAME,0); + rk30_mux_api_set(GPIO1B6_CIFDATA10_NAME,0); break; } case RK30_PIN1_PB7: { - rk30_mux_api_set(GPIO1B7_SPI0CSN1_NAME,0); + rk30_mux_api_set(GPIO1B7_CIFDATA11_NAME,0); break; } case RK30_PIN1_PC0: { - rk30_mux_api_set(GPIO1C0_I2SCLK_NAME,0); + rk30_mux_api_set(GPIO1C0_CIF1DATA2_RMIICLKOUT_RMIICLKIN_NAME,0); break; } case RK30_PIN1_PC1: { - rk30_mux_api_set(GPIO1C1_I2SSCLK_NAME,0); + rk30_mux_api_set(GPIO1C1_CIFDATA3_RMIITXEN_NAME,0); break; } case RK30_PIN1_PC2: { - rk30_mux_api_set(GPIO1C2_I2SLRCLKRX_NAME,0); + rk30_mux_api_set(GPIO1C2_CIF1DATA4_RMIITXD1_NAME,0); break; } case RK30_PIN1_PC3: { - rk30_mux_api_set(GPIO1C3_I2SLRCLKTX_NAME,0); + rk30_mux_api_set(GPIO1C3_CIFDATA5_RMIITXD0_NAME,0); break; } case RK30_PIN1_PC4: { - rk30_mux_api_set(GPIO1C4_I2SSDI_NAME,0); + rk30_mux_api_set(GPIO1C4_CIFDATA6_RMIIRXERR_NAME,0); break; } case RK30_PIN1_PC5: + { + rk29_mux_api_set(GPIO1C5_CIFDATA7_RMIICRSDVALID_NAME,0); + break; + } case RK30_PIN1_PC6: + { + rk30_mux_api_set(GPIO1C6_CIFDATA8_RMIIRXD1_NAME,0); + break; + } case RK30_PIN1_PC7: + { + rk30_mux_api_set(GPIO1C7_CIFDATA9_RMIIRXD0_NAME,0); break; + } case RK30_PIN1_PD0: { - rk30_mux_api_set(GPIO1D0_I2C0SDA_NAME,0); + rk30_mux_api_set(GPIO1D0_CIF1VSYNC_MIIMD_NAME,0); break; } case RK30_PIN1_PD1: { - rk30_mux_api_set(GPIO1D1_I2C0SCL_NAME,0); + rk30_mux_api_set(GPIO1D1_CIF1HREF_MIIMDCLK_NAME,0); break; } case RK30_PIN1_PD2: { - rk30_mux_api_set(GPIO1D2_I2C1SDA_NAME,0); + rk30_mux_api_set(GPIO1D2_CIF1CLKIN_NAME,0); break; } case RK30_PIN1_PD3: { - rk30_mux_api_set(GPIO1D3_I2C1SCL_NAME,0); + rk30_mux_api_set(GPIO1D3_CIF1DATA0_NAME,0); break; } case RK30_PIN1_PD4: { - rk30_mux_api_set(GPIO1D4_I2C2SDA_NAME,0); + rk30_mux_api_set(GPIO1D4_CIF1DATA1_NAME,0); break; } case RK30_PIN1_PD5: { - rk30_mux_api_set(GPIO1D5_I2C2SCL_NAME,0); + rk30_mux_api_set(GPIO1D5_CIF1DATA10_NAME,0); break; } case RK30_PIN1_PD6: { - rk30_mux_api_set(GPIO1D6_I2C4SDA_NAME,0); + rk30_mux_api_set(GPIO1D6_CIF1DATA11_NAME,0); break; } case RK30_PIN1_PD7: { - rk30_mux_api_set(GPIO1D7_I2C4SCL_NAME,0); + rk30_mux_api_set(GPIO1D7_CIF1CLKOUT_NAME,0); break; } case RK30_PIN2_PA0: { - rk30_mux_api_set(GPIO2A0_LCDC1DATA0_SMCDATA0_TRACEDATA0_NAME,0); + rk30_mux_api_set(GPIO2A0_LCDC1DATA0_SMCADDR4_NAME,0); break; } case RK30_PIN2_PA1: { - rk30_mux_api_set(GPIO2A1_LCDC1DATA1_SMCDATA1_TRACEDATA1_NAME,0); + rk30_mux_api_set(GPIO2A1_LCDC1DATA1_SMCADDR5_NAME,0); break; } case RK30_PIN2_PA2: { - rk30_mux_api_set(GPIO2A2_LCDC1DATA2_SMCDATA2_TRACEDATA2_NAME,0); + rk30_mux_api_set(GPIO2A2_LCDCDATA2_SMCADDR6_NAME,0); break; } case RK30_PIN2_PA3: { - rk30_mux_api_set(GPIO2A3_LCDC1DATA3_SMCDATA3_TRACEDATA3_NAME,0); + rk30_mux_api_set(GPIO2A3_LCDCDATA3_SMCADDR7_NAME,0); break; } case RK30_PIN2_PA4: { - rk30_mux_api_set(GPIO2A4_LCDC1DATA4_SMCDATA4_TRACEDATA4_NAME,0); + rk30_mux_api_set(GPIO2A4_LCDC1DATA4_SMCADDR8_NAME,0); break; } case RK30_PIN2_PA5: { - rk30_mux_api_set(GPIO2A5_LCDC1DATA5_SMCDATA5_TRACEDATA5_NAME,0); + rk30_mux_api_set(GPIO2A5_LCDC1DATA5_SMCADDR9_NAME,0); break; } case RK30_PIN2_PA6: { - rk30_mux_api_set(GPIO2A6_LCDC1DATA6_SMCDATA6_TRACEDATA6_NAME,0); + rk30_mux_api_set(GPIO2A6_LCDC1DATA6_SMCADDR10_NAME,0); break; } case RK30_PIN2_PA7: { - rk30_mux_api_set(GPIO2A7_LCDC1DATA7_SMCDATA7_TRACEDATA7_NAME,0); + rk30_mux_api_set(GPIO2A7_LCDC1DATA7_SMCADDR11_NAME,0); break; } case RK30_PIN2_PB0: { - rk30_mux_api_set(GPIO2B0_LCDC1DATA8_SMCDATA8_TRACEDATA8_NAME,0); + rk30_mux_api_set(GPIO2B0_LCDC1DATA8_SMCADDR12_NAME,0); break; } case RK30_PIN2_PB1: { - rk30_mux_api_set(GPIO2B1_LCDC1DATA9_SMCDATA9_TRACEDATA9_NAME,0); + rk30_mux_api_set(GPIO2B1_LCDC1DATA9_SMCADDR13_NAME,0); break; } case RK30_PIN2_PB2: { - rk30_mux_api_set(GPIO2B2_LCDC1DATA10_SMCDATA10_TRACEDATA10_NAME,0); + rk30_mux_api_set(GPIO2B2_LCDC1DATA10_SMCADDR14_NAME,0); break; } case RK30_PIN2_PB3: { - rk30_mux_api_set(GPIO2B3_LCDC1DATA11_SMCDATA11_TRACEDATA11_NAME,0); + rk30_mux_api_set(GPIO2B3_LCDC1DATA11_SMCADDR15_NAME,0); break; } case RK30_PIN2_PB4: { - rk30_mux_api_set(GPIO2B4_LCDC1DATA12_SMCDATA12_TRACEDATA12_NAME,0); + rk30_mux_api_set(GPIO2B4_LCDC1DATA12_SMCADDR16_HSADCDATA9_NAME,0); break; } case RK30_PIN2_PB5: { - rk30_mux_api_set(GPIO2B5_LCDC1DATA13_SMCDATA13_TRACEDATA13_NAME,0); + rk30_mux_api_set(GPIO2B5_LCDC1DATA13_SMCADDR17_HSADCDATA8_NAME,0); break; } case RK30_PIN2_PB6: { - rk30_mux_api_set(GPIO2B6_LCDC1DATA14_SMCDATA14_TRACEDATA14_NAME,0); + rk30_mux_api_set(GPIO2B6_LCDC1DATA14_SMCADDR18_TSSYNC_NAME,0); break; } case RK30_PIN2_PB7: { - rk30_mux_api_set(GPIO2B7_LCDC1DATA15_SMCDATA15_TRACEDATA15_NAME,0); + rk30_mux_api_set(GPIO2B7_LCDC1DATA15_SMCADDR19_HSADCDATA7_NAME,0); break; } case RK30_PIN2_PC0: { - rk30_mux_api_set(GPIO2C0_LCDC1DATA16_SMCADDR0_TRACECLK_NAME,0); + rk30_mux_api_set(GPIO2C0_LCDCDATA16_GPSCLK_HSADCCLKOUT_NAME,0); break; } case RK30_PIN2_PC1: { - rk30_mux_api_set(GPIO2C1_LCDC1DATA17_SMCADDR1_TRACECTL_NAME,0); + rk30_mux_api_set(GPIO2C1_LCDC1DATA17_SMCBLSN0_HSADCDATA6_NAME,0); break; } case RK30_PIN2_PC2: { - rk30_mux_api_set(GPIO2C2_LCDC1DATA18_SMCADDR2_NAME,0); + rk30_mux_api_set(GPIO2C2_LCDC1DATA18_SMCBLSN1_HSADCDATA5_NAME,0); break; } case RK30_PIN2_PC3: { - rk29_mux_api_set(GPIO2C3_LCDC1DATA19_SMCADDR3_NAME,0); + rk29_mux_api_set(GPIO2C3_LCDC1DATA19_SPI1CLK_HSADCDATA0_NAME,0); break; } case RK30_PIN2_PC4: { - rk30_mux_api_set(GPIO2C4_LCDC1DATA20_SMCADDR4_NAME,0); + rk30_mux_api_set(GPIO2C4_LCDC1DATA20_SPI1CSN0_HSADCDATA1_NAME,0); break; } case RK30_PIN2_PC5: { - rk30_mux_api_set(GPIO2C5_LCDC1DATA21_SMCADDR5_NAME,0); + rk30_mux_api_set(GPIO2C5_LCDC1DATA21_SPI1TXD_HSADCDATA2_NAME,0); break; } case RK30_PIN2_PC6: { - rk30_mux_api_set(GPIO2C6_LCDC1DATA22_SMCADDR6_NAME,0); + rk30_mux_api_set(GPIO2C6_LCDC1DATA22_SPI1RXD_HSADCDATA3_NAME,0); break; } case RK30_PIN2_PC7: { - rk30_mux_api_set(GPIO2C7_LCDC1DATA23_SMCADDR7_NAME,0); + rk30_mux_api_set(GPIO2C7_LCDC1DATA23_SPI1CSN1_HSADCDATA4_NAME,0); break; } case RK30_PIN2_PD0: { - rk30_mux_api_set(GPIO2D0_LCDC1DCLK_SMCCSN0_NAME,0); + rk30_mux_api_set(GPIO2D0_LCDC1DCLK_NAME,0); break; } case RK30_PIN2_PD1: { - rk30_mux_api_set(GPIO2D1_LCDC1DEN_SMCWEN_NAME,0); + rk30_mux_api_set(GPIO2D1_LCDC1DEN_SMCCSN1_NAME,0); break; } case RK30_PIN2_PD2: { - rk30_mux_api_set(GPIO2D2_LCDC1HSYNC_SMCOEN_NAME,0); + rk30_mux_api_set(GPIO2D2_LCDC1HSYNC_NAME,0); break; } case RK30_PIN2_PD3: { - rk30_mux_api_set(GPIO2D3_LCDC1VSYNC_SMCADVN_NAME,0); + rk30_mux_api_set(GPIO2D3_LCDC1VSYNC_NAME,0); break; } case RK30_PIN2_PD4: { - rk30_mux_api_set(GPIO2D4_SMCBLSN0_NAME,0); + rk30_mux_api_set(GPIO2D4_I2C0SDA_NAME,0); break; } case RK30_PIN2_PD5: { - rk30_mux_api_set(GPIO2D5_SMCBLSN1_NAME,0); + rk30_mux_api_set(GPIO2D5_I2C0SCL_NAME,0); break; } case RK30_PIN2_PD6: { - rk30_mux_api_set(GPIO2D6_SMCCSN1_NAME,0); + rk30_mux_api_set(GPIO2D6_I2C1SDA_NAME,0); break; } case RK30_PIN2_PD7: { - rk30_mux_api_set(GPIO2D7_TESTCLOCKOUT_NAME,0); + rk30_mux_api_set(GPIO2D7_I2C1SCL_NAME,0); break; } case RK30_PIN3_PA0: { - rk30_mux_api_set(GPIO3A0_SDMMC0RSTNOUT_NAME,0); + rk30_mux_api_set(GPIO3A0_I2C2SDA_NAME,0); break; } case RK30_PIN3_PA1: { - rk30_mux_api_set(GPIO3A1_SDMMC0PWREN_NAME,0); + rk30_mux_api_set(GPIO3A1_I2C2SCL_NAME,0); break; } case RK30_PIN3_PA2: { - rk30_mux_api_set(GPIO3A2_SDMMC0CLKOUT_NAME,0); + rk30_mux_api_set(GPIO3A2_I2C3SDA_NAME,0); break; } case RK30_PIN3_PA3: { - rk30_mux_api_set(GPIO3A3_SDMMC0CMD_NAME,0); + rk30_mux_api_set(GPIO3A3_I2C3SCL_NAME,0); break; } case RK30_PIN3_PA4: { - rk30_mux_api_set(GPIO3A4_SDMMC0DATA0_NAME,0); + rk30_mux_api_set(GPIO3A4_I2C4SDA_NAME,0); break; } case RK30_PIN3_PA5: { - rk30_mux_api_set(GPIO3A5_SDMMC0DATA1_NAME,0); + rk30_mux_api_set(GPIO3A5_I2C4SCL_NAME,0); break; } case RK30_PIN3_PA6: { - rk30_mux_api_set(GPIO3A6_SDMMC0DATA2_NAME,0); + rk30_mux_api_set(GPIO3A6_SDMMC0RSTNOUT_NAME,0); break; } case RK30_PIN3_PA7: { - rk30_mux_api_set(GPIO3A7_SDMMC0DATA3_NAME,0); + rk30_mux_api_set(GPIO3A7_SDMMC0PWREN_NAME,0); break; } case RK30_PIN3_PB0: { - rk30_mux_api_set(GPIO3B0_SDMMC0DETECTN_NAME,0); + rk30_mux_api_set(GPIO3B0_SDMMC0CLKOUT_NAME,0); break; } case RK30_PIN3_PB1: { - rk30_mux_api_set(GPIO3B1_SDMMC0WRITEPRT_NAME,0); + rk30_mux_api_set(GPIO3B1_SDMMC0CMD_NAME,0); + break; + } + case RK30_PIN3_PB2: + { + rk30_mux_api_set(GPIO3B2_SDMMC0DATA0_NAME,0); break; } - case RK30_PIN3_PB2: - break; case RK30_PIN3_PB3: { - rk30_mux_api_set(GPIO3B3_CIFCLKOUT_NAME,0); + rk30_mux_api_set(GPIO3B3_SDMMC0DATA1_NAME,0); break; } case RK30_PIN3_PB4: { - rk30_mux_api_set(GPIO3B4_CIFDATA0_HSADCDATA8_NAME,0); + rk30_mux_api_set(GPIO3B4_SDMMC0DATA2_NAME,0); break; } case RK30_PIN3_PB5: { - rk30_mux_api_set(GPIO3B5_CIFDATA1_HSADCDATA9_NAME,0); + rk30_mux_api_set(GPIO3B5_SDMMC0DATA3_NAME,0); break; } case RK30_PIN3_PB6: { - rk30_mux_api_set(GPIO3B6_CIFDATA10_I2C3SDA_NAME,0); + rk30_mux_api_set(GPIO3B6_SDMMC0DETECTN_NAME,0); break; } case RK30_PIN3_PB7: { - rk30_mux_api_set(GPIO3B7_CIFDATA11_I2C3SCL_NAME,0); + rk30_mux_api_set(GPIO3B7_SDMMC0WRITEPRT_NAME,0); break; } case RK30_PIN3_PC0: { - rk30_mux_api_set(GPIO3C0_SDMMC1CMD_RMIITXEN_NAME,0); + rk30_mux_api_set(GPIO3C0_SMMC1CMD_NAME,0); break; } case RK30_PIN3_PC1: { - rk30_mux_api_set(GPIO3C1_SDMMC1DATA0_RMIITXD1_NAME,0); + rk30_mux_api_set(GPIO3C1_SDMMC1DATA0_NAME,0); break; } case RK30_PIN3_PC2: { - rk30_mux_api_set(GPIO3C2_SDMMC1DATA1_RMIITXD0_NAME,0); + rk30_mux_api_set(GPIO3C2_SDMMC1DATA1_NAME,0); break; } case RK30_PIN3_PC3: { - rk30_mux_api_set(GPIO3C3_SDMMC1DATA2_RMIIRXD0_NAME,0); + rk30_mux_api_set(GPIO3C3_SDMMC1DATA2_NAME,0); break; } case RK30_PIN3_PC4: { - rk30_mux_api_set(GPIO3C4_SDMMC1DATA3_RMIIRXD1_NAME,0); + rk30_mux_api_set(GPIO3C4_SDMMC1DATA3_NAME,0); break; } case RK30_PIN3_PC5: { - rk30_mux_api_set(GPIO3C5_SDMMC1CLKOUT_RMIICLKOUT_RMIICLKIN_NAME,0); + rk30_mux_api_set(GPIO3C5_SDMMC1CLKOUT_NAME,0); break; } case RK30_PIN3_PC6: { - rk30_mux_api_set(GPIO3C6_SDMMC1DETECTN_RMIIRXERR_NAME,0); + rk30_mux_api_set(GPIO3C6_SDMMC1DETECTN_NAME,0); break; } case RK30_PIN3_PC7: { - rk30_mux_api_set(GPIO3C7_SDMMC1WRITEPRT_RMIICRS_NAME,0); + rk30_mux_api_set(GPIO3C7_SDMMC1WRITEPRT_NAME,0); break; } case RK30_PIN3_PD0: { - rk30_mux_api_set(GPIO3D0_SDMMC1PWREN_MIIMD_NAME,0); + rk30_mux_api_set(GPIO3D0_SDMMC1PWREN_NAME,0); break; } case RK30_PIN3_PD1: { - rk30_mux_api_set(GPIO3D1_SDMMC1BACKENDPWR_MIIMDCLK_NAME,0); + rk30_mux_api_set(GPIO3D1_SDMMC1BACKENDPWR_NAME,0); break; } case RK30_PIN3_PD2: @@ -1389,33 +1203,219 @@ static int rk_sensor_iomux(int pin) } case RK30_PIN3_PD3: { - rk30_mux_api_set(GPIO3D3_PWM0_NAME,0); + rk30_mux_api_set(GPIO3D3_UART3SIN_NAME,0); break; } case RK30_PIN3_PD4: { - rk30_mux_api_set(GPIO3D4_PWM1_JTAGTRSTN_NAME,0); + rk30_mux_api_set(GPIO3D4_UART3SOUT_NAME,0); break; } case RK30_PIN3_PD5: { - rk30_mux_api_set(GPIO3D5_PWM2_JTAGTCK_OTGDRVVBUS_NAME,0); + rk30_mux_api_set(GPIO3D5_UART3CTSN_NAME,0); break; } case RK30_PIN3_PD6: { - rk30_mux_api_set(GPIO3D6_PWM3_JTAGTMS_HOSTDRVVBUS_NAME,0); + rk30_mux_api_set(GPIO3D6_UART3RTSN_NAME,0); break; } - case RK30_PIN3_PD7: - break; + case RK30_PIN3_PD7: + { + rk30_mux_api_set(GPIO3D7_FLASHDQS_EMMCCLKOUT_NAME,0); + break; + } + case RK30_PIN4_PA0: + { + rk30_mux_api_set(GPIO4A0_FLASHDATA8_NAME,0); + break; + } + case RK30_PIN4_PA1: + { + rk30_mux_api_set(GPIO4A1_FLASHDATA9_NAME,0); + break; + } + case RK30_PIN4_PA2: + { + rk30_mux_api_set(GPIO4A2_FLASHDATA10_NAME,0); + break; + } + + case RK30_PIN4_PA3: + { + rk30_mux_api_set(GPIO4A3_FLASHDATA11_NAME,0); + break; + } + case RK30_PIN4_PA4: + { + rk30_mux_api_set(GPIO4A4_FLASHDATA12_NAME,0); + break; + } + case RK30_PIN4_PA5: + { + rk30_mux_api_set(GPIO4A5_FLASHDATA13_NAME,0); + break; + } + case RK30_PIN4_PA6: + { + rk30_mux_api_set(GPIO4A6_FLASHDATA14_NAME,0); + break; + } + case RK30_PIN4_PA7: + { + rk30_mux_api_set(GPIO4A7_FLASHDATA15_NAME,0); + break; + } + case RK30_PIN4_PB0: + { + rk30_mux_api_set(GPIO4B0_FLASHCSN1_NAME,0); + break; + } + case RK30_PIN4_PB1: + { + rk30_mux_api_set(GPIO4B1_FLASHCSN2_EMMCCMD_NAME,0); + break; + } + case RK30_PIN4_PB2: + { + rk30_mux_api_set(GPIO4B2_FLASHCSN3_EMMCRSTNOUT_NAME,0); + break; + } + case RK30_PIN4_PB3: + { + rk30_mux_api_set(GPIO4B3_FLASHCSN4_NAME,0); + break; + } + case RK30_PIN4_PB4: + { + rk30_mux_api_set(GPIO4B4_FLASHCSN5_NAME,0); + break; + } + case RK30_PIN4_PB5: + { + rk30_mux_api_set(GPIO4B5_FLASHCSN6_NAME,0); + break; + } + case RK30_PIN4_PB6: + { + rk30_mux_api_set(GPIO4B6_FLASHCSN7_NAME ,0); + break; + } + case RK30_PIN4_PB7: + { + rk30_mux_api_set(GPIO4B7_SPI0CSN1_NAME,0); + break; + } + case RK30_PIN4_PC0: + { + rk30_mux_api_set(GPIO4C0_SMCDATA0_TRACEDATA0_NAME,0); + break; + } + case RK30_PIN4_PC1: + { + rk30_mux_api_set(GPIO4C1_SMCDATA1_TRACEDATA1_NAME,0); + break; + } + case RK30_PIN4_PC2: + { + rk30_mux_api_set(GPIO4C2_SMCDATA2_TRACEDATA2_NAME,0); + break; + } + case RK30_PIN4_PC3: + { + rk30_mux_api_set(GPIO4C3_SMCDATA3_TRACEDATA3_NAME,0); + break; + } + case RK30_PIN4_PC4: + { + rk30_mux_api_set(GPIO4C4_SMCDATA4_TRACEDATA4_NAME,0); + break; + } + case RK30_PIN4_PC5: + { + rk30_mux_api_set(GPIO4C5_SMCDATA5_TRACEDATA5_NAME,0); + break; + } + case RK30_PIN4_PC6: + { + rk30_mux_api_set(GPIO4C6_SMCDATA6_TRACEDATA6_NAME,0); + break; + } + + + case RK30_PIN4_PC7: + { + rk30_mux_api_set(GPIO4C7_SMCDATA7_TRACEDATA7_NAME,0); + break; + } + case RK30_PIN4_PD0: + { + rk30_mux_api_set(GPIO4D0_SMCDATA8_TRACEDATA8_NAME,0); + break; + } + case RK30_PIN4_PD1: + { + rk30_mux_api_set(GPIO4D1_SMCDATA9_TRACEDATA9_NAME,0); + break; + } + case RK30_PIN4_PD2: + { + rk30_mux_api_set(GPIO4D2_SMCDATA10_TRACEDATA10_NAME,0); + break; + } + case RK30_PIN4_PD3: + { + rk30_mux_api_set(GPIO4D3_SMCDATA11_TRACEDATA11_NAME,0); + break; + } + case RK30_PIN4_PD4: + { + rk30_mux_api_set(GPIO4D4_SMCDATA12_TRACEDATA12_NAME,0); + break; + } + case RK30_PIN4_PD5: + { + rk30_mux_api_set(GPIO4D5_SMCDATA13_TRACEDATA13_NAME,0); + break; + } + case RK30_PIN4_PD6: + { + rk30_mux_api_set(GPIO4D6_SMCDATA14_TRACEDATA14_NAME,0); + break; + } + case RK30_PIN4_PD7: + { + rk30_mux_api_set(GPIO4D7_SMCDATA15_TRACEDATA15_NAME,0); + break; + } + case RK30_PIN6_PA0: + case RK30_PIN6_PA1: + case RK30_PIN6_PA2: + case RK30_PIN6_PA3: + case RK30_PIN6_PA4: + case RK30_PIN6_PA5: + case RK30_PIN6_PA6: + case RK30_PIN6_PA7: + case RK30_PIN6_PB0: + case RK30_PIN6_PB1: + case RK30_PIN6_PB2: + case RK30_PIN6_PB3: + case RK30_PIN6_PB4: + case RK30_PIN6_PB5: + case RK30_PIN6_PB6: + break; + case RK30_PIN6_PB7: + { + rk30_mux_api_set(GPIO6B7_TESTCLOCKOUT_NAME,0); + break; + } default: { printk("Pin=%d isn't RK GPIO, Please init it's iomux yourself!",pin); break; } } - #endif return 0; } diff --git a/drivers/media/video/rk30_camera_oneframe.c b/drivers/media/video/rk30_camera_oneframe.c index e4ec396482c5..686795496247 100755 --- a/drivers/media/video/rk30_camera_oneframe.c +++ b/drivers/media/video/rk30_camera_oneframe.c @@ -9,7 +9,7 @@ * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. */ -#if defined(CONFIG_ARCH_RK2928) || defined(CONFIG_ARCH_RK30) || defined(CONFIG_ARCH_RK31) +#if defined(CONFIG_ARCH_RK2928) || defined(CONFIG_ARCH_RK30) #include #include #include @@ -40,7 +40,7 @@ #include #include #include "../../video/rockchip/rga/rga.h" -#if defined(CONFIG_ARCH_RK30) || defined(CONFIG_ARCH_RK31) +#if defined(CONFIG_ARCH_RK30) #include #include #include @@ -148,7 +148,7 @@ module_param(debug, int, S_IRUGO|S_IWUSR); #define ENABLE_32BIT_BYPASS (0x01<<6) #define DISABLE_32BIT_BYPASS (0x00<<6) -#if (defined(CONFIG_ARCH_RK30) || defined(CONFIG_ARCH_RK31)) +#if defined(CONFIG_ARCH_RK30) //CRU,PIXCLOCK #define CRU_PCLK_REG30 0xbc #define ENANABLE_INVERT_PCLK_CIF0 ((0x1<<24)|(0x1<<8)) @@ -172,7 +172,7 @@ module_param(debug, int, S_IRUGO|S_IWUSR); #define read_cif_reg(base,addr) __raw_readl(addr+(base)) #define mask_cif_reg(addr, msk, val) write_cif_reg(addr, (val)|((~(msk))&read_cif_reg(addr))) -#if (defined(CONFIG_ARCH_RK30) || defined(CONFIG_ARCH_RK31)) +#if defined(CONFIG_ARCH_RK30) #define write_cru_reg(addr, val) __raw_writel(val, addr+RK30_CRU_BASE) #define read_cru_reg(addr) __raw_readl(addr+RK30_CRU_BASE) #define mask_cru_reg(addr, msk, val) write_cru_reg(addr,(val)|((~(msk))&read_cru_reg(addr))) @@ -2818,7 +2818,8 @@ static struct soc_camera_host_ops rk_soc_camera_host_ops = }; static void rk_camera_cif_iomux(int cif_index) { -#ifdef CONFIG_ARCH_RK30 +#if defined(CONFIG_ARCH_RK3066B) +#elif defined(CONFIG_ARCH_RK30) switch(cif_index){ case 0: rk30_mux_api_set(GPIO1B3_CIF0CLKOUT_NAME, GPIO1B_CIF0_CLKOUT); diff --git a/drivers/mmc/host/rk29_sdmmc.c b/drivers/mmc/host/rk29_sdmmc.c index 7e5c999f65ae..10b3a58fa8a6 100755 --- a/drivers/mmc/host/rk29_sdmmc.c +++ b/drivers/mmc/host/rk29_sdmmc.c @@ -72,15 +72,15 @@ int debug_level = 5; #if defined(CONFIG_ARCH_RK29) #define RK29_SDMMC0DETECTN_GPIO RK29_PIN2_PA2 #define RK29_SDMMC0PWREN_GPIO RK29_PIN5_PD5 +#elif defined(CONFIG_ARCH_RK3066B) + #define RK29_SDMMC0DETECTN_GPIO RK30_PIN3_PB0 + #define RK29_SDMMC0PWREN_GPIO RK30_PIN3_PA1 #elif defined(CONFIG_ARCH_RK30) #define RK29_SDMMC0DETECTN_GPIO RK30_PIN3_PB6 #define RK29_SDMMC0PWREN_GPIO RK30_PIN3_PA7 #elif defined(CONFIG_ARCH_RK2928) #define RK29_SDMMC0DETECTN_GPIO RK2928_PIN1_PC7 #define RK29_SDMMC0PWREN_GPIO RK2928_PIN1_PB6 -#elif defined(CONFIG_ARCH_RK31) - #define RK29_SDMMC0DETECTN_GPIO RK30_PIN3_PB0 - #define RK29_SDMMC0PWREN_GPIO RK30_PIN3_PA1 #endif #define RK29_SDMMC_ERROR_FLAGS (SDMMC_INT_FRUN | SDMMC_INT_HLE ) @@ -3786,12 +3786,12 @@ static int rk29_sdmmc_sdcard_suspend(struct rk29_sdmmc *host) #if defined(CONFIG_ARCH_RK29) rk29_mux_api_set(GPIO2A2_SDMMC0DETECTN_NAME, GPIO2L_GPIO2A2); +#elif defined(CONFIG_ARCH_RK3066B) + rk29_mux_api_set(GPIO3B0_SDMMC0DETECTN_NAME, GPIO3B_GPIO3B0); #elif defined(CONFIG_ARCH_RK30) rk29_mux_api_set(GPIO3B6_SDMMC0DETECTN_NAME, GPIO3B_GPIO3B6); #elif defined(CONFIG_ARCH_RK2928) rk29_mux_api_set(GPIO1C1_MMC0_DETN_NAME, GPIO1C_GPIO1C1); -#elif defined(CONFIG_ARCH_RK31) - rk29_mux_api_set(GPIO3B0_SDMMC0DETECTN_NAME, GPIO3B_GPIO3B0); #endif gpio_request(RK29_SDMMC0DETECTN_GPIO, "sd_detect"); @@ -3815,12 +3815,12 @@ static void rk29_sdmmc_sdcard_resume(struct rk29_sdmmc *host) #if defined(CONFIG_ARCH_RK29) rk29_mux_api_set(GPIO2A2_SDMMC0DETECTN_NAME, GPIO2L_SDMMC0_DETECT_N); +#elif defined(CONFIG_ARCH_RK3066B) + rk29_mux_api_set(GPIO3B0_SDMMC0DETECTN_NAME, GPIO3B_SDMMC0DETECTN); #elif defined(CONFIG_ARCH_RK30) rk29_mux_api_set(GPIO3B6_SDMMC0DETECTN_NAME, GPIO3B_SDMMC0_DETECT_N); #elif defined(CONFIG_ARCH_RK2928) rk29_mux_api_set(GPIO1C1_MMC0_DETN_NAME, GPIO1C_MMC0_DETN); -#elif defined(CONFIG_ARCH_RK31) - rk29_mux_api_set(GPIO3B0_SDMMC0DETECTN_NAME, GPIO3B_SDMMC0DETECTN); #endif } diff --git a/drivers/regulator/rk30-pwm-regulator.c b/drivers/regulator/rk30-pwm-regulator.c index 2019ef5a264c..ff459c706ea9 100755 --- a/drivers/regulator/rk30-pwm-regulator.c +++ b/drivers/regulator/rk30-pwm-regulator.c @@ -87,7 +87,7 @@ static int pwm_set_rate(struct pwm_platform_data *pdata,int nHz,u32 rate) #if defined(CONFIG_ARCH_RK29) || defined(CONFIG_ARCH_RK2928) clkrate = clk_get_rate(pwm_clk[0]); -#elif defined(CONFIG_ARCH_RK30) || defined(CONFIG_ARCH_RK31) +#elif defined(CONFIG_ARCH_RK30) if (id == 0 || id == 1) { clkrate = clk_get_rate(pwm_clk[0]); } else if (id== 2 || id == 3) { diff --git a/drivers/usb/dwc_otg/dwc_otg_driver.c b/drivers/usb/dwc_otg/dwc_otg_driver.c index 0e47b5fd99e7..6bbdcdf21e40 100755 --- a/drivers/usb/dwc_otg/dwc_otg_driver.c +++ b/drivers/usb/dwc_otg/dwc_otg_driver.c @@ -1583,7 +1583,8 @@ static __devinit int dwc_otg_driver_probe(struct platform_device *pdev) #ifdef CONFIG_ARCH_RK29 USB_IOMUX_INIT(GPIO4A5_OTG0DRVVBUS_NAME, GPIO4L_OTG0_DRV_VBUS); #endif -#ifdef CONFIG_ARCH_RK30 +#if defined(CONFIG_ARCH_RK3066B) +#elif defined(CONFIG_ARCH_RK30) USB_IOMUX_INIT(GPIO0A5_OTGDRVVBUS_NAME, GPIO0A_OTG_DRV_VBUS); #endif #ifdef CONFIG_ARCH_RK2928 @@ -2278,7 +2279,8 @@ static __devinit int host20_driver_probe(struct platform_device *pdev) #ifdef CONFIG_ARCH_RK29 USB_IOMUX_INIT(GPIO4A6_OTG1DRVVBUS_NAME, GPIO4L_OTG1_DRV_VBUS); #endif -#ifdef CONFIG_ARCH_RK30 +#if defined(CONFIG_ARCH_RK3066B) +#elif defined(CONFIG_ARCH_RK30) USB_IOMUX_INIT(GPIO0A6_HOSTDRVVBUS_NAME, GPIO0A_HOST_DRV_VBUS); #endif /* diff --git a/drivers/video/backlight/rk29_backlight.c b/drivers/video/backlight/rk29_backlight.c index 1d151b35229b..ee8cd6047856 100755 --- a/drivers/video/backlight/rk29_backlight.c +++ b/drivers/video/backlight/rk29_backlight.c @@ -38,7 +38,7 @@ #define DBG(x...) #endif -#if defined(CONFIG_ARCH_RK30) || defined(CONFIG_ARCH_RK31) +#if defined(CONFIG_ARCH_RK30) #define write_pwm_reg(id, addr, val) __raw_writel(val, addr+(RK30_PWM01_BASE+(id>>1)*0x20000)+id*0x10) #define read_pwm_reg(id, addr) __raw_readl(addr+(RK30_PWM01_BASE+(id>>1)*0x20000+id*0x10)) @@ -238,7 +238,7 @@ static int rk29_backlight_probe(struct platform_device *pdev) #if defined(CONFIG_ARCH_RK29) pwm_clk = clk_get(NULL, "pwm"); -#elif defined(CONFIG_ARCH_RK30) || defined(CONFIG_ARCH_RK31) || defined(CONFIG_ARCH_RK2928) +#elif defined(CONFIG_ARCH_RK30) || defined(CONFIG_ARCH_RK2928) if (id == 0 || id == 1) pwm_clk = clk_get(NULL, "pwm01"); else if (id == 2 || id == 3) diff --git a/drivers/video/rockchip/Kconfig b/drivers/video/rockchip/Kconfig index 44135b06fb19..49e959e9301e 100755 --- a/drivers/video/rockchip/Kconfig +++ b/drivers/video/rockchip/Kconfig @@ -41,24 +41,24 @@ config LCDC1_RK30 Support rk30 lcdc1 if you say y here config LCDC_RK31 - tristate "rk31 lcdc support" - depends on FB_ROCKCHIP && ARCH_RK31 + tristate "rk3066b/rk31 lcdc support" + depends on FB_ROCKCHIP && ARCH_RK3066B help - Driver for rk31 lcdc .There are two lcdc controllers on RK31 + Driver for rk3066b/rk31 lcdc. config LCDC0_RK31 bool "lcdc0 support" depends on LCDC_RK31 default y help - Support rk31 lcdc0 if you say y here + Support lcdc0 if you say y here config LCDC1_RK31 bool "lcdc1 support" depends on LCDC_RK31 default y if HDMI_RK31 help - Support rk31 lcdc1 if you say y here + Support lcdc1 if you say y here config DUAL_DISP_IN_KERNEL bool "implement dual display in kernel" diff --git a/drivers/video/rockchip/rga/Kconfig b/drivers/video/rockchip/rga/Kconfig index 305130cac236..152e2bd55ef0 100755 --- a/drivers/video/rockchip/rga/Kconfig +++ b/drivers/video/rockchip/rga/Kconfig @@ -1,8 +1,8 @@ menu "RGA" - depends on ARCH_RK30 || ARCH_RK2928 || ARCH_RK31 + depends on ARCH_RK30 || ARCH_RK2928 config RGA_RK30 - tristate "ROCKCHIP RK30 || RK2928 RGA || RK31 RGA " + tristate "ROCKCHIP RK30 || RK2928 RGA" help rk30 rga module. diff --git a/drivers/video/rockchip/rga/rga.h b/drivers/video/rockchip/rga/rga.h index 2623d6dd1e9b..bbf5fa94833d 100755 --- a/drivers/video/rockchip/rga/rga.h +++ b/drivers/video/rockchip/rga/rga.h @@ -390,8 +390,6 @@ typedef struct rga_service_info { #define RGA_BASE 0x1010c000 #elif defined(CONFIG_ARCH_RK30) #define RGA_BASE 0x10114000 -#elif defined(CONFIG_ARCH_RK31) -#define RGA_BASE 0x10114000 #endif //General Registers diff --git a/sound/soc/codecs/rk610_codec.c b/sound/soc/codecs/rk610_codec.c index 70ce8727422b..5820a788e99d 100755 --- a/sound/soc/codecs/rk610_codec.c +++ b/sound/soc/codecs/rk610_codec.c @@ -42,10 +42,10 @@ //you can look soc-core.c the resume source.s #define RESUME_PROBLEM 0 -#ifdef CONFIG_ARCH_RK30 -#define RK610_SPK_CTRL_PIN RK30_PIN4_PC6 -#elif defined(CONFIG_ARCH_RK31) +#if defined(CONFIG_ARCH_RK3066B) #define RK610_SPK_CTRL_PIN RK30_PIN2_PA0 +#elif defined(CONFIG_ARCH_RK30) +#define RK610_SPK_CTRL_PIN RK30_PIN4_PC6 #else #define RK610_SPK_CTRL_PIN RK29_PIN6_PB6 #endif @@ -906,4 +906,4 @@ static int RK610_PROC_init(void) return 0; } -#endif \ No newline at end of file +#endif diff --git a/sound/soc/rk29/Kconfig b/sound/soc/rk29/Kconfig index 6cde11914664..d54108faf554 100755 --- a/sound/soc/rk29/Kconfig +++ b/sound/soc/rk29/Kconfig @@ -12,7 +12,7 @@ config SND_RK29_SOC_I2S config SND_RK29_SOC_I2S_8CH bool "Soc RK29 I2S 8 Channel support(I2S0)" default y - depends on SND_RK29_SOC_I2S && !ARCH_RK31 + depends on SND_RK29_SOC_I2S && !ARCH_RK3066B help This supports the use of the 8 Channel I2S interface on rk29 processors. diff --git a/sound/soc/rk29/Makefile b/sound/soc/rk29/Makefile index 51c4a44de8b7..e20e36607497 100755 --- a/sound/soc/rk29/Makefile +++ b/sound/soc/rk29/Makefile @@ -9,9 +9,6 @@ endif ifdef CONFIG_ARCH_RK2928 snd-soc-rockchip-i2s-objs := rk30_i2s.o endif -ifdef CONFIG_ARCH_RK31 -snd-soc-rockchip-i2s-objs := rk30_i2s.o -endif snd-soc-rockchip-spdif-objs := rk29_spdif.o obj-$(CONFIG_SND_RK29_SOC) += snd-soc-rockchip.o diff --git a/sound/soc/rk29/rk30_i2s.c b/sound/soc/rk29/rk30_i2s.c index 7c5bd15adc67..ad474d44d4ae 100755 --- a/sound/soc/rk29/rk30_i2s.c +++ b/sound/soc/rk29/rk30_i2s.c @@ -490,7 +490,8 @@ static int rockchip_i2s_dai_probe(struct snd_soc_dai *dai) { I2S_DBG("Enter %s, %d >>>>>>>>>>>\n", __func__, __LINE__); switch(dai->id) { -#ifdef CONFIG_ARCH_RK30 +#if defined(CONFIG_ARCH_RK3066B) +#elif defined(CONFIG_ARCH_RK30) case 0: rk30_mux_api_set(GPIO0A7_I2S8CHSDI_NAME, GPIO0A_I2S_8CH_SDI); rk30_mux_api_set(GPIO0B0_I2S8CHCLK_NAME, GPIO0B_I2S_8CH_CLK); -- 2.34.1