From 4db3748fcf39ac0001b9d02eb6bf803e309a5c19 Mon Sep 17 00:00:00 2001 From: Evan Cheng Date: Mon, 27 Jun 2011 23:47:21 +0000 Subject: [PATCH] Remove RCBarriers from TargetInstrDesc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133964 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/Target/TargetInstrDesc.h | 12 ------ utils/TableGen/InstrInfoEmitter.cpp | 56 +-------------------------- utils/TableGen/InstrInfoEmitter.h | 1 - 3 files changed, 1 insertion(+), 68 deletions(-) diff --git a/include/llvm/Target/TargetInstrDesc.h b/include/llvm/Target/TargetInstrDesc.h index ecd2acc9939..6a540ab7cb2 100644 --- a/include/llvm/Target/TargetInstrDesc.h +++ b/include/llvm/Target/TargetInstrDesc.h @@ -130,7 +130,6 @@ public: uint64_t TSFlags; // Target Specific Flag values const unsigned *ImplicitUses; // Registers implicitly read by this instr const unsigned *ImplicitDefs; // Registers implicitly defined by this instr - const TargetRegisterClass **RCBarriers; // Reg classes completely "clobbered" const TargetOperandInfo *OpInfo; // 'NumOperands' entries about operands /// getOperandConstraint - Returns the value of the specific constraint if @@ -251,17 +250,6 @@ public: return false; } - /// getRegClassBarriers - Return a list of register classes that are - /// completely clobbered by this machine instruction. For example, on X86 - /// the call instructions will completely clobber all the registers in the - /// fp stack and XMM classes. - /// - /// This method returns null if the instruction doesn't completely clobber - /// any register class. - const TargetRegisterClass **getRegClassBarriers() const { - return RCBarriers; - } - /// getSchedClass - Return the scheduling class for this instruction. The /// scheduling class is an index into the InstrItineraryData table. This /// returns zero if there is no known scheduling information for the diff --git a/utils/TableGen/InstrInfoEmitter.cpp b/utils/TableGen/InstrInfoEmitter.cpp index 6a96696b24d..22c100451e4 100644 --- a/utils/TableGen/InstrInfoEmitter.cpp +++ b/utils/TableGen/InstrInfoEmitter.cpp @@ -27,14 +27,6 @@ static void PrintDefList(const std::vector &Uses, OS << "0 };\n"; } -static void PrintBarriers(std::vector &Barriers, - unsigned Num, raw_ostream &OS) { - OS << "static const TargetRegisterClass* Barriers" << Num << "[] = { "; - for (unsigned i = 0, e = Barriers.size(); i != e; ++i) - OS << "&" << getQualifiedName(Barriers[i]) << "RegClass, "; - OS << "NULL };\n"; -} - //===----------------------------------------------------------------------===// // Instruction Itinerary Information. //===----------------------------------------------------------------------===// @@ -158,33 +150,6 @@ void InstrInfoEmitter::EmitOperandInfo(raw_ostream &OS, } } -void InstrInfoEmitter::DetectRegisterClassBarriers(std::vector &Defs, - const std::vector &RCs, - std::vector &Barriers) { - std::set DefSet; - unsigned NumDefs = Defs.size(); - for (unsigned i = 0; i < NumDefs; ++i) - DefSet.insert(Defs[i]); - - for (unsigned i = 0, e = RCs.size(); i != e; ++i) { - const CodeGenRegisterClass &RC = RCs[i]; - ArrayRef Order = RC.getOrder(); - if (Order.size() > NumDefs) - continue; // Can't possibly clobber this RC. - - bool Clobber = true; - for (unsigned j = 0; j < Order.size(); ++j) { - Record *Reg = Order[j]; - if (!DefSet.count(Reg)) { - Clobber = false; - break; - } - } - if (Clobber) - Barriers.push_back(RC.TheDef); - } -} - //===----------------------------------------------------------------------===// // Main Output. //===----------------------------------------------------------------------===// @@ -199,14 +164,10 @@ void InstrInfoEmitter::run(raw_ostream &OS) { CodeGenTarget &Target = CDP.getTargetInfo(); const std::string &TargetName = Target.getName(); Record *InstrInfo = Target.getInstructionSet(); - const std::vector &RCs = Target.getRegisterClasses(); // Keep track of all of the def lists we have emitted already. std::map, unsigned> EmittedLists; unsigned ListNumber = 0; - std::map, unsigned> EmittedBarriers; - unsigned BarrierNumber = 0; - std::map BarriersMap; // Emit all of the instruction's implicit uses and defs. for (CodeGenTarget::inst_iterator II = Target.inst_begin(), @@ -219,14 +180,6 @@ void InstrInfoEmitter::run(raw_ostream &OS) { } std::vector Defs = Inst->getValueAsListOfDefs("Defs"); if (!Defs.empty()) { - std::vector RCBarriers; - DetectRegisterClassBarriers(Defs, RCs, RCBarriers); - if (!RCBarriers.empty()) { - unsigned &IB = EmittedBarriers[RCBarriers]; - if (!IB) PrintBarriers(RCBarriers, IB = ++BarrierNumber, OS); - BarriersMap.insert(std::make_pair(Inst, IB)); - } - unsigned &IL = EmittedLists[Defs]; if (!IL) PrintDefList(Defs, IL = ++ListNumber, OS); } @@ -246,7 +199,7 @@ void InstrInfoEmitter::run(raw_ostream &OS) { for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) emitRecord(*NumberedInstructions[i], i, InstrInfo, EmittedLists, - BarriersMap, OperandInfoIDs, OS); + OperandInfoIDs, OS); OS << "};\n"; OS << "} // End llvm namespace \n"; } @@ -254,7 +207,6 @@ void InstrInfoEmitter::run(raw_ostream &OS) { void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num, Record *InstrInfo, std::map, unsigned> &EmittedLists, - std::map &BarriersMap, const OperandInfoMapTy &OpInfo, raw_ostream &OS) { int MinOperands = 0; @@ -322,12 +274,6 @@ void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num, else OS << "ImplicitList" << EmittedLists[DefList] << ", "; - std::map::iterator BI = BarriersMap.find(Inst.TheDef); - if (BI == BarriersMap.end()) - OS << "NULL, "; - else - OS << "Barriers" << BI->second << ", "; - // Emit the operand info. std::vector OperandInfo = GetOperandInfo(Inst); if (OperandInfo.empty()) diff --git a/utils/TableGen/InstrInfoEmitter.h b/utils/TableGen/InstrInfoEmitter.h index abb1c6bc188..41672ccd287 100644 --- a/utils/TableGen/InstrInfoEmitter.h +++ b/utils/TableGen/InstrInfoEmitter.h @@ -44,7 +44,6 @@ private: void emitRecord(const CodeGenInstruction &Inst, unsigned Num, Record *InstrInfo, std::map, unsigned> &EL, - std::map &BM, const OperandInfoMapTy &OpInfo, raw_ostream &OS); -- 2.34.1