From 4e378c6504958edb0f1a2f979248b2b09755066a Mon Sep 17 00:00:00 2001 From: Duraid Madina Date: Wed, 27 Jun 2007 08:11:59 +0000 Subject: [PATCH] revert evan's fixes (and my doofusness) since they had a huge code quality hit. will look at this soon. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37748 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/CodeGen/RegAllocBigBlock.cpp | 94 +++++++++++--------------------- 1 file changed, 31 insertions(+), 63 deletions(-) diff --git a/lib/CodeGen/RegAllocBigBlock.cpp b/lib/CodeGen/RegAllocBigBlock.cpp index e2f160f39ea..e4bbcd8e7a4 100644 --- a/lib/CodeGen/RegAllocBigBlock.cpp +++ b/lib/CodeGen/RegAllocBigBlock.cpp @@ -47,7 +47,6 @@ #include "llvm/ADT/SmallPtrSet.h" #include "llvm/ADT/Statistic.h" #include -#include using namespace llvm; STATISTIC(NumStores, "Number of stores added"); @@ -358,7 +357,18 @@ void RABigBlock::spillPhysReg(MachineBasicBlock &MBB, MachineInstr *I, *AliasSet; ++AliasSet) if (PhysRegsUsed[*AliasSet] != -1 && // Spill aliased register. PhysRegsUsed[*AliasSet] != -2) // If allocatable. - if (PhysRegsUsed[*AliasSet]) + if (PhysRegsUsed[*AliasSet] == 0) { + // This must have been a dead def due to something like this: + // %EAX := + // := op %AL + // No more use of %EAX, %AH, etc. + // %EAX isn't dead upon definition, but %AH is. However %AH isn't + // an operand of definition MI so it's not marked as such. + DOUT << " Register " << RegInfo->getName(*AliasSet) + << " [%reg" << *AliasSet + << "] is never used, removing it frame live list\n"; + removePhysReg(*AliasSet); + } else spillVirtReg(MBB, I, PhysRegsUsed[*AliasSet], *AliasSet); } } @@ -460,8 +470,8 @@ unsigned RABigBlock::chooseReg(MachineBasicBlock &MBB, MachineInstr *I, } } } - - assert(PhysReg && "couldn't assign a physical register :( "); + + assert(PhysReg && "couldn't grab a register from the table?"); // TODO: assert that RC->contains(PhysReg) / handle aliased registers // since we needed to look in the table we need to spill this register. @@ -572,29 +582,6 @@ void RABigBlock::FillVRegReadTable(MachineBasicBlock &MBB) { } } -/// isReadModWriteImplicitKill - True if this is an implicit kill for a -/// read/mod/write register, i.e. update partial register. -static bool isReadModWriteImplicitKill(MachineInstr *MI, unsigned Reg) { - for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { - MachineOperand& MO = MI->getOperand(i); - if (MO.isRegister() && MO.getReg() == Reg && MO.isImplicit() && - MO.isDef() && !MO.isDead()) - return true; - } - return false; -} - -/// isReadModWriteImplicitDef - True if this is an implicit def for a -/// read/mod/write register, i.e. update partial register. -static bool isReadModWriteImplicitDef(MachineInstr *MI, unsigned Reg) { - for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { - MachineOperand& MO = MI->getOperand(i); - if (MO.isRegister() && MO.getReg() == Reg && MO.isImplicit() && - !MO.isDef() && MO.isKill()) - return true; - } - return false; -} void RABigBlock::AllocateBasicBlock(MachineBasicBlock &MBB) { // loop over each instruction @@ -612,7 +599,7 @@ void RABigBlock::AllocateBasicBlock(MachineBasicBlock &MBB) { unsigned Reg = I->first; MF->setPhysRegUsed(Reg); PhysRegsUsed[Reg] = 0; // It is free and reserved now - for (const unsigned *AliasSet = RegInfo->getSubRegisters(Reg); + for (const unsigned *AliasSet = RegInfo->getAliasSet(Reg); *AliasSet; ++AliasSet) { if (PhysRegsUsed[*AliasSet] != -2) { PhysRegsUsed[*AliasSet] = 0; // It is free and reserved now @@ -623,10 +610,12 @@ void RABigBlock::AllocateBasicBlock(MachineBasicBlock &MBB) { } // Otherwise, sequentially allocate each instruction in the MBB. + MBBCurTime = -1; while (MII != MBB.end()) { MachineInstr *MI = MII++; + MBBCurTime++; const TargetInstrDescriptor &TID = TII.get(MI->getOpcode()); - DEBUG(DOUT << "\nStarting RegAlloc of: " << *MI; + DEBUG(DOUT << "\nTime=" << MBBCurTime << " Starting RegAlloc of: " << *MI; DOUT << " Regs have values: "; for (unsigned i = 0; i != RegInfo->getNumRegs(); ++i) if (PhysRegsUsed[i] != -1 && PhysRegsUsed[i] != -2) @@ -634,28 +623,11 @@ void RABigBlock::AllocateBasicBlock(MachineBasicBlock &MBB) { << ",%reg" << PhysRegsUsed[i] << "] "; DOUT << "\n"); -/* XXX : - // Loop over the implicit uses, making sure that they are at the head of the - // use order list, so they don't get reallocated. - if (TID.ImplicitUses) { - for (const unsigned *ImplicitUses = TID.ImplicitUses; - *ImplicitUses; ++ImplicitUses) - MarkPhysRegRecentlyUsed(*ImplicitUses); - } - XXX */ - SmallVector Kills; for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { MachineOperand& MO = MI->getOperand(i); - if (MO.isRegister() && MO.isKill()) { - if (!MO.isImplicit()) - Kills.push_back(MO.getReg()); - else if (!isReadModWriteImplicitKill(MI, MO.getReg())) - // These are extra physical register kills when a sub-register - // is defined (def of a sub-register is a read/mod/write of the - // larger registers). Ignore. - Kills.push_back(MO.getReg()); - } + if (MO.isRegister() && MO.isKill()) + Kills.push_back(MO.getReg()); } // Get the used operands into registers. This has the potential to spill @@ -688,16 +660,13 @@ void RABigBlock::AllocateBasicBlock(MachineBasicBlock &MBB) { } else if (PhysRegsUsed[PhysReg] == -2) { // Unallocatable register dead, ignore. continue; - } else { - assert(!PhysRegsUsed[PhysReg] || PhysRegsUsed[PhysReg] == -1 && - "Silently clearing a virtual register?"); } if (PhysReg) { DOUT << " Last use of " << RegInfo->getName(PhysReg) << "[%reg" << VirtReg <<"], removing it from live set\n"; removePhysReg(PhysReg); - for (const unsigned *AliasSet = RegInfo->getSubRegisters(PhysReg); + for (const unsigned *AliasSet = RegInfo->getAliasSet(PhysReg); *AliasSet; ++AliasSet) { if (PhysRegsUsed[*AliasSet] != -2) { DOUT << " Last use of " @@ -717,20 +686,15 @@ void RABigBlock::AllocateBasicBlock(MachineBasicBlock &MBB) { MRegisterInfo::isPhysicalRegister(MO.getReg())) { unsigned Reg = MO.getReg(); if (PhysRegsUsed[Reg] == -2) continue; // Something like ESP. - // These are extra physical register defs when a sub-register - // is defined (def of a sub-register is a read/mod/write of the - // larger registers). Ignore. - if (isReadModWriteImplicitDef(MI, MO.getReg())) continue; - + MF->setPhysRegUsed(Reg); spillPhysReg(MBB, MI, Reg, true); // Spill any existing value in reg PhysRegsUsed[Reg] = 0; // It is free and reserved now - - for (const unsigned *AliasSet = RegInfo->getSubRegisters(Reg); + for (const unsigned *AliasSet = RegInfo->getAliasSet(Reg); *AliasSet; ++AliasSet) { if (PhysRegsUsed[*AliasSet] != -2) { - MF->setPhysRegUsed(*AliasSet); PhysRegsUsed[*AliasSet] = 0; // It is free and reserved now + MF->setPhysRegUsed(*AliasSet); } } } @@ -741,15 +705,19 @@ void RABigBlock::AllocateBasicBlock(MachineBasicBlock &MBB) { for (const unsigned *ImplicitDefs = TID.ImplicitDefs; *ImplicitDefs; ++ImplicitDefs) { unsigned Reg = *ImplicitDefs; - if (PhysRegsUsed[Reg] != -2) { + bool IsNonAllocatable = PhysRegsUsed[Reg] == -2; + if (!IsNonAllocatable) { spillPhysReg(MBB, MI, Reg, true); PhysRegsUsed[Reg] = 0; // It is free and reserved now } MF->setPhysRegUsed(Reg); - for (const unsigned *AliasSet = RegInfo->getSubRegisters(Reg); + + for (const unsigned *AliasSet = RegInfo->getAliasSet(Reg); *AliasSet; ++AliasSet) { if (PhysRegsUsed[*AliasSet] != -2) { - PhysRegsUsed[*AliasSet] = 0; // It is free and reserved now + if (!IsNonAllocatable) { + PhysRegsUsed[*AliasSet] = 0; // It is free and reserved now + } MF->setPhysRegUsed(*AliasSet); } } -- 2.34.1