From 4e8f68f24593b70164f09fec837f4bca3fd8951d Mon Sep 17 00:00:00 2001 From: Colin LeMahieu Date: Thu, 4 Jun 2015 21:32:42 +0000 Subject: [PATCH] Revert r239095 incorrect test tree. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239102 91177308-0d34-0410-b5e6-96231b3b80d8 --- .../Disassembler/HexagonDisassembler.cpp | 742 +---------- lib/Target/Hexagon/HexagonAsmPrinter.cpp | 8 +- lib/Target/Hexagon/HexagonInstrFormatsV4.td | 5 - lib/Target/Hexagon/HexagonInstrInfoV4.td | 4 - lib/Target/Hexagon/HexagonIsetDx.td | 728 ----------- lib/Target/Hexagon/HexagonOperands.td | 8 - .../Hexagon/MCTargetDesc/CMakeLists.txt | 1 - .../MCTargetDesc/HexagonAsmBackend.cpp | 1 - .../Hexagon/MCTargetDesc/HexagonBaseInfo.h | 12 - .../MCTargetDesc/HexagonInstPrinter.cpp | 8 +- .../MCTargetDesc/HexagonMCCodeEmitter.cpp | 82 -- .../MCTargetDesc/HexagonMCDuplexInfo.cpp | 1100 ----------------- .../MCTargetDesc/HexagonMCInstrInfo.cpp | 68 - .../Hexagon/MCTargetDesc/HexagonMCInstrInfo.h | 60 +- .../MCTargetDesc/HexagonMCShuffler.cpp | 55 - test/CodeGen/Hexagon/args.ll | 1 + test/CodeGen/Hexagon/duplex.ll | 7 - 17 files changed, 59 insertions(+), 2831 deletions(-) delete mode 100644 lib/Target/Hexagon/HexagonIsetDx.td delete mode 100644 lib/Target/Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp delete mode 100644 test/CodeGen/Hexagon/duplex.ll diff --git a/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp b/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp index 14f9d777580..81f26321b99 100644 --- a/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp +++ b/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp @@ -56,43 +56,37 @@ public: } static DecodeStatus DecodeModRegsRegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t Address, - const void *Decoder); + uint64_t Address, const void *Decoder); static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t Address, - const void *Decoder); + uint64_t Address, const void *Decoder); static DecodeStatus DecodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t Address, - void const *Decoder); - -static unsigned GetSubinstOpcode(unsigned IClass, unsigned inst, unsigned &op, - raw_ostream &os); -static void AddSubinstOperands(MCInst *MI, unsigned opcode, unsigned inst); + uint64_t Address, void const *Decoder); static const uint16_t IntRegDecoderTable[] = { - Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, Hexagon::R4, - Hexagon::R5, Hexagon::R6, Hexagon::R7, Hexagon::R8, Hexagon::R9, - Hexagon::R10, Hexagon::R11, Hexagon::R12, Hexagon::R13, Hexagon::R14, - Hexagon::R15, Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19, - Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, Hexagon::R24, - Hexagon::R25, Hexagon::R26, Hexagon::R27, Hexagon::R28, Hexagon::R29, - Hexagon::R30, Hexagon::R31}; + Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, Hexagon::R4, + Hexagon::R5, Hexagon::R6, Hexagon::R7, Hexagon::R8, Hexagon::R9, + Hexagon::R10, Hexagon::R11, Hexagon::R12, Hexagon::R13, Hexagon::R14, + Hexagon::R15, Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19, + Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, Hexagon::R24, + Hexagon::R25, Hexagon::R26, Hexagon::R27, Hexagon::R28, Hexagon::R29, + Hexagon::R30, Hexagon::R31 }; -static const uint16_t PredRegDecoderTable[] = {Hexagon::P0, Hexagon::P1, - Hexagon::P2, Hexagon::P3}; +static const uint16_t PredRegDecoderTable[] = { Hexagon::P0, Hexagon::P1, +Hexagon::P2, Hexagon::P3 }; static DecodeStatus DecodeRegisterClass(MCInst &Inst, unsigned RegNo, - const uint16_t Table[], size_t Size) { + const uint16_t Table[], size_t Size) { if (RegNo < Size) { Inst.addOperand(MCOperand::createReg(Table[RegNo])); return MCDisassembler::Success; - } else + } + else return MCDisassembler::Fail; } static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t /*Address*/, - void const *Decoder) { + uint64_t /*Address*/, + void const *Decoder) { if (RegNo > 31) return MCDisassembler::Fail; @@ -102,13 +96,13 @@ static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo, } static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t /*Address*/, - const void *Decoder) { + uint64_t /*Address*/, const void *Decoder) { static const uint16_t CtrlRegDecoderTable[] = { - Hexagon::SA0, Hexagon::LC0, Hexagon::SA1, Hexagon::LC1, - Hexagon::P3_0, Hexagon::NoRegister, Hexagon::C6, Hexagon::C7, - Hexagon::USR, Hexagon::PC, Hexagon::UGP, Hexagon::GP, - Hexagon::CS0, Hexagon::CS1, Hexagon::UPCL, Hexagon::UPCH}; + Hexagon::SA0, Hexagon::LC0, Hexagon::SA1, Hexagon::LC1, + Hexagon::P3_0, Hexagon::NoRegister, Hexagon::C6, Hexagon::C7, + Hexagon::USR, Hexagon::PC, Hexagon::UGP, Hexagon::GP, + Hexagon::CS0, Hexagon::CS1, Hexagon::UPCL, Hexagon::UPCH + }; if (RegNo >= sizeof(CtrlRegDecoderTable) / sizeof(CtrlRegDecoderTable[0])) return MCDisassembler::Fail; @@ -122,15 +116,17 @@ static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo, } static DecodeStatus DecodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t /*Address*/, - void const *Decoder) { + uint64_t /*Address*/, void const *Decoder) { static const uint16_t CtrlReg64DecoderTable[] = { - Hexagon::C1_0, Hexagon::NoRegister, Hexagon::C3_2, - Hexagon::NoRegister, Hexagon::NoRegister, Hexagon::NoRegister, - Hexagon::C7_6, Hexagon::NoRegister, Hexagon::C9_8, - Hexagon::NoRegister, Hexagon::C11_10, Hexagon::NoRegister, - Hexagon::CS, Hexagon::NoRegister, Hexagon::UPC, - Hexagon::NoRegister}; + Hexagon::C1_0, Hexagon::NoRegister, + Hexagon::C3_2, Hexagon::NoRegister, + Hexagon::NoRegister, Hexagon::NoRegister, + Hexagon::C7_6, Hexagon::NoRegister, + Hexagon::C9_8, Hexagon::NoRegister, + Hexagon::C11_10, Hexagon::NoRegister, + Hexagon::CS, Hexagon::NoRegister, + Hexagon::UPC, Hexagon::NoRegister + }; if (RegNo >= sizeof(CtrlReg64DecoderTable) / sizeof(CtrlReg64DecoderTable[0])) return MCDisassembler::Fail; @@ -144,8 +140,7 @@ static DecodeStatus DecodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo, } static DecodeStatus DecodeModRegsRegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t /*Address*/, - const void *Decoder) { + uint64_t /*Address*/, const void *Decoder) { unsigned Register = 0; switch (RegNo) { case 0: @@ -162,21 +157,22 @@ static DecodeStatus DecodeModRegsRegisterClass(MCInst &Inst, unsigned RegNo, } static DecodeStatus DecodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t /*Address*/, - const void *Decoder) { + uint64_t /*Address*/, const void *Decoder) { static const uint16_t DoubleRegDecoderTable[] = { - Hexagon::D0, Hexagon::D1, Hexagon::D2, Hexagon::D3, - Hexagon::D4, Hexagon::D5, Hexagon::D6, Hexagon::D7, - Hexagon::D8, Hexagon::D9, Hexagon::D10, Hexagon::D11, - Hexagon::D12, Hexagon::D13, Hexagon::D14, Hexagon::D15}; + Hexagon::D0, Hexagon::D1, Hexagon::D2, Hexagon::D3, + Hexagon::D4, Hexagon::D5, Hexagon::D6, Hexagon::D7, + Hexagon::D8, Hexagon::D9, Hexagon::D10, Hexagon::D11, + Hexagon::D12, Hexagon::D13, Hexagon::D14, Hexagon::D15 + }; - return (DecodeRegisterClass(Inst, RegNo >> 1, DoubleRegDecoderTable, - sizeof(DoubleRegDecoderTable))); + return (DecodeRegisterClass(Inst, RegNo >> 1, + DoubleRegDecoderTable, + sizeof (DoubleRegDecoderTable))); } static DecodeStatus DecodePredRegsRegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t /*Address*/, - void const *Decoder) { + uint64_t /*Address*/, + void const *Decoder) { if (RegNo > 3) return MCDisassembler::Fail; @@ -210,10 +206,11 @@ DecodeStatus HexagonDisassembler::getInstruction(MCInst &MI, uint64_t &Size, *CurrentBundle = &MI; MI.setOpcode(Hexagon::BUNDLE); MI.addOperand(MCOperand::createImm(0)); - while (Result == Success && Complete == false) { + while (Result == Success && Complete == false) + { if (Bytes.size() < HEXAGON_INSTR_SIZE) return MCDisassembler::Fail; - MCInst *Inst = new (getContext()) MCInst; + MCInst * Inst = new (getContext()) MCInst; Result = getSingleInstruction(*Inst, MI, Bytes, Address, os, cs, Complete); MI.addOperand(MCOperand::createInst(Inst)); Size += HEXAGON_INSTR_SIZE; @@ -244,646 +241,11 @@ DecodeStatus HexagonDisassembler::getSingleInstruction( DecodeStatus Result = DecodeStatus::Success; if ((Instruction & HexagonII::INST_PARSE_MASK) == - HexagonII::INST_PARSE_DUPLEX) { - // Determine the instruction class of each instruction in the duplex. - unsigned duplexIClass, IClassLow, IClassHigh; - - duplexIClass = ((Instruction >> 28) & 0xe) | ((Instruction >> 13) & 0x1); - switch (duplexIClass) { - default: - return MCDisassembler::Fail; - case 0: - IClassLow = HexagonII::HSIG_L1; - IClassHigh = HexagonII::HSIG_L1; - break; - case 1: - IClassLow = HexagonII::HSIG_L2; - IClassHigh = HexagonII::HSIG_L1; - break; - case 2: - IClassLow = HexagonII::HSIG_L2; - IClassHigh = HexagonII::HSIG_L2; - break; - case 3: - IClassLow = HexagonII::HSIG_A; - IClassHigh = HexagonII::HSIG_A; - break; - case 4: - IClassLow = HexagonII::HSIG_L1; - IClassHigh = HexagonII::HSIG_A; - break; - case 5: - IClassLow = HexagonII::HSIG_L2; - IClassHigh = HexagonII::HSIG_A; - break; - case 6: - IClassLow = HexagonII::HSIG_S1; - IClassHigh = HexagonII::HSIG_A; - break; - case 7: - IClassLow = HexagonII::HSIG_S2; - IClassHigh = HexagonII::HSIG_A; - break; - case 8: - IClassLow = HexagonII::HSIG_S1; - IClassHigh = HexagonII::HSIG_L1; - break; - case 9: - IClassLow = HexagonII::HSIG_S1; - IClassHigh = HexagonII::HSIG_L2; - break; - case 10: - IClassLow = HexagonII::HSIG_S1; - IClassHigh = HexagonII::HSIG_S1; - break; - case 11: - IClassLow = HexagonII::HSIG_S2; - IClassHigh = HexagonII::HSIG_S1; - break; - case 12: - IClassLow = HexagonII::HSIG_S2; - IClassHigh = HexagonII::HSIG_L1; - break; - case 13: - IClassLow = HexagonII::HSIG_S2; - IClassHigh = HexagonII::HSIG_L2; - break; - case 14: - IClassLow = HexagonII::HSIG_S2; - IClassHigh = HexagonII::HSIG_S2; - break; - } - - // Set the MCInst to be a duplex instruction. Which one doesn't matter. - MI.setOpcode(Hexagon::DuplexIClass0); - - // Decode each instruction in the duplex. - // Create an MCInst for each instruction. - unsigned instLow = Instruction & 0x1fff; - unsigned instHigh = (Instruction >> 16) & 0x1fff; - unsigned opLow; - if (GetSubinstOpcode(IClassLow, instLow, opLow, os) != - MCDisassembler::Success) - return MCDisassembler::Fail; - unsigned opHigh; - if (GetSubinstOpcode(IClassHigh, instHigh, opHigh, os) != - MCDisassembler::Success) - return MCDisassembler::Fail; - MCInst *MILow = new (getContext()) MCInst; - MILow->setOpcode(opLow); - MCInst *MIHigh = new (getContext()) MCInst; - MIHigh->setOpcode(opHigh); - AddSubinstOperands(MILow, opLow, instLow); - AddSubinstOperands(MIHigh, opHigh, instHigh); - // see ConvertToSubInst() in - // lib/Target/Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp - - // Add the duplex instruction MCInsts as operands to the passed in MCInst. - MCOperand OPLow = MCOperand::createInst(MILow); - MCOperand OPHigh = MCOperand::createInst(MIHigh); - MI.addOperand(OPLow); - MI.addOperand(OPHigh); + HexagonII::INST_PARSE_PACKET_END) Complete = true; - } else { - if ((Instruction & HexagonII::INST_PARSE_MASK) == - HexagonII::INST_PARSE_PACKET_END) - Complete = true; - // Calling the auto-generated decoder function. - Result = - decodeInstruction(DecoderTable32, MI, Instruction, Address, this, STI); - } + // Calling the auto-generated decoder function. + Result = + decodeInstruction(DecoderTable32, MI, Instruction, Address, this, STI); return Result; } - -// These values are from HexagonGenMCCodeEmitter.inc and HexagonIsetDx.td -enum subInstBinaryValues { - V4_SA1_addi_BITS = 0x0000, - V4_SA1_addi_MASK = 0x1800, - V4_SA1_addrx_BITS = 0x1800, - V4_SA1_addrx_MASK = 0x1f00, - V4_SA1_addsp_BITS = 0x0c00, - V4_SA1_addsp_MASK = 0x1c00, - V4_SA1_and1_BITS = 0x1200, - V4_SA1_and1_MASK = 0x1f00, - V4_SA1_clrf_BITS = 0x1a70, - V4_SA1_clrf_MASK = 0x1e70, - V4_SA1_clrfnew_BITS = 0x1a50, - V4_SA1_clrfnew_MASK = 0x1e70, - V4_SA1_clrt_BITS = 0x1a60, - V4_SA1_clrt_MASK = 0x1e70, - V4_SA1_clrtnew_BITS = 0x1a40, - V4_SA1_clrtnew_MASK = 0x1e70, - V4_SA1_cmpeqi_BITS = 0x1900, - V4_SA1_cmpeqi_MASK = 0x1f00, - V4_SA1_combine0i_BITS = 0x1c00, - V4_SA1_combine0i_MASK = 0x1d18, - V4_SA1_combine1i_BITS = 0x1c08, - V4_SA1_combine1i_MASK = 0x1d18, - V4_SA1_combine2i_BITS = 0x1c10, - V4_SA1_combine2i_MASK = 0x1d18, - V4_SA1_combine3i_BITS = 0x1c18, - V4_SA1_combine3i_MASK = 0x1d18, - V4_SA1_combinerz_BITS = 0x1d08, - V4_SA1_combinerz_MASK = 0x1d08, - V4_SA1_combinezr_BITS = 0x1d00, - V4_SA1_combinezr_MASK = 0x1d08, - V4_SA1_dec_BITS = 0x1300, - V4_SA1_dec_MASK = 0x1f00, - V4_SA1_inc_BITS = 0x1100, - V4_SA1_inc_MASK = 0x1f00, - V4_SA1_seti_BITS = 0x0800, - V4_SA1_seti_MASK = 0x1c00, - V4_SA1_setin1_BITS = 0x1a00, - V4_SA1_setin1_MASK = 0x1e40, - V4_SA1_sxtb_BITS = 0x1500, - V4_SA1_sxtb_MASK = 0x1f00, - V4_SA1_sxth_BITS = 0x1400, - V4_SA1_sxth_MASK = 0x1f00, - V4_SA1_tfr_BITS = 0x1000, - V4_SA1_tfr_MASK = 0x1f00, - V4_SA1_zxtb_BITS = 0x1700, - V4_SA1_zxtb_MASK = 0x1f00, - V4_SA1_zxth_BITS = 0x1600, - V4_SA1_zxth_MASK = 0x1f00, - V4_SL1_loadri_io_BITS = 0x0000, - V4_SL1_loadri_io_MASK = 0x1000, - V4_SL1_loadrub_io_BITS = 0x1000, - V4_SL1_loadrub_io_MASK = 0x1000, - V4_SL2_deallocframe_BITS = 0x1f00, - V4_SL2_deallocframe_MASK = 0x1fc0, - V4_SL2_jumpr31_BITS = 0x1fc0, - V4_SL2_jumpr31_MASK = 0x1fc4, - V4_SL2_jumpr31_f_BITS = 0x1fc5, - V4_SL2_jumpr31_f_MASK = 0x1fc7, - V4_SL2_jumpr31_fnew_BITS = 0x1fc7, - V4_SL2_jumpr31_fnew_MASK = 0x1fc7, - V4_SL2_jumpr31_t_BITS = 0x1fc4, - V4_SL2_jumpr31_t_MASK = 0x1fc7, - V4_SL2_jumpr31_tnew_BITS = 0x1fc6, - V4_SL2_jumpr31_tnew_MASK = 0x1fc7, - V4_SL2_loadrb_io_BITS = 0x1000, - V4_SL2_loadrb_io_MASK = 0x1800, - V4_SL2_loadrd_sp_BITS = 0x1e00, - V4_SL2_loadrd_sp_MASK = 0x1f00, - V4_SL2_loadrh_io_BITS = 0x0000, - V4_SL2_loadrh_io_MASK = 0x1800, - V4_SL2_loadri_sp_BITS = 0x1c00, - V4_SL2_loadri_sp_MASK = 0x1e00, - V4_SL2_loadruh_io_BITS = 0x0800, - V4_SL2_loadruh_io_MASK = 0x1800, - V4_SL2_return_BITS = 0x1f40, - V4_SL2_return_MASK = 0x1fc4, - V4_SL2_return_f_BITS = 0x1f45, - V4_SL2_return_f_MASK = 0x1fc7, - V4_SL2_return_fnew_BITS = 0x1f47, - V4_SL2_return_fnew_MASK = 0x1fc7, - V4_SL2_return_t_BITS = 0x1f44, - V4_SL2_return_t_MASK = 0x1fc7, - V4_SL2_return_tnew_BITS = 0x1f46, - V4_SL2_return_tnew_MASK = 0x1fc7, - V4_SS1_storeb_io_BITS = 0x1000, - V4_SS1_storeb_io_MASK = 0x1000, - V4_SS1_storew_io_BITS = 0x0000, - V4_SS1_storew_io_MASK = 0x1000, - V4_SS2_allocframe_BITS = 0x1c00, - V4_SS2_allocframe_MASK = 0x1e00, - V4_SS2_storebi0_BITS = 0x1200, - V4_SS2_storebi0_MASK = 0x1f00, - V4_SS2_storebi1_BITS = 0x1300, - V4_SS2_storebi1_MASK = 0x1f00, - V4_SS2_stored_sp_BITS = 0x0a00, - V4_SS2_stored_sp_MASK = 0x1e00, - V4_SS2_storeh_io_BITS = 0x0000, - V4_SS2_storeh_io_MASK = 0x1800, - V4_SS2_storew_sp_BITS = 0x0800, - V4_SS2_storew_sp_MASK = 0x1e00, - V4_SS2_storewi0_BITS = 0x1000, - V4_SS2_storewi0_MASK = 0x1f00, - V4_SS2_storewi1_BITS = 0x1100, - V4_SS2_storewi1_MASK = 0x1f00 -}; - -static unsigned GetSubinstOpcode(unsigned IClass, unsigned inst, unsigned &op, - raw_ostream &os) { - switch (IClass) { - case HexagonII::HSIG_L1: - if ((inst & V4_SL1_loadri_io_MASK) == V4_SL1_loadri_io_BITS) - op = Hexagon::V4_SL1_loadri_io; - else if ((inst & V4_SL1_loadrub_io_MASK) == V4_SL1_loadrub_io_BITS) - op = Hexagon::V4_SL1_loadrub_io; - else { - os << ""; - return MCDisassembler::Fail; - } - break; - case HexagonII::HSIG_L2: - if ((inst & V4_SL2_deallocframe_MASK) == V4_SL2_deallocframe_BITS) - op = Hexagon::V4_SL2_deallocframe; - else if ((inst & V4_SL2_jumpr31_MASK) == V4_SL2_jumpr31_BITS) - op = Hexagon::V4_SL2_jumpr31; - else if ((inst & V4_SL2_jumpr31_f_MASK) == V4_SL2_jumpr31_f_BITS) - op = Hexagon::V4_SL2_jumpr31_f; - else if ((inst & V4_SL2_jumpr31_fnew_MASK) == V4_SL2_jumpr31_fnew_BITS) - op = Hexagon::V4_SL2_jumpr31_fnew; - else if ((inst & V4_SL2_jumpr31_t_MASK) == V4_SL2_jumpr31_t_BITS) - op = Hexagon::V4_SL2_jumpr31_t; - else if ((inst & V4_SL2_jumpr31_tnew_MASK) == V4_SL2_jumpr31_tnew_BITS) - op = Hexagon::V4_SL2_jumpr31_tnew; - else if ((inst & V4_SL2_loadrb_io_MASK) == V4_SL2_loadrb_io_BITS) - op = Hexagon::V4_SL2_loadrb_io; - else if ((inst & V4_SL2_loadrd_sp_MASK) == V4_SL2_loadrd_sp_BITS) - op = Hexagon::V4_SL2_loadrd_sp; - else if ((inst & V4_SL2_loadrh_io_MASK) == V4_SL2_loadrh_io_BITS) - op = Hexagon::V4_SL2_loadrh_io; - else if ((inst & V4_SL2_loadri_sp_MASK) == V4_SL2_loadri_sp_BITS) - op = Hexagon::V4_SL2_loadri_sp; - else if ((inst & V4_SL2_loadruh_io_MASK) == V4_SL2_loadruh_io_BITS) - op = Hexagon::V4_SL2_loadruh_io; - else if ((inst & V4_SL2_return_MASK) == V4_SL2_return_BITS) - op = Hexagon::V4_SL2_return; - else if ((inst & V4_SL2_return_f_MASK) == V4_SL2_return_f_BITS) - op = Hexagon::V4_SL2_return_f; - else if ((inst & V4_SL2_return_fnew_MASK) == V4_SL2_return_fnew_BITS) - op = Hexagon::V4_SL2_return_fnew; - else if ((inst & V4_SL2_return_t_MASK) == V4_SL2_return_t_BITS) - op = Hexagon::V4_SL2_return_t; - else if ((inst & V4_SL2_return_tnew_MASK) == V4_SL2_return_tnew_BITS) - op = Hexagon::V4_SL2_return_tnew; - else { - os << ""; - return MCDisassembler::Fail; - } - break; - case HexagonII::HSIG_A: - if ((inst & V4_SA1_addi_MASK) == V4_SA1_addi_BITS) - op = Hexagon::V4_SA1_addi; - else if ((inst & V4_SA1_addrx_MASK) == V4_SA1_addrx_BITS) - op = Hexagon::V4_SA1_addrx; - else if ((inst & V4_SA1_addsp_MASK) == V4_SA1_addsp_BITS) - op = Hexagon::V4_SA1_addsp; - else if ((inst & V4_SA1_and1_MASK) == V4_SA1_and1_BITS) - op = Hexagon::V4_SA1_and1; - else if ((inst & V4_SA1_clrf_MASK) == V4_SA1_clrf_BITS) - op = Hexagon::V4_SA1_clrf; - else if ((inst & V4_SA1_clrfnew_MASK) == V4_SA1_clrfnew_BITS) - op = Hexagon::V4_SA1_clrfnew; - else if ((inst & V4_SA1_clrt_MASK) == V4_SA1_clrt_BITS) - op = Hexagon::V4_SA1_clrt; - else if ((inst & V4_SA1_clrtnew_MASK) == V4_SA1_clrtnew_BITS) - op = Hexagon::V4_SA1_clrtnew; - else if ((inst & V4_SA1_cmpeqi_MASK) == V4_SA1_cmpeqi_BITS) - op = Hexagon::V4_SA1_cmpeqi; - else if ((inst & V4_SA1_combine0i_MASK) == V4_SA1_combine0i_BITS) - op = Hexagon::V4_SA1_combine0i; - else if ((inst & V4_SA1_combine1i_MASK) == V4_SA1_combine1i_BITS) - op = Hexagon::V4_SA1_combine1i; - else if ((inst & V4_SA1_combine2i_MASK) == V4_SA1_combine2i_BITS) - op = Hexagon::V4_SA1_combine2i; - else if ((inst & V4_SA1_combine3i_MASK) == V4_SA1_combine3i_BITS) - op = Hexagon::V4_SA1_combine3i; - else if ((inst & V4_SA1_combinerz_MASK) == V4_SA1_combinerz_BITS) - op = Hexagon::V4_SA1_combinerz; - else if ((inst & V4_SA1_combinezr_MASK) == V4_SA1_combinezr_BITS) - op = Hexagon::V4_SA1_combinezr; - else if ((inst & V4_SA1_dec_MASK) == V4_SA1_dec_BITS) - op = Hexagon::V4_SA1_dec; - else if ((inst & V4_SA1_inc_MASK) == V4_SA1_inc_BITS) - op = Hexagon::V4_SA1_inc; - else if ((inst & V4_SA1_seti_MASK) == V4_SA1_seti_BITS) - op = Hexagon::V4_SA1_seti; - else if ((inst & V4_SA1_setin1_MASK) == V4_SA1_setin1_BITS) - op = Hexagon::V4_SA1_setin1; - else if ((inst & V4_SA1_sxtb_MASK) == V4_SA1_sxtb_BITS) - op = Hexagon::V4_SA1_sxtb; - else if ((inst & V4_SA1_sxth_MASK) == V4_SA1_sxth_BITS) - op = Hexagon::V4_SA1_sxth; - else if ((inst & V4_SA1_tfr_MASK) == V4_SA1_tfr_BITS) - op = Hexagon::V4_SA1_tfr; - else if ((inst & V4_SA1_zxtb_MASK) == V4_SA1_zxtb_BITS) - op = Hexagon::V4_SA1_zxtb; - else if ((inst & V4_SA1_zxth_MASK) == V4_SA1_zxth_BITS) - op = Hexagon::V4_SA1_zxth; - else { - os << ""; - return MCDisassembler::Fail; - } - break; - case HexagonII::HSIG_S1: - if ((inst & V4_SS1_storeb_io_MASK) == V4_SS1_storeb_io_BITS) - op = Hexagon::V4_SS1_storeb_io; - else if ((inst & V4_SS1_storew_io_MASK) == V4_SS1_storew_io_BITS) - op = Hexagon::V4_SS1_storew_io; - else { - os << ""; - return MCDisassembler::Fail; - } - break; - case HexagonII::HSIG_S2: - if ((inst & V4_SS2_allocframe_MASK) == V4_SS2_allocframe_BITS) - op = Hexagon::V4_SS2_allocframe; - else if ((inst & V4_SS2_storebi0_MASK) == V4_SS2_storebi0_BITS) - op = Hexagon::V4_SS2_storebi0; - else if ((inst & V4_SS2_storebi1_MASK) == V4_SS2_storebi1_BITS) - op = Hexagon::V4_SS2_storebi1; - else if ((inst & V4_SS2_stored_sp_MASK) == V4_SS2_stored_sp_BITS) - op = Hexagon::V4_SS2_stored_sp; - else if ((inst & V4_SS2_storeh_io_MASK) == V4_SS2_storeh_io_BITS) - op = Hexagon::V4_SS2_storeh_io; - else if ((inst & V4_SS2_storew_sp_MASK) == V4_SS2_storew_sp_BITS) - op = Hexagon::V4_SS2_storew_sp; - else if ((inst & V4_SS2_storewi0_MASK) == V4_SS2_storewi0_BITS) - op = Hexagon::V4_SS2_storewi0; - else if ((inst & V4_SS2_storewi1_MASK) == V4_SS2_storewi1_BITS) - op = Hexagon::V4_SS2_storewi1; - else { - os << ""; - return MCDisassembler::Fail; - } - break; - default: - os << ""; - return MCDisassembler::Fail; - } - return MCDisassembler::Success; -} - -static unsigned getRegFromSubinstEncoding(unsigned encoded_reg) { - if (encoded_reg < 8) - return Hexagon::R0 + encoded_reg; - else if (encoded_reg < 16) - return Hexagon::R0 + encoded_reg + 8; - return Hexagon::NoRegister; -} - -static unsigned getDRegFromSubinstEncoding(unsigned encoded_dreg) { - if (encoded_dreg < 4) - return Hexagon::D0 + encoded_dreg; - else if (encoded_dreg < 8) - return Hexagon::D0 + encoded_dreg + 4; - return Hexagon::NoRegister; -} - -static void AddSubinstOperands(MCInst *MI, unsigned opcode, unsigned inst) { - int64_t operand; - MCOperand Op; - switch (opcode) { - case Hexagon::V4_SL2_deallocframe: - case Hexagon::V4_SL2_jumpr31: - case Hexagon::V4_SL2_jumpr31_f: - case Hexagon::V4_SL2_jumpr31_fnew: - case Hexagon::V4_SL2_jumpr31_t: - case Hexagon::V4_SL2_jumpr31_tnew: - case Hexagon::V4_SL2_return: - case Hexagon::V4_SL2_return_f: - case Hexagon::V4_SL2_return_fnew: - case Hexagon::V4_SL2_return_t: - case Hexagon::V4_SL2_return_tnew: - // no operands for these instructions - break; - case Hexagon::V4_SS2_allocframe: - // u 8-4{5_3} - operand = ((inst & 0x1f0) >> 4) << 3; - Op = MCOperand::createImm(operand); - MI->addOperand(Op); - break; - case Hexagon::V4_SL1_loadri_io: - // Rd 3-0, Rs 7-4, u 11-8{4_2} - operand = getRegFromSubinstEncoding(inst & 0xf); - Op = MCOperand::createReg(operand); - MI->addOperand(Op); - operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4); - Op = MCOperand::createReg(operand); - MI->addOperand(Op); - operand = (inst & 0xf00) >> 6; - Op = MCOperand::createImm(operand); - MI->addOperand(Op); - break; - case Hexagon::V4_SL1_loadrub_io: - // Rd 3-0, Rs 7-4, u 11-8 - operand = getRegFromSubinstEncoding(inst & 0xf); - Op = MCOperand::createReg(operand); - MI->addOperand(Op); - operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4); - Op = MCOperand::createReg(operand); - MI->addOperand(Op); - operand = (inst & 0xf00) >> 8; - Op = MCOperand::createImm(operand); - MI->addOperand(Op); - break; - case Hexagon::V4_SL2_loadrb_io: - // Rd 3-0, Rs 7-4, u 10-8 - operand = getRegFromSubinstEncoding(inst & 0xf); - Op = MCOperand::createReg(operand); - MI->addOperand(Op); - operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4); - Op = MCOperand::createReg(operand); - MI->addOperand(Op); - operand = (inst & 0x700) >> 8; - Op = MCOperand::createImm(operand); - MI->addOperand(Op); - break; - case Hexagon::V4_SL2_loadrh_io: - case Hexagon::V4_SL2_loadruh_io: - // Rd 3-0, Rs 7-4, u 10-8{3_1} - operand = getRegFromSubinstEncoding(inst & 0xf); - Op = MCOperand::createReg(operand); - MI->addOperand(Op); - operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4); - Op = MCOperand::createReg(operand); - MI->addOperand(Op); - operand = ((inst & 0x700) >> 8) << 1; - Op = MCOperand::createImm(operand); - MI->addOperand(Op); - break; - case Hexagon::V4_SL2_loadrd_sp: - // Rdd 2-0, u 7-3{5_3} - operand = getDRegFromSubinstEncoding(inst & 0x7); - Op = MCOperand::createReg(operand); - MI->addOperand(Op); - operand = ((inst & 0x0f8) >> 3) << 3; - Op = MCOperand::createImm(operand); - MI->addOperand(Op); - break; - case Hexagon::V4_SL2_loadri_sp: - // Rd 3-0, u 8-4{5_2} - operand = getRegFromSubinstEncoding(inst & 0xf); - Op = MCOperand::createReg(operand); - MI->addOperand(Op); - operand = ((inst & 0x1f0) >> 4) << 2; - Op = MCOperand::createImm(operand); - MI->addOperand(Op); - break; - case Hexagon::V4_SA1_addi: - // Rx 3-0 (x2), s7 10-4 - operand = getRegFromSubinstEncoding(inst & 0xf); - Op = MCOperand::createReg(operand); - MI->addOperand(Op); - MI->addOperand(Op); - operand = SignExtend64<7>((inst & 0x7f0) >> 4); - Op = MCOperand::createImm(operand); - MI->addOperand(Op); - break; - case Hexagon::V4_SA1_addrx: - // Rx 3-0 (x2), Rs 7-4 - operand = getRegFromSubinstEncoding(inst & 0xf); - Op = MCOperand::createReg(operand); - MI->addOperand(Op); - MI->addOperand(Op); - operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4); - Op = MCOperand::createReg(operand); - MI->addOperand(Op); - case Hexagon::V4_SA1_and1: - case Hexagon::V4_SA1_dec: - case Hexagon::V4_SA1_inc: - case Hexagon::V4_SA1_sxtb: - case Hexagon::V4_SA1_sxth: - case Hexagon::V4_SA1_tfr: - case Hexagon::V4_SA1_zxtb: - case Hexagon::V4_SA1_zxth: - // Rd 3-0, Rs 7-4 - operand = getRegFromSubinstEncoding(inst & 0xf); - Op = MCOperand::createReg(operand); - MI->addOperand(Op); - operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4); - Op = MCOperand::createReg(operand); - MI->addOperand(Op); - break; - case Hexagon::V4_SA1_addsp: - // Rd 3-0, u 9-4{6_2} - operand = getRegFromSubinstEncoding(inst & 0xf); - Op = MCOperand::createReg(operand); - MI->addOperand(Op); - operand = ((inst & 0x3f0) >> 4) << 2; - Op = MCOperand::createImm(operand); - MI->addOperand(Op); - break; - case Hexagon::V4_SA1_seti: - // Rd 3-0, u 9-4 - operand = getRegFromSubinstEncoding(inst & 0xf); - Op = MCOperand::createReg(operand); - MI->addOperand(Op); - operand = (inst & 0x3f0) >> 4; - Op = MCOperand::createImm(operand); - MI->addOperand(Op); - break; - case Hexagon::V4_SA1_clrf: - case Hexagon::V4_SA1_clrfnew: - case Hexagon::V4_SA1_clrt: - case Hexagon::V4_SA1_clrtnew: - case Hexagon::V4_SA1_setin1: - // Rd 3-0 - operand = getRegFromSubinstEncoding(inst & 0xf); - Op = MCOperand::createReg(operand); - MI->addOperand(Op); - break; - case Hexagon::V4_SA1_cmpeqi: - // Rs 7-4, u 1-0 - operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4); - Op = MCOperand::createReg(operand); - MI->addOperand(Op); - operand = inst & 0x3; - Op = MCOperand::createImm(operand); - MI->addOperand(Op); - break; - case Hexagon::V4_SA1_combine0i: - case Hexagon::V4_SA1_combine1i: - case Hexagon::V4_SA1_combine2i: - case Hexagon::V4_SA1_combine3i: - // Rdd 2-0, u 6-5 - operand = getDRegFromSubinstEncoding(inst & 0x7); - Op = MCOperand::createReg(operand); - MI->addOperand(Op); - operand = (inst & 0x060) >> 5; - Op = MCOperand::createImm(operand); - MI->addOperand(Op); - break; - case Hexagon::V4_SA1_combinerz: - case Hexagon::V4_SA1_combinezr: - // Rdd 2-0, Rs 7-4 - operand = getDRegFromSubinstEncoding(inst & 0x7); - Op = MCOperand::createReg(operand); - MI->addOperand(Op); - operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4); - Op = MCOperand::createReg(operand); - MI->addOperand(Op); - break; - case Hexagon::V4_SS1_storeb_io: - // Rs 7-4, u 11-8, Rt 3-0 - operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4); - Op = MCOperand::createReg(operand); - MI->addOperand(Op); - operand = (inst & 0xf00) >> 8; - Op = MCOperand::createImm(operand); - MI->addOperand(Op); - operand = getRegFromSubinstEncoding(inst & 0xf); - Op = MCOperand::createReg(operand); - MI->addOperand(Op); - break; - case Hexagon::V4_SS1_storew_io: - // Rs 7-4, u 11-8{4_2}, Rt 3-0 - operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4); - Op = MCOperand::createReg(operand); - MI->addOperand(Op); - operand = ((inst & 0xf00) >> 8) << 2; - Op = MCOperand::createImm(operand); - MI->addOperand(Op); - operand = getRegFromSubinstEncoding(inst & 0xf); - Op = MCOperand::createReg(operand); - MI->addOperand(Op); - break; - case Hexagon::V4_SS2_storebi0: - case Hexagon::V4_SS2_storebi1: - // Rs 7-4, u 3-0 - operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4); - Op = MCOperand::createReg(operand); - MI->addOperand(Op); - operand = inst & 0xf; - Op = MCOperand::createImm(operand); - MI->addOperand(Op); - break; - case Hexagon::V4_SS2_storewi0: - case Hexagon::V4_SS2_storewi1: - // Rs 7-4, u 3-0{4_2} - operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4); - Op = MCOperand::createReg(operand); - MI->addOperand(Op); - operand = (inst & 0xf) << 2; - Op = MCOperand::createImm(operand); - MI->addOperand(Op); - break; - case Hexagon::V4_SS2_stored_sp: - // s 8-3{6_3}, Rtt 2-0 - operand = SignExtend64<9>(((inst & 0x1f8) >> 3) << 3); - Op = MCOperand::createImm(operand); - MI->addOperand(Op); - operand = getDRegFromSubinstEncoding(inst & 0x7); - Op = MCOperand::createReg(operand); - MI->addOperand(Op); - case Hexagon::V4_SS2_storeh_io: - // Rs 7-4, u 10-8{3_1}, Rt 3-0 - operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4); - Op = MCOperand::createReg(operand); - MI->addOperand(Op); - operand = ((inst & 0x700) >> 8) << 1; - Op = MCOperand::createImm(operand); - MI->addOperand(Op); - operand = getRegFromSubinstEncoding(inst & 0xf); - Op = MCOperand::createReg(operand); - MI->addOperand(Op); - break; - case Hexagon::V4_SS2_storew_sp: - // u 8-4{5_2}, Rd 3-0 - operand = ((inst & 0x1f0) >> 4) << 2; - Op = MCOperand::createImm(operand); - MI->addOperand(Op); - operand = getRegFromSubinstEncoding(inst & 0xf); - Op = MCOperand::createReg(operand); - MI->addOperand(Op); - break; - default: - // don't crash with an invalid subinstruction - // llvm_unreachable("Invalid subinstruction in duplex instruction"); - break; - } -} diff --git a/lib/Target/Hexagon/HexagonAsmPrinter.cpp b/lib/Target/Hexagon/HexagonAsmPrinter.cpp index 45d953ff40a..48113610c80 100644 --- a/lib/Target/Hexagon/HexagonAsmPrinter.cpp +++ b/lib/Target/Hexagon/HexagonAsmPrinter.cpp @@ -20,7 +20,6 @@ #include "HexagonTargetMachine.h" #include "MCTargetDesc/HexagonInstPrinter.h" #include "MCTargetDesc/HexagonMCInstrInfo.h" -#include "MCTargetDesc/HexagonMCShuffler.h" #include "llvm/ADT/SmallString.h" #include "llvm/ADT/SmallVector.h" #include "llvm/ADT/StringExtras.h" @@ -200,12 +199,9 @@ void HexagonAsmPrinter::EmitInstruction(const MachineInstr *MI) { HexagonLowerToMC(MI, MCB, *this); HexagonMCInstrInfo::padEndloop(MCB); } - // Examine the packet and convert pairs of instructions to duplex - // instructions when possible. - SmallVector possibleDuplexes; - possibleDuplexes = HexagonMCInstrInfo::getDuplexPossibilties(*Subtarget->getInstrInfo(), MCB); - HexagonMCShuffle(*Subtarget->getInstrInfo(), *Subtarget, OutStreamer->getContext(), MCB, possibleDuplexes); EmitToStreamer(*OutStreamer, MCB); + + return; } extern "C" void LLVMInitializeHexagonAsmPrinter() { diff --git a/lib/Target/Hexagon/HexagonInstrFormatsV4.td b/lib/Target/Hexagon/HexagonInstrFormatsV4.td index db83ef6bc47..7f7b2c96dba 100644 --- a/lib/Target/Hexagon/HexagonInstrFormatsV4.td +++ b/lib/Target/Hexagon/HexagonInstrFormatsV4.td @@ -146,11 +146,6 @@ class EXTENDERInst pattern = []> : InstHexagon, OpcodeHexagon; -class SUBInst pattern = [], - string cstr = ""> - : InstHexagon, - OpcodeHexagon; - class CJInst pattern = [], string cstr = ""> : InstHexagon, diff --git a/lib/Target/Hexagon/HexagonInstrInfoV4.td b/lib/Target/Hexagon/HexagonInstrInfoV4.td index 65b0f497436..8b667c64515 100644 --- a/lib/Target/Hexagon/HexagonInstrInfoV4.td +++ b/lib/Target/Hexagon/HexagonInstrInfoV4.td @@ -4263,7 +4263,3 @@ def J4_jumpsetr: CJInst < let Inst{19-16} = Rs; let Inst{7-1} = r9_2{8-2}; } - -// Duplex instructions -//===----------------------------------------------------------------------===// -include "HexagonIsetDx.td" diff --git a/lib/Target/Hexagon/HexagonIsetDx.td b/lib/Target/Hexagon/HexagonIsetDx.td deleted file mode 100644 index 0ca95e99985..00000000000 --- a/lib/Target/Hexagon/HexagonIsetDx.td +++ /dev/null @@ -1,728 +0,0 @@ -//=- HexagonIsetDx.td - Target Desc. for Hexagon Target -*- tablegen -*-=// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// This file describes the Hexagon duplex instructions. -// -//===----------------------------------------------------------------------===// - -// SA1_combine1i: Combines. -let isCodeGenOnly = 1, hasSideEffects = 0 in -def V4_SA1_combine1i: SUBInst < - (outs DoubleRegs:$Rdd), - (ins u2Imm:$u2), - "$Rdd = combine(#1, #$u2)"> { - bits<3> Rdd; - bits<2> u2; - - let Inst{12-10} = 0b111; - let Inst{8} = 0b0; - let Inst{4-3} = 0b01; - let Inst{2-0} = Rdd; - let Inst{6-5} = u2; - } - -// SL2_jumpr31_f: Indirect conditional jump if false. -// SL2_jumpr31_f -> SL2_jumpr31_fnew -let Defs = [PC], Uses = [P0, R31], isCodeGenOnly = 1, isPredicated = 1, isPredicatedFalse = 1, isBranch = 1, isIndirectBranch = 1, hasSideEffects = 0 in -def V4_SL2_jumpr31_f: SUBInst < - (outs ), - (ins ), - "if (!p0) jumpr r31"> { - let Inst{12-6} = 0b1111111; - let Inst{2-0} = 0b101; - } - -// SL2_deallocframe: Deallocate stack frame. -let Defs = [R31, R29, R30], Uses = [R30], isCodeGenOnly = 1, mayLoad = 1, accessSize = DoubleWordAccess in -def V4_SL2_deallocframe: SUBInst < - (outs ), - (ins ), - "deallocframe"> { - let Inst{12-6} = 0b1111100; - let Inst{2} = 0b0; - } - -// SL2_return_f: Deallocate stack frame and return. -// SL2_return_f -> SL2_return_fnew -let Defs = [PC, R31, R29, R30], Uses = [R30, P0], isCodeGenOnly = 1, isPredicated = 1, isPredicatedFalse = 1, mayLoad = 1, accessSize = DoubleWordAccess, isBranch = 1, isIndirectBranch = 1 in -def V4_SL2_return_f: SUBInst < - (outs ), - (ins ), - "if (!p0) dealloc_return"> { - let Inst{12-6} = 0b1111101; - let Inst{2-0} = 0b101; - } - -// SA1_combine3i: Combines. -let isCodeGenOnly = 1, hasSideEffects = 0 in -def V4_SA1_combine3i: SUBInst < - (outs DoubleRegs:$Rdd), - (ins u2Imm:$u2), - "$Rdd = combine(#3, #$u2)"> { - bits<3> Rdd; - bits<2> u2; - - let Inst{12-10} = 0b111; - let Inst{8} = 0b0; - let Inst{4-3} = 0b11; - let Inst{2-0} = Rdd; - let Inst{6-5} = u2; - } - -// SS2_storebi0: Store byte. -let isCodeGenOnly = 1, mayStore = 1, accessSize = ByteAccess in -def V4_SS2_storebi0: SUBInst < - (outs ), - (ins IntRegs:$Rs, u4_0Imm:$u4_0), - "memb($Rs + #$u4_0)=#0"> { - bits<4> Rs; - bits<4> u4_0; - - let Inst{12-8} = 0b10010; - let Inst{7-4} = Rs; - let Inst{3-0} = u4_0; - } - -// SA1_clrtnew: Clear if true. -let Uses = [P0], isCodeGenOnly = 1, isPredicated = 1, isPredicatedNew = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in -def V4_SA1_clrtnew: SUBInst < - (outs IntRegs:$Rd), - (ins ), - "if (p0.new) $Rd = #0"> { - bits<4> Rd; - - let Inst{12-9} = 0b1101; - let Inst{6-4} = 0b100; - let Inst{3-0} = Rd; - } - -// SL2_loadruh_io: Load half. -let isCodeGenOnly = 1, mayLoad = 1, accessSize = HalfWordAccess, hasNewValue = 1, opNewValue = 0 in -def V4_SL2_loadruh_io: SUBInst < - (outs IntRegs:$Rd), - (ins IntRegs:$Rs, u3_1Imm:$u3_1), - "$Rd = memuh($Rs + #$u3_1)"> { - bits<4> Rd; - bits<4> Rs; - bits<4> u3_1; - - let Inst{12-11} = 0b01; - let Inst{3-0} = Rd; - let Inst{7-4} = Rs; - let Inst{10-8} = u3_1{3-1}; - } - -// SL2_jumpr31_tnew: Indirect conditional jump if true. -let Defs = [PC], Uses = [P0, R31], isCodeGenOnly = 1, isPredicated = 1, isPredicatedNew = 1, isBranch = 1, isIndirectBranch = 1, hasSideEffects = 0 in -def V4_SL2_jumpr31_tnew: SUBInst < - (outs ), - (ins ), - "if (p0.new) jumpr:nt r31"> { - let Inst{12-6} = 0b1111111; - let Inst{2-0} = 0b110; - } - -// SA1_addi: Add. -let isCodeGenOnly = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0, isExtendable = 1, isExtentSigned = 1, opExtentBits = 7, opExtendable = 2 in -def V4_SA1_addi: SUBInst < - (outs IntRegs:$Rx), - (ins IntRegs:$_src_, s7Ext:$s7), - "$Rx = add($_src_, #$s7)" , - [] , - "$_src_ = $Rx"> { - bits<4> Rx; - bits<7> s7; - - let Inst{12-11} = 0b00; - let Inst{3-0} = Rx; - let Inst{10-4} = s7; - } - -// SL1_loadrub_io: Load byte. -let isCodeGenOnly = 1, mayLoad = 1, accessSize = ByteAccess, hasNewValue = 1, opNewValue = 0 in -def V4_SL1_loadrub_io: SUBInst < - (outs IntRegs:$Rd), - (ins IntRegs:$Rs, u4_0Imm:$u4_0), - "$Rd = memub($Rs + #$u4_0)"> { - bits<4> Rd; - bits<4> Rs; - bits<4> u4_0; - - let Inst{12} = 0b1; - let Inst{3-0} = Rd; - let Inst{7-4} = Rs; - let Inst{11-8} = u4_0; - } - -// SL1_loadri_io: Load word. -let isCodeGenOnly = 1, mayLoad = 1, accessSize = WordAccess, hasNewValue = 1, opNewValue = 0 in -def V4_SL1_loadri_io: SUBInst < - (outs IntRegs:$Rd), - (ins IntRegs:$Rs, u4_2Imm:$u4_2), - "$Rd = memw($Rs + #$u4_2)"> { - bits<4> Rd; - bits<4> Rs; - bits<6> u4_2; - - let Inst{12} = 0b0; - let Inst{3-0} = Rd; - let Inst{7-4} = Rs; - let Inst{11-8} = u4_2{5-2}; - } - -// SA1_cmpeqi: Compareimmed. -let Defs = [P0], isCodeGenOnly = 1, hasSideEffects = 0 in -def V4_SA1_cmpeqi: SUBInst < - (outs ), - (ins IntRegs:$Rs, u2Imm:$u2), - "p0 = cmp.eq($Rs, #$u2)"> { - bits<4> Rs; - bits<2> u2; - - let Inst{12-8} = 0b11001; - let Inst{7-4} = Rs; - let Inst{1-0} = u2; - } - -// SA1_combinerz: Combines. -let isCodeGenOnly = 1, hasSideEffects = 0 in -def V4_SA1_combinerz: SUBInst < - (outs DoubleRegs:$Rdd), - (ins IntRegs:$Rs), - "$Rdd = combine($Rs, #0)"> { - bits<3> Rdd; - bits<4> Rs; - - let Inst{12-10} = 0b111; - let Inst{8} = 0b1; - let Inst{3} = 0b1; - let Inst{2-0} = Rdd; - let Inst{7-4} = Rs; - } - -// SL2_return_t: Deallocate stack frame and return. -// SL2_return_t -> SL2_return_tnew -let Defs = [PC, R31, R29, R30], Uses = [R30, P0], isCodeGenOnly = 1, isPredicated = 1, mayLoad = 1, accessSize = DoubleWordAccess, isBranch = 1, isIndirectBranch = 1 in -def V4_SL2_return_t: SUBInst < - (outs ), - (ins ), - "if (p0) dealloc_return"> { - let Inst{12-6} = 0b1111101; - let Inst{2-0} = 0b100; - } - -// SS2_allocframe: Allocate stack frame. -let Defs = [R29, R30], Uses = [R30, R31, R29], isCodeGenOnly = 1, mayStore = 1, accessSize = DoubleWordAccess in -def V4_SS2_allocframe: SUBInst < - (outs ), - (ins u5_3Imm:$u5_3), - "allocframe(#$u5_3)"> { - bits<8> u5_3; - - let Inst{12-9} = 0b1110; - let Inst{8-4} = u5_3{7-3}; - } - -// SS2_storeh_io: Store half. -let isCodeGenOnly = 1, mayStore = 1, accessSize = HalfWordAccess in -def V4_SS2_storeh_io: SUBInst < - (outs ), - (ins IntRegs:$Rs, u3_1Imm:$u3_1, IntRegs:$Rt), - "memh($Rs + #$u3_1) = $Rt"> { - bits<4> Rs; - bits<4> u3_1; - bits<4> Rt; - - let Inst{12-11} = 0b00; - let Inst{7-4} = Rs; - let Inst{10-8} = u3_1{3-1}; - let Inst{3-0} = Rt; - } - -// SS2_storewi0: Store word. -let isCodeGenOnly = 1, mayStore = 1, accessSize = WordAccess in -def V4_SS2_storewi0: SUBInst < - (outs ), - (ins IntRegs:$Rs, u4_2Imm:$u4_2), - "memw($Rs + #$u4_2)=#0"> { - bits<4> Rs; - bits<6> u4_2; - - let Inst{12-8} = 0b10000; - let Inst{7-4} = Rs; - let Inst{3-0} = u4_2{5-2}; - } - -// SS2_storewi1: Store word. -let isCodeGenOnly = 1, mayStore = 1, accessSize = WordAccess in -def V4_SS2_storewi1: SUBInst < - (outs ), - (ins IntRegs:$Rs, u4_2Imm:$u4_2), - "memw($Rs + #$u4_2)=#1"> { - bits<4> Rs; - bits<6> u4_2; - - let Inst{12-8} = 0b10001; - let Inst{7-4} = Rs; - let Inst{3-0} = u4_2{5-2}; - } - -// SL2_jumpr31: Indirect conditional jump if true. -let Defs = [PC], Uses = [R31], isCodeGenOnly = 1, isBranch = 1, isIndirectBranch = 1, hasSideEffects = 0 in -def V4_SL2_jumpr31: SUBInst < - (outs ), - (ins ), - "jumpr r31"> { - let Inst{12-6} = 0b1111111; - let Inst{2} = 0b0; - } - -// SA1_combinezr: Combines. -let isCodeGenOnly = 1, hasSideEffects = 0 in -def V4_SA1_combinezr: SUBInst < - (outs DoubleRegs:$Rdd), - (ins IntRegs:$Rs), - "$Rdd = combine(#0, $Rs)"> { - bits<3> Rdd; - bits<4> Rs; - - let Inst{12-10} = 0b111; - let Inst{8} = 0b1; - let Inst{3} = 0b0; - let Inst{2-0} = Rdd; - let Inst{7-4} = Rs; - } - -// SL2_loadrh_io: Load half. -let isCodeGenOnly = 1, mayLoad = 1, accessSize = HalfWordAccess, hasNewValue = 1, opNewValue = 0 in -def V4_SL2_loadrh_io: SUBInst < - (outs IntRegs:$Rd), - (ins IntRegs:$Rs, u3_1Imm:$u3_1), - "$Rd = memh($Rs + #$u3_1)"> { - bits<4> Rd; - bits<4> Rs; - bits<4> u3_1; - - let Inst{12-11} = 0b00; - let Inst{3-0} = Rd; - let Inst{7-4} = Rs; - let Inst{10-8} = u3_1{3-1}; - } - -// SA1_addrx: Add. -let isCodeGenOnly = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in -def V4_SA1_addrx: SUBInst < - (outs IntRegs:$Rx), - (ins IntRegs:$_src_, IntRegs:$Rs), - "$Rx = add($_src_, $Rs)" , - [] , - "$_src_ = $Rx"> { - bits<4> Rx; - bits<4> Rs; - - let Inst{12-8} = 0b11000; - let Inst{3-0} = Rx; - let Inst{7-4} = Rs; - } - -// SA1_setin1: Set to -1. -let isCodeGenOnly = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in -def V4_SA1_setin1: SUBInst < - (outs IntRegs:$Rd), - (ins ), - "$Rd = #-1"> { - bits<4> Rd; - - let Inst{12-9} = 0b1101; - let Inst{6} = 0b0; - let Inst{3-0} = Rd; - } - -// SA1_sxth: Sxth. -let isCodeGenOnly = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in -def V4_SA1_sxth: SUBInst < - (outs IntRegs:$Rd), - (ins IntRegs:$Rs), - "$Rd = sxth($Rs)"> { - bits<4> Rd; - bits<4> Rs; - - let Inst{12-8} = 0b10100; - let Inst{3-0} = Rd; - let Inst{7-4} = Rs; - } - -// SA1_combine0i: Combines. -let isCodeGenOnly = 1, hasSideEffects = 0 in -def V4_SA1_combine0i: SUBInst < - (outs DoubleRegs:$Rdd), - (ins u2Imm:$u2), - "$Rdd = combine(#0, #$u2)"> { - bits<3> Rdd; - bits<2> u2; - - let Inst{12-10} = 0b111; - let Inst{8} = 0b0; - let Inst{4-3} = 0b00; - let Inst{2-0} = Rdd; - let Inst{6-5} = u2; - } - -// SA1_combine2i: Combines. -let isCodeGenOnly = 1, hasSideEffects = 0 in -def V4_SA1_combine2i: SUBInst < - (outs DoubleRegs:$Rdd), - (ins u2Imm:$u2), - "$Rdd = combine(#2, #$u2)"> { - bits<3> Rdd; - bits<2> u2; - - let Inst{12-10} = 0b111; - let Inst{8} = 0b0; - let Inst{4-3} = 0b10; - let Inst{2-0} = Rdd; - let Inst{6-5} = u2; - } - -// SA1_sxtb: Sxtb. -let isCodeGenOnly = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in -def V4_SA1_sxtb: SUBInst < - (outs IntRegs:$Rd), - (ins IntRegs:$Rs), - "$Rd = sxtb($Rs)"> { - bits<4> Rd; - bits<4> Rs; - - let Inst{12-8} = 0b10101; - let Inst{3-0} = Rd; - let Inst{7-4} = Rs; - } - -// SA1_clrf: Clear if false. -// SA1_clrf -> SA1_clrfnew -let Uses = [P0], isCodeGenOnly = 1, isPredicated = 1, isPredicatedFalse = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in -def V4_SA1_clrf: SUBInst < - (outs IntRegs:$Rd), - (ins ), - "if (!p0) $Rd = #0"> { - bits<4> Rd; - - let Inst{12-9} = 0b1101; - let Inst{6-4} = 0b111; - let Inst{3-0} = Rd; - } - -// SL2_loadrb_io: Load byte. -let isCodeGenOnly = 1, mayLoad = 1, accessSize = ByteAccess, hasNewValue = 1, opNewValue = 0 in -def V4_SL2_loadrb_io: SUBInst < - (outs IntRegs:$Rd), - (ins IntRegs:$Rs, u3_0Imm:$u3_0), - "$Rd = memb($Rs + #$u3_0)"> { - bits<4> Rd; - bits<4> Rs; - bits<3> u3_0; - - let Inst{12-11} = 0b10; - let Inst{3-0} = Rd; - let Inst{7-4} = Rs; - let Inst{10-8} = u3_0; - } - -// SA1_tfr: Tfr. -let isCodeGenOnly = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in -def V4_SA1_tfr: SUBInst < - (outs IntRegs:$Rd), - (ins IntRegs:$Rs), - "$Rd = $Rs"> { - bits<4> Rd; - bits<4> Rs; - - let Inst{12-8} = 0b10000; - let Inst{3-0} = Rd; - let Inst{7-4} = Rs; - } - -// SL2_loadrd_sp: Load dword. -let Uses = [R29], isCodeGenOnly = 1, mayLoad = 1, accessSize = DoubleWordAccess in -def V4_SL2_loadrd_sp: SUBInst < - (outs DoubleRegs:$Rdd), - (ins u5_3Imm:$u5_3), - "$Rdd = memd(r29 + #$u5_3)"> { - bits<3> Rdd; - bits<8> u5_3; - - let Inst{12-8} = 0b11110; - let Inst{2-0} = Rdd; - let Inst{7-3} = u5_3{7-3}; - } - -// SA1_and1: And #1. -let isCodeGenOnly = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in -def V4_SA1_and1: SUBInst < - (outs IntRegs:$Rd), - (ins IntRegs:$Rs), - "$Rd = and($Rs, #1)"> { - bits<4> Rd; - bits<4> Rs; - - let Inst{12-8} = 0b10010; - let Inst{3-0} = Rd; - let Inst{7-4} = Rs; - } - -// SS2_storebi1: Store byte. -let isCodeGenOnly = 1, mayStore = 1, accessSize = ByteAccess in -def V4_SS2_storebi1: SUBInst < - (outs ), - (ins IntRegs:$Rs, u4_0Imm:$u4_0), - "memb($Rs + #$u4_0)=#1"> { - bits<4> Rs; - bits<4> u4_0; - - let Inst{12-8} = 0b10011; - let Inst{7-4} = Rs; - let Inst{3-0} = u4_0; - } - -// SA1_inc: Inc. -let isCodeGenOnly = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in -def V4_SA1_inc: SUBInst < - (outs IntRegs:$Rd), - (ins IntRegs:$Rs), - "$Rd = add($Rs, #1)"> { - bits<4> Rd; - bits<4> Rs; - - let Inst{12-8} = 0b10001; - let Inst{3-0} = Rd; - let Inst{7-4} = Rs; - } - -// SS2_stored_sp: Store dword. -let Uses = [R29], isCodeGenOnly = 1, mayStore = 1, accessSize = DoubleWordAccess in -def V4_SS2_stored_sp: SUBInst < - (outs ), - (ins s6_3Imm:$s6_3, DoubleRegs:$Rtt), - "memd(r29 + #$s6_3) = $Rtt"> { - bits<9> s6_3; - bits<3> Rtt; - - let Inst{12-9} = 0b0101; - let Inst{8-3} = s6_3{8-3}; - let Inst{2-0} = Rtt; - } - -// SS2_storew_sp: Store word. -let Uses = [R29], isCodeGenOnly = 1, mayStore = 1, accessSize = WordAccess in -def V4_SS2_storew_sp: SUBInst < - (outs ), - (ins u5_2Imm:$u5_2, IntRegs:$Rt), - "memw(r29 + #$u5_2) = $Rt"> { - bits<7> u5_2; - bits<4> Rt; - - let Inst{12-9} = 0b0100; - let Inst{8-4} = u5_2{6-2}; - let Inst{3-0} = Rt; - } - -// SL2_jumpr31_fnew: Indirect conditional jump if false. -let Defs = [PC], Uses = [P0, R31], isCodeGenOnly = 1, isPredicated = 1, isPredicatedFalse = 1, isPredicatedNew = 1, isBranch = 1, isIndirectBranch = 1, hasSideEffects = 0 in -def V4_SL2_jumpr31_fnew: SUBInst < - (outs ), - (ins ), - "if (!p0.new) jumpr:nt r31"> { - let Inst{12-6} = 0b1111111; - let Inst{2-0} = 0b111; - } - -// SA1_clrt: Clear if true. -// SA1_clrt -> SA1_clrtnew -let Uses = [P0], isCodeGenOnly = 1, isPredicated = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in -def V4_SA1_clrt: SUBInst < - (outs IntRegs:$Rd), - (ins ), - "if (p0) $Rd = #0"> { - bits<4> Rd; - - let Inst{12-9} = 0b1101; - let Inst{6-4} = 0b110; - let Inst{3-0} = Rd; - } - -// SL2_return: Deallocate stack frame and return. -let Defs = [PC, R31, R29, R30], Uses = [R30], isCodeGenOnly = 1, mayLoad = 1, accessSize = DoubleWordAccess, isBranch = 1, isIndirectBranch = 1 in -def V4_SL2_return: SUBInst < - (outs ), - (ins ), - "dealloc_return"> { - let Inst{12-6} = 0b1111101; - let Inst{2} = 0b0; - } - -// SA1_dec: Dec. -let isCodeGenOnly = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in -def V4_SA1_dec: SUBInst < - (outs IntRegs:$Rd), - (ins IntRegs:$Rs), - "$Rd = add($Rs,#-1)"> { - bits<4> Rd; - bits<4> Rs; - - let Inst{12-8} = 0b10011; - let Inst{3-0} = Rd; - let Inst{7-4} = Rs; - } - -// SA1_seti: Set immed. -let isCodeGenOnly = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0, isExtendable = 1, isExtentSigned = 0, opExtentBits = 6, opExtendable = 1 in -def V4_SA1_seti: SUBInst < - (outs IntRegs:$Rd), - (ins u6Ext:$u6), - "$Rd = #$u6"> { - bits<4> Rd; - bits<6> u6; - - let Inst{12-10} = 0b010; - let Inst{3-0} = Rd; - let Inst{9-4} = u6; - } - -// SL2_jumpr31_t: Indirect conditional jump if true. -// SL2_jumpr31_t -> SL2_jumpr31_tnew -let Defs = [PC], Uses = [P0, R31], isCodeGenOnly = 1, isPredicated = 1, isBranch = 1, isIndirectBranch = 1, hasSideEffects = 0 in -def V4_SL2_jumpr31_t: SUBInst < - (outs ), - (ins ), - "if (p0) jumpr r31"> { - let Inst{12-6} = 0b1111111; - let Inst{2-0} = 0b100; - } - -// SA1_clrfnew: Clear if false. -let Uses = [P0], isCodeGenOnly = 1, isPredicated = 1, isPredicatedFalse = 1, isPredicatedNew = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in -def V4_SA1_clrfnew: SUBInst < - (outs IntRegs:$Rd), - (ins ), - "if (!p0.new) $Rd = #0"> { - bits<4> Rd; - - let Inst{12-9} = 0b1101; - let Inst{6-4} = 0b101; - let Inst{3-0} = Rd; - } - -// SS1_storew_io: Store word. -let isCodeGenOnly = 1, mayStore = 1, accessSize = WordAccess in -def V4_SS1_storew_io: SUBInst < - (outs ), - (ins IntRegs:$Rs, u4_2Imm:$u4_2, IntRegs:$Rt), - "memw($Rs + #$u4_2) = $Rt"> { - bits<4> Rs; - bits<6> u4_2; - bits<4> Rt; - - let Inst{12} = 0b0; - let Inst{7-4} = Rs; - let Inst{11-8} = u4_2{5-2}; - let Inst{3-0} = Rt; - } - -// SA1_zxtb: Zxtb. -let isCodeGenOnly = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in -def V4_SA1_zxtb: SUBInst < - (outs IntRegs:$Rd), - (ins IntRegs:$Rs), - "$Rd = and($Rs, #255)"> { - bits<4> Rd; - bits<4> Rs; - - let Inst{12-8} = 0b10111; - let Inst{3-0} = Rd; - let Inst{7-4} = Rs; - } - -// SA1_addsp: Add. -let Uses = [R29], isCodeGenOnly = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in -def V4_SA1_addsp: SUBInst < - (outs IntRegs:$Rd), - (ins u6_2Imm:$u6_2), - "$Rd = add(r29, #$u6_2)"> { - bits<4> Rd; - bits<8> u6_2; - - let Inst{12-10} = 0b011; - let Inst{3-0} = Rd; - let Inst{9-4} = u6_2{7-2}; - } - -// SL2_loadri_sp: Load word. -let Uses = [R29], isCodeGenOnly = 1, mayLoad = 1, accessSize = WordAccess, hasNewValue = 1, opNewValue = 0 in -def V4_SL2_loadri_sp: SUBInst < - (outs IntRegs:$Rd), - (ins u5_2Imm:$u5_2), - "$Rd = memw(r29 + #$u5_2)"> { - bits<4> Rd; - bits<7> u5_2; - - let Inst{12-9} = 0b1110; - let Inst{3-0} = Rd; - let Inst{8-4} = u5_2{6-2}; - } - -// SS1_storeb_io: Store byte. -let isCodeGenOnly = 1, mayStore = 1, accessSize = ByteAccess in -def V4_SS1_storeb_io: SUBInst < - (outs ), - (ins IntRegs:$Rs, u4_0Imm:$u4_0, IntRegs:$Rt), - "memb($Rs + #$u4_0) = $Rt"> { - bits<4> Rs; - bits<4> u4_0; - bits<4> Rt; - - let Inst{12} = 0b1; - let Inst{7-4} = Rs; - let Inst{11-8} = u4_0; - let Inst{3-0} = Rt; - } - -// SL2_return_tnew: Deallocate stack frame and return. -let Defs = [PC, R31, R29, R30], Uses = [R30, P0], isCodeGenOnly = 1, isPredicated = 1, isPredicatedNew = 1, mayLoad = 1, accessSize = DoubleWordAccess, isBranch = 1, isIndirectBranch = 1 in -def V4_SL2_return_tnew: SUBInst < - (outs ), - (ins ), - "if (p0.new) dealloc_return:nt"> { - let Inst{12-6} = 0b1111101; - let Inst{2-0} = 0b110; - } - -// SL2_return_fnew: Deallocate stack frame and return. -let Defs = [PC, R31, R29, R30], Uses = [R30, P0], isCodeGenOnly = 1, isPredicated = 1, isPredicatedFalse = 1, isPredicatedNew = 1, mayLoad = 1, accessSize = DoubleWordAccess, isBranch = 1, isIndirectBranch = 1 in -def V4_SL2_return_fnew: SUBInst < - (outs ), - (ins ), - "if (!p0.new) dealloc_return:nt"> { - let Inst{12-6} = 0b1111101; - let Inst{2-0} = 0b111; - } - -// SA1_zxth: Zxth. -let isCodeGenOnly = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in -def V4_SA1_zxth: SUBInst < - (outs IntRegs:$Rd), - (ins IntRegs:$Rs), - "$Rd = zxth($Rs)"> { - bits<4> Rd; - bits<4> Rs; - - let Inst{12-8} = 0b10110; - let Inst{3-0} = Rd; - let Inst{7-4} = Rs; - } - diff --git a/lib/Target/Hexagon/HexagonOperands.td b/lib/Target/Hexagon/HexagonOperands.td index be8204b7de5..b7f364ef075 100644 --- a/lib/Target/Hexagon/HexagonOperands.td +++ b/lib/Target/Hexagon/HexagonOperands.td @@ -27,7 +27,6 @@ let PrintMethod = "printImmOperand" in { def s8Imm : Operand; def s8Imm64 : Operand; def s6Imm : Operand; - def s6_3Imm : Operand; def s4Imm : Operand; def s4_0Imm : Operand; def s4_1Imm : Operand; @@ -52,14 +51,8 @@ let PrintMethod = "printImmOperand" in { def u6_2Imm : Operand; def u6_3Imm : Operand; def u5Imm : Operand; - def u5_2Imm : Operand; - def u5_3Imm : Operand; def u4Imm : Operand; - def u4_0Imm : Operand; - def u4_2Imm : Operand; def u3Imm : Operand; - def u3_0Imm : Operand; - def u3_1Imm : Operand; def u2Imm : Operand; def u1Imm : Operand; def n8Imm : Operand; @@ -451,7 +444,6 @@ let PrintMethod = "printExtOperand" in { def s10Ext : Operand; def s9Ext : Operand; def s8Ext : Operand; - def s7Ext : Operand; def s6Ext : Operand; def s11_0Ext : Operand; def s11_1Ext : Operand; diff --git a/lib/Target/Hexagon/MCTargetDesc/CMakeLists.txt b/lib/Target/Hexagon/MCTargetDesc/CMakeLists.txt index d0fae8a5192..90b34d304b7 100644 --- a/lib/Target/Hexagon/MCTargetDesc/CMakeLists.txt +++ b/lib/Target/Hexagon/MCTargetDesc/CMakeLists.txt @@ -4,7 +4,6 @@ add_llvm_library(LLVMHexagonDesc HexagonInstPrinter.cpp HexagonMCAsmInfo.cpp HexagonMCCodeEmitter.cpp - HexagonMCDuplexInfo.cpp HexagonMCInstrInfo.cpp HexagonMCShuffler.cpp HexagonMCTargetDesc.cpp diff --git a/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp b/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp index 76894840153..b4db977e361 100644 --- a/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp +++ b/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp @@ -16,7 +16,6 @@ #include "llvm/MC/MCAssembler.h" #include "llvm/MC/MCELFObjectWriter.h" #include "llvm/MC/MCFixupKindInfo.h" -#include "llvm/MC/MCInstrInfo.h" #include "llvm/Support/TargetRegistry.h" using namespace llvm; diff --git a/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h b/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h index 4f84e0d79e6..342a61190e6 100644 --- a/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h +++ b/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h @@ -43,7 +43,6 @@ namespace HexagonII { TypeXTYPE = 8, TypeMEMOP = 9, TypeNV = 10, - TypeDUPLEX = 11, TypePREFIX = 30, // Such as extenders. TypeENDLOOP = 31 // Such as end of a HW loop. }; @@ -191,17 +190,6 @@ namespace HexagonII { MO_GPREL }; - // Hexagon Sub-instruction classes. - enum SubInstructionGroup { - HSIG_None = 0, - HSIG_L1, - HSIG_L2, - HSIG_S1, - HSIG_S2, - HSIG_A, - HSIG_Compound - }; - enum InstParseBits { INST_PARSE_MASK = 0x0000c000, INST_PARSE_PACKET_END = 0x0000c000, diff --git a/lib/Target/Hexagon/MCTargetDesc/HexagonInstPrinter.cpp b/lib/Target/Hexagon/MCTargetDesc/HexagonInstPrinter.cpp index 3fe20395c40..73f20f52439 100644 --- a/lib/Target/Hexagon/MCTargetDesc/HexagonInstPrinter.cpp +++ b/lib/Target/Hexagon/MCTargetDesc/HexagonInstPrinter.cpp @@ -129,13 +129,7 @@ void HexagonInstPrinter::printInst(MCInst const *MI, raw_ostream &OS, HasExtender = false; for (auto const &I : HexagonMCInstrInfo::bundleInstructions(*MI)) { MCInst const &MCI = *I.getInst(); - if (HexagonMCInstrInfo::isDuplex(MII, MCI)) { - printInstruction(MCI.getOperand(1).getInst(), OS); - OS << '\v'; - HasExtender = false; - printInstruction(MCI.getOperand(0).getInst(), OS); - } else - printInstruction(&MCI, OS); + printInstruction(&MCI, OS); setExtender(MCI); OS << "\n"; } diff --git a/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp b/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp index 1eee852996f..6796a22f725 100644 --- a/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp +++ b/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp @@ -40,25 +40,18 @@ HexagonMCCodeEmitter::HexagonMCCodeEmitter(MCInstrInfo const &aMII, uint32_t HexagonMCCodeEmitter::parseBits(size_t Instruction, size_t Last, MCInst const &MCB, MCInst const &MCI) const { - bool Duplex = HexagonMCInstrInfo::isDuplex(MCII, MCI); if (Instruction == 0) { if (HexagonMCInstrInfo::isInnerLoop(MCB)) { - assert(!Duplex); assert(Instruction != Last); return HexagonII::INST_PARSE_LOOP_END; } } if (Instruction == 1) { if (HexagonMCInstrInfo::isOuterLoop(MCB)) { - assert(!Duplex); assert(Instruction != Last); return HexagonII::INST_PARSE_LOOP_END; } } - if (Duplex) { - assert(Instruction == Last); - return HexagonII::INST_PARSE_DUPLEX; - } if(Instruction == Last) return HexagonII::INST_PARSE_PACKET_END; return HexagonII::INST_PARSE_NOT_END; @@ -156,81 +149,6 @@ void HexagonMCCodeEmitter::EncodeSingleInstruction( llvm_unreachable("Unimplemented Instruction"); } Binary |= Parse; - - // if we need to emit a duplexed instruction - if (HMB.getOpcode() >= Hexagon::DuplexIClass0 && - HMB.getOpcode() <= Hexagon::DuplexIClassF) { - assert(Parse == HexagonII::INST_PARSE_DUPLEX && - "Emitting duplex without duplex parse bits"); - unsigned dupIClass; - switch (HMB.getOpcode()) { - case Hexagon::DuplexIClass0: - dupIClass = 0; - break; - case Hexagon::DuplexIClass1: - dupIClass = 1; - break; - case Hexagon::DuplexIClass2: - dupIClass = 2; - break; - case Hexagon::DuplexIClass3: - dupIClass = 3; - break; - case Hexagon::DuplexIClass4: - dupIClass = 4; - break; - case Hexagon::DuplexIClass5: - dupIClass = 5; - break; - case Hexagon::DuplexIClass6: - dupIClass = 6; - break; - case Hexagon::DuplexIClass7: - dupIClass = 7; - break; - case Hexagon::DuplexIClass8: - dupIClass = 8; - break; - case Hexagon::DuplexIClass9: - dupIClass = 9; - break; - case Hexagon::DuplexIClassA: - dupIClass = 10; - break; - case Hexagon::DuplexIClassB: - dupIClass = 11; - break; - case Hexagon::DuplexIClassC: - dupIClass = 12; - break; - case Hexagon::DuplexIClassD: - dupIClass = 13; - break; - case Hexagon::DuplexIClassE: - dupIClass = 14; - break; - case Hexagon::DuplexIClassF: - dupIClass = 15; - break; - default: - llvm_unreachable("Unimplemented DuplexIClass"); - break; - } - // 29 is the bit position. - // 0b1110 =0xE bits are masked off and down shifted by 1 bit. - // Last bit is moved to bit position 13 - Binary = ((dupIClass & 0xE) << (29 - 1)) | ((dupIClass & 0x1) << 13); - - const MCInst *subInst0 = HMB.getOperand(0).getInst(); - const MCInst *subInst1 = HMB.getOperand(1).getInst(); - - // get subinstruction slot 0 - unsigned subInstSlot0Bits = getBinaryCodeForInstr(*subInst0, Fixups, STI); - // get subinstruction slot 1 - unsigned subInstSlot1Bits = getBinaryCodeForInstr(*subInst1, Fixups, STI); - - Binary |= subInstSlot0Bits | (subInstSlot1Bits << 16); - } support::endian::Writer(OS).write(Binary); ++MCNumEmitted; } diff --git a/lib/Target/Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp b/lib/Target/Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp deleted file mode 100644 index eb629774a2c..00000000000 --- a/lib/Target/Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp +++ /dev/null @@ -1,1100 +0,0 @@ -//===----- HexagonMCDuplexInfo.cpp - Instruction bundle checking ----------===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// This implements duplexing of instructions to reduce code size -// -//===----------------------------------------------------------------------===// - -#include "HexagonBaseInfo.h" -#include "MCTargetDesc/HexagonMCInstrInfo.h" - -#include "llvm/ADT/SmallVector.h" -#include "llvm/Support/Debug.h" -#include "llvm/Support/raw_ostream.h" - -#include - -using namespace llvm; -using namespace Hexagon; - -#define DEBUG_TYPE "hexagon-mcduplex-info" - -// pair table of subInstructions with opcodes -static std::pair opcodeData[] = { - std::make_pair((unsigned)V4_SA1_addi, 0), - std::make_pair((unsigned)V4_SA1_addrx, 6144), - std::make_pair((unsigned)V4_SA1_addsp, 3072), - std::make_pair((unsigned)V4_SA1_and1, 4608), - std::make_pair((unsigned)V4_SA1_clrf, 6768), - std::make_pair((unsigned)V4_SA1_clrfnew, 6736), - std::make_pair((unsigned)V4_SA1_clrt, 6752), - std::make_pair((unsigned)V4_SA1_clrtnew, 6720), - std::make_pair((unsigned)V4_SA1_cmpeqi, 6400), - std::make_pair((unsigned)V4_SA1_combine0i, 7168), - std::make_pair((unsigned)V4_SA1_combine1i, 7176), - std::make_pair((unsigned)V4_SA1_combine2i, 7184), - std::make_pair((unsigned)V4_SA1_combine3i, 7192), - std::make_pair((unsigned)V4_SA1_combinerz, 7432), - std::make_pair((unsigned)V4_SA1_combinezr, 7424), - std::make_pair((unsigned)V4_SA1_dec, 4864), - std::make_pair((unsigned)V4_SA1_inc, 4352), - std::make_pair((unsigned)V4_SA1_seti, 2048), - std::make_pair((unsigned)V4_SA1_setin1, 6656), - std::make_pair((unsigned)V4_SA1_sxtb, 5376), - std::make_pair((unsigned)V4_SA1_sxth, 5120), - std::make_pair((unsigned)V4_SA1_tfr, 4096), - std::make_pair((unsigned)V4_SA1_zxtb, 5888), - std::make_pair((unsigned)V4_SA1_zxth, 5632), - std::make_pair((unsigned)V4_SL1_loadri_io, 0), - std::make_pair((unsigned)V4_SL1_loadrub_io, 4096), - std::make_pair((unsigned)V4_SL2_deallocframe, 7936), - std::make_pair((unsigned)V4_SL2_jumpr31, 8128), - std::make_pair((unsigned)V4_SL2_jumpr31_f, 8133), - std::make_pair((unsigned)V4_SL2_jumpr31_fnew, 8135), - std::make_pair((unsigned)V4_SL2_jumpr31_t, 8132), - std::make_pair((unsigned)V4_SL2_jumpr31_tnew, 8134), - std::make_pair((unsigned)V4_SL2_loadrb_io, 4096), - std::make_pair((unsigned)V4_SL2_loadrd_sp, 7680), - std::make_pair((unsigned)V4_SL2_loadrh_io, 0), - std::make_pair((unsigned)V4_SL2_loadri_sp, 7168), - std::make_pair((unsigned)V4_SL2_loadruh_io, 2048), - std::make_pair((unsigned)V4_SL2_return, 8000), - std::make_pair((unsigned)V4_SL2_return_f, 8005), - std::make_pair((unsigned)V4_SL2_return_fnew, 8007), - std::make_pair((unsigned)V4_SL2_return_t, 8004), - std::make_pair((unsigned)V4_SL2_return_tnew, 8006), - std::make_pair((unsigned)V4_SS1_storeb_io, 4096), - std::make_pair((unsigned)V4_SS1_storew_io, 0), - std::make_pair((unsigned)V4_SS2_allocframe, 7168), - std::make_pair((unsigned)V4_SS2_storebi0, 4608), - std::make_pair((unsigned)V4_SS2_storebi1, 4864), - std::make_pair((unsigned)V4_SS2_stored_sp, 2560), - std::make_pair((unsigned)V4_SS2_storeh_io, 0), - std::make_pair((unsigned)V4_SS2_storew_sp, 2048), - std::make_pair((unsigned)V4_SS2_storewi0, 4096), - std::make_pair((unsigned)V4_SS2_storewi1, 4352)}; - -static std::map - subinstOpcodeMap(opcodeData, - opcodeData + sizeof(opcodeData) / sizeof(opcodeData[0])); - -bool HexagonMCInstrInfo::isDuplexPairMatch(unsigned Ga, unsigned Gb) { - switch (Ga) { - case HexagonII::HSIG_None: - default: - return false; - case HexagonII::HSIG_L1: - return (Gb == HexagonII::HSIG_L1 || Gb == HexagonII::HSIG_A); - case HexagonII::HSIG_L2: - return (Gb == HexagonII::HSIG_L1 || Gb == HexagonII::HSIG_L2 || - Gb == HexagonII::HSIG_A); - case HexagonII::HSIG_S1: - return (Gb == HexagonII::HSIG_L1 || Gb == HexagonII::HSIG_L2 || - Gb == HexagonII::HSIG_S1 || Gb == HexagonII::HSIG_A); - case HexagonII::HSIG_S2: - return (Gb == HexagonII::HSIG_L1 || Gb == HexagonII::HSIG_L2 || - Gb == HexagonII::HSIG_S1 || Gb == HexagonII::HSIG_S2 || - Gb == HexagonII::HSIG_A); - case HexagonII::HSIG_A: - return (Gb == HexagonII::HSIG_A); - case HexagonII::HSIG_Compound: - return (Gb == HexagonII::HSIG_Compound); - } - return false; -} - -unsigned HexagonMCInstrInfo::iClassOfDuplexPair(unsigned Ga, unsigned Gb) { - switch (Ga) { - case HexagonII::HSIG_None: - default: - break; - case HexagonII::HSIG_L1: - switch (Gb) { - default: - break; - case HexagonII::HSIG_L1: - return 0; - case HexagonII::HSIG_A: - return 0x4; - } - case HexagonII::HSIG_L2: - switch (Gb) { - default: - break; - case HexagonII::HSIG_L1: - return 0x1; - case HexagonII::HSIG_L2: - return 0x2; - case HexagonII::HSIG_A: - return 0x5; - } - case HexagonII::HSIG_S1: - switch (Gb) { - default: - break; - case HexagonII::HSIG_L1: - return 0x8; - case HexagonII::HSIG_L2: - return 0x9; - case HexagonII::HSIG_S1: - return 0xA; - case HexagonII::HSIG_A: - return 0x6; - } - case HexagonII::HSIG_S2: - switch (Gb) { - default: - break; - case HexagonII::HSIG_L1: - return 0xC; - case HexagonII::HSIG_L2: - return 0xD; - case HexagonII::HSIG_S1: - return 0xB; - case HexagonII::HSIG_S2: - return 0xE; - case HexagonII::HSIG_A: - return 0x7; - } - case HexagonII::HSIG_A: - switch (Gb) { - default: - break; - case HexagonII::HSIG_A: - return 0x3; - } - case HexagonII::HSIG_Compound: - switch (Gb) { - case HexagonII::HSIG_Compound: - return 0xFFFFFFFF; - } - } - return 0xFFFFFFFF; -} - -unsigned HexagonMCInstrInfo::getDuplexCandidateGroup(MCInst const &MCI) { - unsigned DstReg, PredReg, SrcReg, Src1Reg, Src2Reg; - - switch (MCI.getOpcode()) { - default: - return HexagonII::HSIG_None; - // - // Group L1: - // - // Rd = memw(Rs+#u4:2) - // Rd = memub(Rs+#u4:0) - case Hexagon::L2_loadri_io: - DstReg = MCI.getOperand(0).getReg(); - SrcReg = MCI.getOperand(1).getReg(); - // Special case this one from Group L2. - // Rd = memw(r29+#u5:2) - if (HexagonMCInstrInfo::isIntRegForSubInst(DstReg)) { - if (HexagonMCInstrInfo::isIntReg(SrcReg) && Hexagon::R29 == SrcReg && - MCI.getOperand(2).isImm() && - isShiftedUInt<5, 2>(MCI.getOperand(2).getImm())) { - return HexagonII::HSIG_L2; - } - // Rd = memw(Rs+#u4:2) - if (HexagonMCInstrInfo::isIntRegForSubInst(SrcReg) && - (MCI.getOperand(2).isImm() && - isShiftedUInt<4, 2>(MCI.getOperand(2).getImm()))) { - return HexagonII::HSIG_L1; - } - } - break; - case Hexagon::L2_loadrub_io: - // Rd = memub(Rs+#u4:0) - DstReg = MCI.getOperand(0).getReg(); - SrcReg = MCI.getOperand(1).getReg(); - if (HexagonMCInstrInfo::isIntRegForSubInst(DstReg) && - HexagonMCInstrInfo::isIntRegForSubInst(SrcReg) && - MCI.getOperand(2).isImm() && isUInt<4>(MCI.getOperand(2).getImm())) { - return HexagonII::HSIG_L1; - } - break; - // - // Group L2: - // - // Rd = memh/memuh(Rs+#u3:1) - // Rd = memb(Rs+#u3:0) - // Rd = memw(r29+#u5:2) - Handled above. - // Rdd = memd(r29+#u5:3) - // deallocframe - // [if ([!]p0[.new])] dealloc_return - // [if ([!]p0[.new])] jumpr r31 - case Hexagon::L2_loadrh_io: - case Hexagon::L2_loadruh_io: - // Rd = memh/memuh(Rs+#u3:1) - DstReg = MCI.getOperand(0).getReg(); - SrcReg = MCI.getOperand(1).getReg(); - if (HexagonMCInstrInfo::isIntRegForSubInst(DstReg) && - HexagonMCInstrInfo::isIntRegForSubInst(SrcReg) && - MCI.getOperand(2).isImm() && - isShiftedUInt<3, 1>(MCI.getOperand(2).getImm())) { - return HexagonII::HSIG_L2; - } - break; - case Hexagon::L2_loadrb_io: - // Rd = memb(Rs+#u3:0) - DstReg = MCI.getOperand(0).getReg(); - SrcReg = MCI.getOperand(1).getReg(); - if (HexagonMCInstrInfo::isIntRegForSubInst(DstReg) && - HexagonMCInstrInfo::isIntRegForSubInst(SrcReg) && - MCI.getOperand(2).isImm() && isUInt<3>(MCI.getOperand(2).getImm())) { - return HexagonII::HSIG_L2; - } - break; - case Hexagon::L2_loadrd_io: - // Rdd = memd(r29+#u5:3) - DstReg = MCI.getOperand(0).getReg(); - SrcReg = MCI.getOperand(1).getReg(); - if (HexagonMCInstrInfo::isDblRegForSubInst(DstReg) && - HexagonMCInstrInfo::isIntReg(SrcReg) && Hexagon::R29 == SrcReg && - MCI.getOperand(2).isImm() && - isShiftedUInt<5, 3>(MCI.getOperand(2).getImm())) { - return HexagonII::HSIG_L2; - } - break; - - case Hexagon::L4_return: - - case Hexagon::L2_deallocframe: - - return HexagonII::HSIG_L2; - case Hexagon::EH_RETURN_JMPR: - - case Hexagon::J2_jumpr: - case Hexagon::JMPret: - // jumpr r31 - // Actual form JMPR %PC, %R31, %R0. - DstReg = MCI.getOperand(0).getReg(); - if (Hexagon::R31 == DstReg) { - return HexagonII::HSIG_L2; - } - break; - - case Hexagon::J2_jumprt: - case Hexagon::J2_jumprf: - case Hexagon::J2_jumprtnew: - case Hexagon::J2_jumprfnew: - case Hexagon::JMPrett: - case Hexagon::JMPretf: - case Hexagon::JMPrettnew: - case Hexagon::JMPretfnew: - case Hexagon::JMPrettnewpt: - case Hexagon::JMPretfnewpt: - DstReg = MCI.getOperand(1).getReg(); - SrcReg = MCI.getOperand(0).getReg(); - // [if ([!]p0[.new])] jumpr r31 - if ((HexagonMCInstrInfo::isPredReg(SrcReg) && (Hexagon::P0 == SrcReg)) && - (Hexagon::R31 == DstReg)) { - return HexagonII::HSIG_L2; - } - break; - case Hexagon::L4_return_t: - - case Hexagon::L4_return_f: - - case Hexagon::L4_return_tnew_pnt: - - case Hexagon::L4_return_fnew_pnt: - - case Hexagon::L4_return_tnew_pt: - - case Hexagon::L4_return_fnew_pt: - // [if ([!]p0[.new])] dealloc_return - SrcReg = MCI.getOperand(0).getReg(); - if (Hexagon::P0 == SrcReg) { - return HexagonII::HSIG_L2; - } - break; - // - // Group S1: - // - // memw(Rs+#u4:2) = Rt - // memb(Rs+#u4:0) = Rt - case Hexagon::S2_storeri_io: - // Special case this one from Group S2. - // memw(r29+#u5:2) = Rt - Src1Reg = MCI.getOperand(0).getReg(); - Src2Reg = MCI.getOperand(2).getReg(); - if (HexagonMCInstrInfo::isIntReg(Src1Reg) && - HexagonMCInstrInfo::isIntRegForSubInst(Src2Reg) && - Hexagon::R29 == Src1Reg && MCI.getOperand(1).isImm() && - isShiftedUInt<5, 2>(MCI.getOperand(1).getImm())) { - return HexagonII::HSIG_S2; - } - // memw(Rs+#u4:2) = Rt - if (HexagonMCInstrInfo::isIntRegForSubInst(Src1Reg) && - HexagonMCInstrInfo::isIntRegForSubInst(Src2Reg) && - MCI.getOperand(1).isImm() && - isShiftedUInt<4, 2>(MCI.getOperand(1).getImm())) { - return HexagonII::HSIG_S1; - } - break; - case Hexagon::S2_storerb_io: - // memb(Rs+#u4:0) = Rt - Src1Reg = MCI.getOperand(0).getReg(); - Src2Reg = MCI.getOperand(2).getReg(); - if (HexagonMCInstrInfo::isIntRegForSubInst(Src1Reg) && - HexagonMCInstrInfo::isIntRegForSubInst(Src2Reg) && - MCI.getOperand(1).isImm() && isUInt<4>(MCI.getOperand(1).getImm())) { - return HexagonII::HSIG_S1; - } - break; - // - // Group S2: - // - // memh(Rs+#u3:1) = Rt - // memw(r29+#u5:2) = Rt - // memd(r29+#s6:3) = Rtt - // memw(Rs+#u4:2) = #U1 - // memb(Rs+#u4) = #U1 - // allocframe(#u5:3) - case Hexagon::S2_storerh_io: - // memh(Rs+#u3:1) = Rt - Src1Reg = MCI.getOperand(0).getReg(); - Src2Reg = MCI.getOperand(2).getReg(); - if (HexagonMCInstrInfo::isIntRegForSubInst(Src1Reg) && - HexagonMCInstrInfo::isIntRegForSubInst(Src2Reg) && - MCI.getOperand(1).isImm() && - isShiftedUInt<3, 1>(MCI.getOperand(1).getImm())) { - return HexagonII::HSIG_S2; - } - break; - case Hexagon::S2_storerd_io: - // memd(r29+#s6:3) = Rtt - Src1Reg = MCI.getOperand(0).getReg(); - Src2Reg = MCI.getOperand(2).getReg(); - if (HexagonMCInstrInfo::isDblRegForSubInst(Src2Reg) && - HexagonMCInstrInfo::isIntReg(Src1Reg) && Hexagon::R29 == Src1Reg && - MCI.getOperand(1).isImm() && - isShiftedInt<6, 3>(MCI.getOperand(1).getImm())) { - return HexagonII::HSIG_S2; - } - break; - case Hexagon::S4_storeiri_io: - // memw(Rs+#u4:2) = #U1 - Src1Reg = MCI.getOperand(0).getReg(); - if (HexagonMCInstrInfo::isIntRegForSubInst(Src1Reg) && - MCI.getOperand(1).isImm() && - isShiftedUInt<4, 2>(MCI.getOperand(1).getImm()) && - MCI.getOperand(2).isImm() && isUInt<1>(MCI.getOperand(2).getImm())) { - return HexagonII::HSIG_S2; - } - break; - case Hexagon::S4_storeirb_io: - // memb(Rs+#u4) = #U1 - Src1Reg = MCI.getOperand(0).getReg(); - if (HexagonMCInstrInfo::isIntRegForSubInst(Src1Reg) && - MCI.getOperand(1).isImm() && isUInt<4>(MCI.getOperand(1).getImm()) && - MCI.getOperand(2).isImm() && MCI.getOperand(2).isImm() && - isUInt<1>(MCI.getOperand(2).getImm())) { - return HexagonII::HSIG_S2; - } - break; - case Hexagon::S2_allocframe: - if (MCI.getOperand(0).isImm() && - isShiftedUInt<5, 3>(MCI.getOperand(0).getImm())) { - return HexagonII::HSIG_S2; - } - break; - // - // Group A: - // - // Rx = add(Rx,#s7) - // Rd = Rs - // Rd = #u6 - // Rd = #-1 - // if ([!]P0[.new]) Rd = #0 - // Rd = add(r29,#u6:2) - // Rx = add(Rx,Rs) - // P0 = cmp.eq(Rs,#u2) - // Rdd = combine(#0,Rs) - // Rdd = combine(Rs,#0) - // Rdd = combine(#u2,#U2) - // Rd = add(Rs,#1) - // Rd = add(Rs,#-1) - // Rd = sxth/sxtb/zxtb/zxth(Rs) - // Rd = and(Rs,#1) - case Hexagon::A2_addi: - DstReg = MCI.getOperand(0).getReg(); - SrcReg = MCI.getOperand(1).getReg(); - if (HexagonMCInstrInfo::isIntRegForSubInst(DstReg)) { - // Rd = add(r29,#u6:2) - if (HexagonMCInstrInfo::isIntReg(SrcReg) && Hexagon::R29 == SrcReg && - MCI.getOperand(2).isImm() && - isShiftedUInt<6, 2>(MCI.getOperand(2).getImm())) { - return HexagonII::HSIG_A; - } - // Rx = add(Rx,#s7) - if (DstReg == SrcReg) { - return HexagonII::HSIG_A; - } - // Rd = add(Rs,#1) - // Rd = add(Rs,#-1) - if (HexagonMCInstrInfo::isIntRegForSubInst(SrcReg) && - MCI.getOperand(2).isImm() && ((MCI.getOperand(2).getImm() == 1) || - (MCI.getOperand(2).getImm() == -1))) { - return HexagonII::HSIG_A; - } - } - break; - case Hexagon::A2_add: - // Rx = add(Rx,Rs) - DstReg = MCI.getOperand(0).getReg(); - Src1Reg = MCI.getOperand(1).getReg(); - Src2Reg = MCI.getOperand(2).getReg(); - if (HexagonMCInstrInfo::isIntRegForSubInst(DstReg) && (DstReg == Src1Reg) && - HexagonMCInstrInfo::isIntRegForSubInst(Src2Reg)) { - return HexagonII::HSIG_A; - } - break; - case Hexagon::A2_andir: - DstReg = MCI.getOperand(0).getReg(); - SrcReg = MCI.getOperand(1).getReg(); - if (HexagonMCInstrInfo::isIntRegForSubInst(DstReg) && - HexagonMCInstrInfo::isIntRegForSubInst(SrcReg) && - MCI.getOperand(2).isImm() && ((MCI.getOperand(2).getImm() == 1) || - (MCI.getOperand(2).getImm() == 255))) { - return HexagonII::HSIG_A; - } - break; - case Hexagon::A2_tfr: - // Rd = Rs - DstReg = MCI.getOperand(0).getReg(); - SrcReg = MCI.getOperand(1).getReg(); - if (HexagonMCInstrInfo::isIntRegForSubInst(DstReg) && - HexagonMCInstrInfo::isIntRegForSubInst(SrcReg)) { - return HexagonII::HSIG_A; - } - break; - case Hexagon::A2_tfrsi: - DstReg = MCI.getOperand(0).getReg(); - - if (HexagonMCInstrInfo::isIntRegForSubInst(DstReg)) { - return HexagonII::HSIG_A; - } - break; - case Hexagon::C2_cmoveit: - case Hexagon::C2_cmovenewit: - case Hexagon::C2_cmoveif: - case Hexagon::C2_cmovenewif: - // if ([!]P0[.new]) Rd = #0 - // Actual form: - // %R16 = C2_cmovenewit %P0, 0, %R16; - DstReg = MCI.getOperand(0).getReg(); // Rd - PredReg = MCI.getOperand(1).getReg(); // P0 - if (HexagonMCInstrInfo::isIntRegForSubInst(DstReg) && - Hexagon::P0 == PredReg && MCI.getOperand(2).isImm() && - MCI.getOperand(2).getImm() == 0) { - return HexagonII::HSIG_A; - } - break; - case Hexagon::C2_cmpeqi: - // P0 = cmp.eq(Rs,#u2) - DstReg = MCI.getOperand(0).getReg(); - SrcReg = MCI.getOperand(1).getReg(); - if (Hexagon::P0 == DstReg && - HexagonMCInstrInfo::isIntRegForSubInst(SrcReg) && - MCI.getOperand(2).isImm() && isUInt<2>(MCI.getOperand(2).getImm())) { - return HexagonII::HSIG_A; - } - break; - case Hexagon::A2_combineii: - case Hexagon::A4_combineii: - // Rdd = combine(#u2,#U2) - DstReg = MCI.getOperand(0).getReg(); - if (HexagonMCInstrInfo::isDblRegForSubInst(DstReg) && - // TODO: Handle Globals/Symbols - (MCI.getOperand(1).isImm() && isUInt<2>(MCI.getOperand(1).getImm())) && - ((MCI.getOperand(2).isImm() && - isUInt<2>(MCI.getOperand(2).getImm())))) { - return HexagonII::HSIG_A; - } - break; - case Hexagon::A4_combineri: - // Rdd = combine(Rs,#0) - DstReg = MCI.getOperand(0).getReg(); - SrcReg = MCI.getOperand(1).getReg(); - if (HexagonMCInstrInfo::isDblRegForSubInst(DstReg) && - HexagonMCInstrInfo::isIntRegForSubInst(SrcReg) && - (MCI.getOperand(2).isImm() && MCI.getOperand(2).getImm() == 0)) { - return HexagonII::HSIG_A; - } - break; - case Hexagon::A4_combineir: - // Rdd = combine(#0,Rs) - DstReg = MCI.getOperand(0).getReg(); - SrcReg = MCI.getOperand(2).getReg(); - if (HexagonMCInstrInfo::isDblRegForSubInst(DstReg) && - HexagonMCInstrInfo::isIntRegForSubInst(SrcReg) && - (MCI.getOperand(1).isImm() && MCI.getOperand(1).getImm() == 0)) { - return HexagonII::HSIG_A; - } - break; - case Hexagon::A2_sxtb: - case Hexagon::A2_sxth: - case Hexagon::A2_zxtb: - case Hexagon::A2_zxth: - // Rd = sxth/sxtb/zxtb/zxth(Rs) - DstReg = MCI.getOperand(0).getReg(); - SrcReg = MCI.getOperand(1).getReg(); - if (HexagonMCInstrInfo::isIntRegForSubInst(DstReg) && - HexagonMCInstrInfo::isIntRegForSubInst(SrcReg)) { - return HexagonII::HSIG_A; - } - break; - } - - return HexagonII::HSIG_None; -} - -bool HexagonMCInstrInfo::subInstWouldBeExtended(MCInst const &potentialDuplex) { - - unsigned DstReg, SrcReg; - - switch (potentialDuplex.getOpcode()) { - case Hexagon::A2_addi: - // testing for case of: Rx = add(Rx,#s7) - DstReg = potentialDuplex.getOperand(0).getReg(); - SrcReg = potentialDuplex.getOperand(1).getReg(); - if (DstReg == SrcReg && HexagonMCInstrInfo::isIntRegForSubInst(DstReg)) { - if (potentialDuplex.getOperand(2).isExpr()) - return true; - if (potentialDuplex.getOperand(2).isImm() && - !(isShiftedInt<7, 0>(potentialDuplex.getOperand(2).getImm()))) - return true; - } - break; - case Hexagon::A2_tfrsi: - DstReg = potentialDuplex.getOperand(0).getReg(); - - if (HexagonMCInstrInfo::isIntRegForSubInst(DstReg)) { - if (potentialDuplex.getOperand(1).isExpr()) - return true; - // Check for case of Rd = #-1. - if (potentialDuplex.getOperand(1).isImm() && - (potentialDuplex.getOperand(1).getImm() == -1)) - return false; - // Check for case of Rd = #u6. - if (potentialDuplex.getOperand(1).isImm() && - !isShiftedUInt<6, 0>(potentialDuplex.getOperand(1).getImm())) - return true; - } - break; - default: - break; - } - return false; -} - -/// non-Symmetrical. See if these two instructions are fit for duplex pair. -bool HexagonMCInstrInfo::isOrderedDuplexPair(MCInstrInfo const &MCII, - MCInst const &MIa, bool ExtendedA, - MCInst const &MIb, bool ExtendedB, - bool bisReversable) { - // Slot 1 cannot be extended in duplexes PRM 10.5 - if (ExtendedA) - return false; - // Only A2_addi and A2_tfrsi can be extended in duplex form PRM 10.5 - if (ExtendedB) { - unsigned Opcode = MIb.getOpcode(); - if ((Opcode != Hexagon::A2_addi) && (Opcode != Hexagon::A2_tfrsi)) - return false; - } - unsigned MIaG = HexagonMCInstrInfo::getDuplexCandidateGroup(MIa), - MIbG = HexagonMCInstrInfo::getDuplexCandidateGroup(MIb); - - // If a duplex contains 2 insns in the same group, the insns must be - // ordered such that the numerically smaller opcode is in slot 1. - if ((MIaG != HexagonII::HSIG_None) && (MIaG == MIbG) && bisReversable) { - MCInst SubInst0 = HexagonMCInstrInfo::deriveSubInst(MIa); - MCInst SubInst1 = HexagonMCInstrInfo::deriveSubInst(MIb); - - unsigned zeroedSubInstS0 = - subinstOpcodeMap.find(SubInst0.getOpcode())->second; - unsigned zeroedSubInstS1 = - subinstOpcodeMap.find(SubInst1.getOpcode())->second; - - if (zeroedSubInstS0 < zeroedSubInstS1) - // subinstS0 (maps to slot 0) must be greater than - // subinstS1 (maps to slot 1) - return false; - } - - // allocframe must always be in slot 0 - if (MIb.getOpcode() == Hexagon::S2_allocframe) - return false; - - if ((MIaG != HexagonII::HSIG_None) && (MIbG != HexagonII::HSIG_None)) { - // Prevent 2 instructions with extenders from duplexing - // Note that MIb (slot1) can be extended and MIa (slot0) - // can never be extended - if (subInstWouldBeExtended(MIa)) - return false; - - // If duplexing produces an extender, but the original did not - // have an extender, do not duplex. - if (subInstWouldBeExtended(MIb) && !ExtendedB) - return false; - } - - // If jumpr r31 appears, it must be in slot 0, and never slot 1 (MIb). - if (MIbG == HexagonII::HSIG_L2) { - if ((MIb.getNumOperands() > 1) && MIb.getOperand(1).isReg() && - (MIb.getOperand(1).getReg() == Hexagon::R31)) - return false; - if ((MIb.getNumOperands() > 0) && MIb.getOperand(0).isReg() && - (MIb.getOperand(0).getReg() == Hexagon::R31)) - return false; - } - - // If a store appears, it must be in slot 0 (MIa) 1st, and then slot 1 (MIb); - // therefore, not duplexable if slot 1 is a store, and slot 0 is not. - if ((MIbG == HexagonII::HSIG_S1) || (MIbG == HexagonII::HSIG_S2)) { - if ((MIaG != HexagonII::HSIG_S1) && (MIaG != HexagonII::HSIG_S2)) - return false; - } - - return (isDuplexPairMatch(MIaG, MIbG)); -} - -/// Symmetrical. See if these two instructions are fit for duplex pair. -bool HexagonMCInstrInfo::isDuplexPair(MCInst const &MIa, MCInst const &MIb) { - unsigned MIaG = getDuplexCandidateGroup(MIa), - MIbG = getDuplexCandidateGroup(MIb); - return (isDuplexPairMatch(MIaG, MIbG) || isDuplexPairMatch(MIbG, MIaG)); -} - -inline static void addOps(MCInst &subInstPtr, MCInst const &Inst, - unsigned opNum) { - if (Inst.getOperand(opNum).isReg()) { - switch (Inst.getOperand(opNum).getReg()) { - default: - llvm_unreachable("Not Duplexable Register"); - break; - case Hexagon::R0: - case Hexagon::R1: - case Hexagon::R2: - case Hexagon::R3: - case Hexagon::R4: - case Hexagon::R5: - case Hexagon::R6: - case Hexagon::R7: - case Hexagon::D0: - case Hexagon::D1: - case Hexagon::D2: - case Hexagon::D3: - case Hexagon::R16: - case Hexagon::R17: - case Hexagon::R18: - case Hexagon::R19: - case Hexagon::R20: - case Hexagon::R21: - case Hexagon::R22: - case Hexagon::R23: - case Hexagon::D8: - case Hexagon::D9: - case Hexagon::D10: - case Hexagon::D11: - subInstPtr.addOperand(Inst.getOperand(opNum)); - break; - } - } else - subInstPtr.addOperand(Inst.getOperand(opNum)); -} - -MCInst HexagonMCInstrInfo::deriveSubInst(MCInst const &Inst) { - MCInst Result; - switch (Inst.getOpcode()) { - default: - // dbgs() << "opcode: "<< Inst->getOpcode() << "\n"; - llvm_unreachable("Unimplemented subinstruction \n"); - break; - case Hexagon::A2_addi: - if (Inst.getOperand(2).isImm() && Inst.getOperand(2).getImm() == 1) { - Result.setOpcode(Hexagon::V4_SA1_inc); - addOps(Result, Inst, 0); - addOps(Result, Inst, 1); - break; - } // 1,2 SUBInst $Rd = add($Rs, #1) - else if (Inst.getOperand(2).isImm() && Inst.getOperand(2).getImm() == -1) { - Result.setOpcode(Hexagon::V4_SA1_dec); - addOps(Result, Inst, 0); - addOps(Result, Inst, 1); - break; - } // 1,2 SUBInst $Rd = add($Rs,#-1) - else if (Inst.getOperand(1).getReg() == Hexagon::R29) { - Result.setOpcode(Hexagon::V4_SA1_addsp); - addOps(Result, Inst, 0); - addOps(Result, Inst, 2); - break; - } // 1,3 SUBInst $Rd = add(r29, #$u6_2) - else { - Result.setOpcode(Hexagon::V4_SA1_addi); - addOps(Result, Inst, 0); - addOps(Result, Inst, 1); - addOps(Result, Inst, 2); - break; - } // 1,2,3 SUBInst $Rx = add($Rx, #$s7) - case Hexagon::A2_add: - Result.setOpcode(Hexagon::V4_SA1_addrx); - addOps(Result, Inst, 0); - addOps(Result, Inst, 1); - addOps(Result, Inst, 2); - break; // 1,2,3 SUBInst $Rx = add($_src_, $Rs) - case Hexagon::S2_allocframe: - Result.setOpcode(Hexagon::V4_SS2_allocframe); - addOps(Result, Inst, 0); - break; // 1 SUBInst allocframe(#$u5_3) - case Hexagon::A2_andir: - if (Inst.getOperand(2).getImm() == 255) { - Result.setOpcode(Hexagon::V4_SA1_zxtb); - addOps(Result, Inst, 0); - addOps(Result, Inst, 1); - break; // 1,2 $Rd = and($Rs, #255) - } else { - Result.setOpcode(Hexagon::V4_SA1_and1); - addOps(Result, Inst, 0); - addOps(Result, Inst, 1); - break; // 1,2 SUBInst $Rd = and($Rs, #1) - } - case Hexagon::C2_cmpeqi: - Result.setOpcode(Hexagon::V4_SA1_cmpeqi); - addOps(Result, Inst, 1); - addOps(Result, Inst, 2); - break; // 2,3 SUBInst p0 = cmp.eq($Rs, #$u2) - case Hexagon::A4_combineii: - case Hexagon::A2_combineii: - if (Inst.getOperand(1).getImm() == 1) { - Result.setOpcode(Hexagon::V4_SA1_combine1i); - addOps(Result, Inst, 0); - addOps(Result, Inst, 2); - break; // 1,3 SUBInst $Rdd = combine(#1, #$u2) - } - - if (Inst.getOperand(1).getImm() == 3) { - Result.setOpcode(Hexagon::V4_SA1_combine3i); - addOps(Result, Inst, 0); - addOps(Result, Inst, 2); - break; // 1,3 SUBInst $Rdd = combine(#3, #$u2) - } - if (Inst.getOperand(1).getImm() == 0) { - Result.setOpcode(Hexagon::V4_SA1_combine0i); - addOps(Result, Inst, 0); - addOps(Result, Inst, 2); - break; // 1,3 SUBInst $Rdd = combine(#0, #$u2) - } - if (Inst.getOperand(1).getImm() == 2) { - Result.setOpcode(Hexagon::V4_SA1_combine2i); - addOps(Result, Inst, 0); - addOps(Result, Inst, 2); - break; // 1,3 SUBInst $Rdd = combine(#2, #$u2) - } - case Hexagon::A4_combineir: - Result.setOpcode(Hexagon::V4_SA1_combinezr); - addOps(Result, Inst, 0); - addOps(Result, Inst, 2); - break; // 1,3 SUBInst $Rdd = combine(#0, $Rs) - - case Hexagon::A4_combineri: - Result.setOpcode(Hexagon::V4_SA1_combinerz); - addOps(Result, Inst, 0); - addOps(Result, Inst, 1); - break; // 1,2 SUBInst $Rdd = combine($Rs, #0) - case Hexagon::L4_return_tnew_pnt: - case Hexagon::L4_return_tnew_pt: - Result.setOpcode(Hexagon::V4_SL2_return_tnew); - break; // none SUBInst if (p0.new) dealloc_return:nt - case Hexagon::L4_return_fnew_pnt: - case Hexagon::L4_return_fnew_pt: - Result.setOpcode(Hexagon::V4_SL2_return_fnew); - break; // none SUBInst if (!p0.new) dealloc_return:nt - case Hexagon::L4_return_f: - Result.setOpcode(Hexagon::V4_SL2_return_f); - break; // none SUBInst if (!p0) dealloc_return - case Hexagon::L4_return_t: - Result.setOpcode(Hexagon::V4_SL2_return_t); - break; // none SUBInst if (p0) dealloc_return - case Hexagon::L4_return: - Result.setOpcode(Hexagon::V4_SL2_return); - break; // none SUBInst dealloc_return - case Hexagon::L2_deallocframe: - Result.setOpcode(Hexagon::V4_SL2_deallocframe); - break; // none SUBInst deallocframe - case Hexagon::EH_RETURN_JMPR: - case Hexagon::J2_jumpr: - case Hexagon::JMPret: - Result.setOpcode(Hexagon::V4_SL2_jumpr31); - break; // none SUBInst jumpr r31 - case Hexagon::J2_jumprf: - case Hexagon::JMPretf: - Result.setOpcode(Hexagon::V4_SL2_jumpr31_f); - break; // none SUBInst if (!p0) jumpr r31 - case Hexagon::J2_jumprfnew: - case Hexagon::JMPretfnewpt: - case Hexagon::JMPretfnew: - Result.setOpcode(Hexagon::V4_SL2_jumpr31_fnew); - break; // none SUBInst if (!p0.new) jumpr:nt r31 - case Hexagon::J2_jumprt: - case Hexagon::JMPrett: - Result.setOpcode(Hexagon::V4_SL2_jumpr31_t); - break; // none SUBInst if (p0) jumpr r31 - case Hexagon::J2_jumprtnew: - case Hexagon::JMPrettnewpt: - case Hexagon::JMPrettnew: - Result.setOpcode(Hexagon::V4_SL2_jumpr31_tnew); - break; // none SUBInst if (p0.new) jumpr:nt r31 - case Hexagon::L2_loadrb_io: - Result.setOpcode(Hexagon::V4_SL2_loadrb_io); - addOps(Result, Inst, 0); - addOps(Result, Inst, 1); - addOps(Result, Inst, 2); - break; // 1,2,3 SUBInst $Rd = memb($Rs + #$u3_0) - case Hexagon::L2_loadrd_io: - Result.setOpcode(Hexagon::V4_SL2_loadrd_sp); - addOps(Result, Inst, 0); - addOps(Result, Inst, 2); - break; // 1,3 SUBInst $Rdd = memd(r29 + #$u5_3) - case Hexagon::L2_loadrh_io: - Result.setOpcode(Hexagon::V4_SL2_loadrh_io); - addOps(Result, Inst, 0); - addOps(Result, Inst, 1); - addOps(Result, Inst, 2); - break; // 1,2,3 SUBInst $Rd = memh($Rs + #$u3_1) - case Hexagon::L2_loadrub_io: - Result.setOpcode(Hexagon::V4_SL1_loadrub_io); - addOps(Result, Inst, 0); - addOps(Result, Inst, 1); - addOps(Result, Inst, 2); - break; // 1,2,3 SUBInst $Rd = memub($Rs + #$u4_0) - case Hexagon::L2_loadruh_io: - Result.setOpcode(Hexagon::V4_SL2_loadruh_io); - addOps(Result, Inst, 0); - addOps(Result, Inst, 1); - addOps(Result, Inst, 2); - break; // 1,2,3 SUBInst $Rd = memuh($Rs + #$u3_1) - case Hexagon::L2_loadri_io: - if (Inst.getOperand(1).getReg() == Hexagon::R29) { - Result.setOpcode(Hexagon::V4_SL2_loadri_sp); - addOps(Result, Inst, 0); - addOps(Result, Inst, 2); - break; // 2 1,3 SUBInst $Rd = memw(r29 + #$u5_2) - } else { - Result.setOpcode(Hexagon::V4_SL1_loadri_io); - addOps(Result, Inst, 0); - addOps(Result, Inst, 1); - addOps(Result, Inst, 2); - break; // 1,2,3 SUBInst $Rd = memw($Rs + #$u4_2) - } - case Hexagon::S4_storeirb_io: - if (Inst.getOperand(2).getImm() == 0) { - Result.setOpcode(Hexagon::V4_SS2_storebi0); - addOps(Result, Inst, 0); - addOps(Result, Inst, 1); - break; // 1,2 SUBInst memb($Rs + #$u4_0)=#0 - } else if (Inst.getOperand(2).getImm() == 1) { - Result.setOpcode(Hexagon::V4_SS2_storebi1); - addOps(Result, Inst, 0); - addOps(Result, Inst, 1); - break; // 2 1,2 SUBInst memb($Rs + #$u4_0)=#1 - } - case Hexagon::S2_storerb_io: - Result.setOpcode(Hexagon::V4_SS1_storeb_io); - addOps(Result, Inst, 0); - addOps(Result, Inst, 1); - addOps(Result, Inst, 2); - break; // 1,2,3 SUBInst memb($Rs + #$u4_0) = $Rt - case Hexagon::S2_storerd_io: - Result.setOpcode(Hexagon::V4_SS2_stored_sp); - addOps(Result, Inst, 1); - addOps(Result, Inst, 2); - break; // 2,3 SUBInst memd(r29 + #$s6_3) = $Rtt - case Hexagon::S2_storerh_io: - Result.setOpcode(Hexagon::V4_SS2_storeh_io); - addOps(Result, Inst, 0); - addOps(Result, Inst, 1); - addOps(Result, Inst, 2); - break; // 1,2,3 SUBInst memb($Rs + #$u4_0) = $Rt - case Hexagon::S4_storeiri_io: - if (Inst.getOperand(2).getImm() == 0) { - Result.setOpcode(Hexagon::V4_SS2_storewi0); - addOps(Result, Inst, 0); - addOps(Result, Inst, 1); - break; // 3 1,2 SUBInst memw($Rs + #$u4_2)=#0 - } else if (Inst.getOperand(2).getImm() == 1) { - Result.setOpcode(Hexagon::V4_SS2_storewi1); - addOps(Result, Inst, 0); - addOps(Result, Inst, 1); - break; // 3 1,2 SUBInst memw($Rs + #$u4_2)=#1 - } else if (Inst.getOperand(0).getReg() == Hexagon::R29) { - Result.setOpcode(Hexagon::V4_SS2_storew_sp); - addOps(Result, Inst, 1); - addOps(Result, Inst, 2); - break; // 1 2,3 SUBInst memw(r29 + #$u5_2) = $Rt - } - case Hexagon::S2_storeri_io: - if (Inst.getOperand(0).getReg() == Hexagon::R29) { - Result.setOpcode(Hexagon::V4_SS2_storew_sp); - addOps(Result, Inst, 1); - addOps(Result, Inst, 2); // 1,2,3 SUBInst memw(sp + #$u5_2) = $Rt - } else { - Result.setOpcode(Hexagon::V4_SS1_storew_io); - addOps(Result, Inst, 0); - addOps(Result, Inst, 1); - addOps(Result, Inst, 2); // 1,2,3 SUBInst memw($Rs + #$u4_2) = $Rt - } - break; - case Hexagon::A2_sxtb: - Result.setOpcode(Hexagon::V4_SA1_sxtb); - addOps(Result, Inst, 0); - addOps(Result, Inst, 1); - break; // 1,2 SUBInst $Rd = sxtb($Rs) - case Hexagon::A2_sxth: - Result.setOpcode(Hexagon::V4_SA1_sxth); - addOps(Result, Inst, 0); - addOps(Result, Inst, 1); - break; // 1,2 SUBInst $Rd = sxth($Rs) - case Hexagon::A2_tfr: - Result.setOpcode(Hexagon::V4_SA1_tfr); - addOps(Result, Inst, 0); - addOps(Result, Inst, 1); - break; // 1,2 SUBInst $Rd = $Rs - case Hexagon::C2_cmovenewif: - Result.setOpcode(Hexagon::V4_SA1_clrfnew); - addOps(Result, Inst, 0); - break; // 2 SUBInst if (!p0.new) $Rd = #0 - case Hexagon::C2_cmovenewit: - Result.setOpcode(Hexagon::V4_SA1_clrtnew); - addOps(Result, Inst, 0); - break; // 2 SUBInst if (p0.new) $Rd = #0 - case Hexagon::C2_cmoveif: - Result.setOpcode(Hexagon::V4_SA1_clrf); - addOps(Result, Inst, 0); - break; // 2 SUBInst if (!p0) $Rd = #0 - case Hexagon::C2_cmoveit: - Result.setOpcode(Hexagon::V4_SA1_clrt); - addOps(Result, Inst, 0); - break; // 2 SUBInst if (p0) $Rd = #0 - case Hexagon::A2_tfrsi: - if (Inst.getOperand(1).isImm() && Inst.getOperand(1).getImm() == -1) { - Result.setOpcode(Hexagon::V4_SA1_setin1); - addOps(Result, Inst, 0); - break; // 2 1 SUBInst $Rd = #-1 - } else { - Result.setOpcode(Hexagon::V4_SA1_seti); - addOps(Result, Inst, 0); - addOps(Result, Inst, 1); - break; // 1,2 SUBInst $Rd = #$u6 - } - case Hexagon::A2_zxtb: - Result.setOpcode(Hexagon::V4_SA1_zxtb); - addOps(Result, Inst, 0); - addOps(Result, Inst, 1); - break; // 1,2 $Rd = and($Rs, #255) - - case Hexagon::A2_zxth: - Result.setOpcode(Hexagon::V4_SA1_zxth); - addOps(Result, Inst, 0); - addOps(Result, Inst, 1); - break; // 1,2 SUBInst $Rd = zxth($Rs) - } - return Result; -} - -static bool isStoreInst(unsigned opCode) { - switch (opCode) { - case Hexagon::S2_storeri_io: - case Hexagon::S2_storerb_io: - case Hexagon::S2_storerh_io: - case Hexagon::S2_storerd_io: - case Hexagon::S4_storeiri_io: - case Hexagon::S4_storeirb_io: - case Hexagon::S2_allocframe: - return true; - default: - return false; - } -} - -SmallVector -HexagonMCInstrInfo::getDuplexPossibilties(MCInstrInfo const &MCII, - MCInst const &MCB) { - assert(isBundle(MCB)); - SmallVector duplexToTry; - // Use an "order matters" version of isDuplexPair. - unsigned numInstrInPacket = MCB.getNumOperands(); - - for (unsigned distance = 1; distance < numInstrInPacket; ++distance) { - for (unsigned j = HexagonMCInstrInfo::bundleInstructionsOffset, - k = j + distance; - (j < numInstrInPacket) && (k < numInstrInPacket); ++j, ++k) { - - // Check if reversable. - bool bisReversable = true; - if (isStoreInst(MCB.getOperand(j).getInst()->getOpcode()) && - isStoreInst(MCB.getOperand(k).getInst()->getOpcode())) { - DEBUG(dbgs() << "skip out of order write pair: " << k << "," << j - << "\n"); - bisReversable = false; - } - - // Try in order. - if (isOrderedDuplexPair( - MCII, *MCB.getOperand(k).getInst(), - HexagonMCInstrInfo::hasExtenderForIndex(MCB, k - 1), - *MCB.getOperand(j).getInst(), - HexagonMCInstrInfo::hasExtenderForIndex(MCB, j - 1), - bisReversable)) { - // Get iClass. - unsigned iClass = iClassOfDuplexPair( - getDuplexCandidateGroup(*MCB.getOperand(k).getInst()), - getDuplexCandidateGroup(*MCB.getOperand(j).getInst())); - - // Save off pairs for duplex checking. - duplexToTry.push_back(DuplexCandidate(j, k, iClass)); - DEBUG(dbgs() << "adding pair: " << j << "," << k << ":" - << MCB.getOperand(j).getInst()->getOpcode() << "," - << MCB.getOperand(k).getInst()->getOpcode() << "\n"); - continue; - } else { - DEBUG(dbgs() << "skipping pair: " << j << "," << k << ":" - << MCB.getOperand(j).getInst()->getOpcode() << "," - << MCB.getOperand(k).getInst()->getOpcode() << "\n"); - } - - // Try reverse. - if (bisReversable) { - if (isOrderedDuplexPair( - MCII, *MCB.getOperand(j).getInst(), - HexagonMCInstrInfo::hasExtenderForIndex(MCB, j - 1), - *MCB.getOperand(k).getInst(), - HexagonMCInstrInfo::hasExtenderForIndex(MCB, k - 1), - bisReversable)) { - // Get iClass. - unsigned iClass = iClassOfDuplexPair( - getDuplexCandidateGroup(*MCB.getOperand(j).getInst()), - getDuplexCandidateGroup(*MCB.getOperand(k).getInst())); - - // Save off pairs for duplex checking. - duplexToTry.push_back(DuplexCandidate(k, j, iClass)); - DEBUG(dbgs() << "adding pair:" << k << "," << j << ":" - << MCB.getOperand(j).getInst()->getOpcode() << "," - << MCB.getOperand(k).getInst()->getOpcode() << "\n"); - } else { - DEBUG(dbgs() << "skipping pair: " << k << "," << j << ":" - << MCB.getOperand(j).getInst()->getOpcode() << "," - << MCB.getOperand(k).getInst()->getOpcode() << "\n"); - } - } - } - } - return duplexToTry; -} diff --git a/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp b/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp index 2731278f0e4..7b0760e8318 100644 --- a/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp +++ b/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp @@ -16,8 +16,6 @@ #include "Hexagon.h" #include "HexagonBaseInfo.h" -#include "llvm/MC/MCContext.h" -#include "llvm/MC/MCInstrInfo.h" #include "llvm/MC/MCSubtargetInfo.h" namespace llvm { @@ -35,32 +33,6 @@ size_t HexagonMCInstrInfo::bundleSize(MCInst const &MCI) { return (1); } -MCInst *HexagonMCInstrInfo::deriveDuplex(MCContext &Context, unsigned iClass, - MCInst const &inst0, - MCInst const &inst1) { - assert((iClass <= 0xf) && "iClass must have range of 0 to 0xf"); - MCInst *duplexInst = new (Context) MCInst; - duplexInst->setOpcode(Hexagon::DuplexIClass0 + iClass); - - MCInst *SubInst0 = new (Context) MCInst(deriveSubInst(inst0)); - MCInst *SubInst1 = new (Context) MCInst(deriveSubInst(inst1)); - duplexInst->addOperand(MCOperand::createInst(SubInst0)); - duplexInst->addOperand(MCOperand::createInst(SubInst1)); - return duplexInst; -} - -MCInst const *HexagonMCInstrInfo::extenderForIndex(MCInst const &MCB, - size_t Index) { - assert(Index <= bundleSize(MCB)); - if (Index == 0) - return nullptr; - MCInst const *Inst = - MCB.getOperand(Index + bundleInstructionsOffset - 1).getInst(); - if (isImmext(*Inst)) - return Inst; - return nullptr; -} - HexagonII::MemAccessSize HexagonMCInstrInfo::getAccessSize(MCInstrInfo const &MCII, MCInst const &MCI) { const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; @@ -216,10 +188,6 @@ bool HexagonMCInstrInfo::hasImmExt(MCInst const &MCI) { return false; } -bool HexagonMCInstrInfo::hasExtenderForIndex(MCInst const &MCB, size_t Index) { - return extenderForIndex(MCB, Index) != nullptr; -} - // Return whether the instruction is a legal new-value producer. bool HexagonMCInstrInfo::hasNewValue(MCInstrInfo const &MCII, MCInst const &MCI) { @@ -246,15 +214,6 @@ bool HexagonMCInstrInfo::isCanon(MCInstrInfo const &MCII, MCInst const &MCI) { HexagonMCInstrInfo::getType(MCII, MCI) != HexagonII::TypeENDLOOP); } -bool HexagonMCInstrInfo::isDblRegForSubInst(unsigned Reg) { - return ((Reg >= Hexagon::D0 && Reg <= Hexagon::D3) || - (Reg >= Hexagon::D8 && Reg <= Hexagon::D11)); -} - -bool HexagonMCInstrInfo::isDuplex(MCInstrInfo const &MCII, MCInst const &MCI) { - return HexagonII::TypeDUPLEX == HexagonMCInstrInfo::getType(MCII, MCI); -} - // Return whether the instruction needs to be constant extended. // 1) Always return true if the instruction has 'isExtended' flag set. // @@ -322,15 +281,6 @@ bool HexagonMCInstrInfo::isInnerLoop(MCInst const &MCI) { return (Flags & innerLoopMask) != 0; } -bool HexagonMCInstrInfo::isIntReg(unsigned Reg) { - return (Reg >= Hexagon::R0 && Reg <= Hexagon::R31); -} - -bool HexagonMCInstrInfo::isIntRegForSubInst(unsigned Reg) { - return ((Reg >= Hexagon::R0 && Reg <= Hexagon::R7) || - (Reg >= Hexagon::R16 && Reg <= Hexagon::R23)); -} - // Return whether the insn is a new-value consumer. bool HexagonMCInstrInfo::isNewValue(MCInstrInfo const &MCII, MCInst const &MCI) { @@ -366,10 +316,6 @@ bool HexagonMCInstrInfo::isPredicatedTrue(MCInstrInfo const &MCII, !((F >> HexagonII::PredicatedFalsePos) & HexagonII::PredicatedFalseMask)); } -bool HexagonMCInstrInfo::isPredReg(unsigned Reg) { - return (Reg >= Hexagon::P0 && Reg <= Hexagon::P3_0); -} - bool HexagonMCInstrInfo::isPrefix(MCInstrInfo const &MCII, MCInst const &MCI) { return (HexagonMCInstrInfo::getType(MCII, MCI) == HexagonII::TypePREFIX); } @@ -421,20 +367,6 @@ bool HexagonMCInstrInfo::prefersSlot3(MCInstrInfo const &MCII, return false; } -void HexagonMCInstrInfo::replaceDuplex(MCContext &Context, MCInst &MCB, - DuplexCandidate Candidate) { - assert(Candidate.packetIndexI < MCB.size()); - assert(Candidate.packetIndexJ < MCB.size()); - assert(isBundle(MCB)); - MCInst *Duplex = - deriveDuplex(Context, Candidate.iClass, - *MCB.getOperand(Candidate.packetIndexJ).getInst(), - *MCB.getOperand(Candidate.packetIndexI).getInst()); - assert(Duplex != nullptr); - MCB.getOperand(Candidate.packetIndexI).setInst(Duplex); - MCB.erase(MCB.begin() + Candidate.packetIndexJ); -} - void HexagonMCInstrInfo::setInnerLoop(MCInst &MCI) { assert(isBundle(MCI)); MCOperand &Operand = MCI.getOperand(0); diff --git a/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.h b/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.h index f09dfd8cf47..99970e2577c 100644 --- a/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.h +++ b/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.h @@ -15,14 +15,15 @@ #define LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCINSTRINFO_H #include "llvm/MC/MCInst.h" +#include "llvm/MC/MCInstrInfo.h" + +#include namespace llvm { -class MCContext; class MCInstrDesc; class MCInstrInfo; class MCInst; class MCOperand; -class MCSubtargetInfo; namespace HexagonII { enum class MemAccessSize; } @@ -47,16 +48,6 @@ size_t bundleSize(MCInst const &MCI); // Returns a iterator range of instructions in this bundle iterator_range bundleInstructions(MCInst const &MCI); -// Return the extender for instruction at Index or nullptr if none -MCInst const *extenderForIndex(MCInst const &MCB, size_t Index); - -// Create a duplex instruction given the two subinsts -MCInst *deriveDuplex(MCContext &Context, unsigned iClass, MCInst const &inst0, - MCInst const &inst1); - -// Convert this instruction in to a duplex subinst -MCInst deriveSubInst(MCInst const &Inst); - // Return memory access size HexagonII::MemAccessSize getAccessSize(MCInstrInfo const &MCII, MCInst const &MCI); @@ -69,13 +60,6 @@ unsigned short getCExtOpNum(MCInstrInfo const &MCII, MCInst const &MCI); MCInstrDesc const &getDesc(MCInstrInfo const &MCII, MCInst const &MCI); -// Return which duplex group this instruction belongs to -unsigned getDuplexCandidateGroup(MCInst const &MI); - -// Return a list of all possible instruction duplex combinations -SmallVector getDuplexPossibilties(MCInstrInfo const &MCII, - MCInst const &MCB); - // Return the index of the extendable operand unsigned short getExtendableOp(MCInstrInfo const &MCII, MCInst const &MCI); @@ -115,9 +99,6 @@ unsigned getType(MCInstrInfo const &MCII, MCInst const &MCI); unsigned getUnits(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst const &MCI); -// Does the packet have an extender for the instruction at Index -bool hasExtenderForIndex(MCInst const &MCB, size_t Index); - bool hasImmExt(MCInst const &MCI); // Return whether the instruction is a legal new-value producer. @@ -132,24 +113,9 @@ bool isBundle(MCInst const &MCI); // Return whether the insn is an actual insn. bool isCanon(MCInstrInfo const &MCII, MCInst const &MCI); -// Return the duplex iclass given the two duplex classes -unsigned iClassOfDuplexPair(unsigned Ga, unsigned Gb); - // Return whether the instruction needs to be constant extended. bool isConstExtended(MCInstrInfo const &MCII, MCInst const &MCI); -// Is this double register suitable for use in a duplex subinst -bool isDblRegForSubInst(unsigned Reg); - -// Is this a duplex instruction -bool isDuplex(MCInstrInfo const &MCII, MCInst const &MCI); - -// Can these instructions be duplexed -bool isDuplexPair(MCInst const &MIa, MCInst const &MIb); - -// Can these duplex classes be combine in to a duplex instruction -bool isDuplexPairMatch(unsigned Ga, unsigned Gb); - // Return true if the insn may be extended based on the operand value. bool isExtendable(MCInstrInfo const &MCII, MCInst const &MCI); @@ -165,12 +131,6 @@ bool isImmext(MCInst const &MCI); // Returns whether this bundle is an endloop0 bool isInnerLoop(MCInst const &MCI); -// Is this an integer register -bool isIntReg(unsigned Reg); - -// Is this register suitable for use in a duplex subinst -bool isIntRegForSubInst(unsigned Reg); - // Return whether the insn is a new-value consumer. bool isNewValue(MCInstrInfo const &MCII, MCInst const &MCI); @@ -178,11 +138,6 @@ bool isNewValue(MCInstrInfo const &MCII, MCInst const &MCI); bool isOperandExtended(MCInstrInfo const &MCII, MCInst const &MCI, unsigned short OperandNum); -// Can these two instructions be duplexed -bool isOrderedDuplexPair(MCInstrInfo const &MCII, MCInst const &MIa, - bool ExtendedA, MCInst const &MIb, bool ExtendedB, - bool bisReversable); - // Returns whether this bundle is an endloop1 bool isOuterLoop(MCInst const &MCI); @@ -192,9 +147,6 @@ bool isPredicated(MCInstrInfo const &MCII, MCInst const &MCI); // Return whether the predicate sense is true bool isPredicatedTrue(MCInstrInfo const &MCII, MCInst const &MCI); -// Is this a predicate register -bool isPredReg(unsigned Reg); - // Return whether the insn is a prefix. bool isPrefix(MCInstrInfo const &MCII, MCInst const &MCI); @@ -212,17 +164,11 @@ void padEndloop(MCInst &MCI); bool prefersSlot3(MCInstrInfo const &MCII, MCInst const &MCI); -// Replace the instructions inside MCB, represented by Candidate -void replaceDuplex(MCContext &Context, MCInst &MCB, DuplexCandidate Candidate); - // Marks a bundle as endloop0 void setInnerLoop(MCInst &MCI); // Marks a bundle as endloop1 void setOuterLoop(MCInst &MCI); - -// Would duplexing this instruction create a requirement to extend -bool subInstWouldBeExtended(MCInst const &potentialDuplex); } } diff --git a/lib/Target/Hexagon/MCTargetDesc/HexagonMCShuffler.cpp b/lib/Target/Hexagon/MCTargetDesc/HexagonMCShuffler.cpp index 8e70280c1a0..37cf3754870 100644 --- a/lib/Target/Hexagon/MCTargetDesc/HexagonMCShuffler.cpp +++ b/lib/Target/Hexagon/MCTargetDesc/HexagonMCShuffler.cpp @@ -147,61 +147,6 @@ bool llvm::HexagonMCShuffle(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, return true; } -unsigned -llvm::HexagonMCShuffle(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, - MCContext &Context, MCInst &MCB, - SmallVector possibleDuplexes) { - - if (DisableShuffle) - return HexagonShuffler::SHUFFLE_SUCCESS; - - if (!HexagonMCInstrInfo::bundleSize(MCB)) { - // There once was a bundle: - // BUNDLE %D2, %R4, %R5, %D7, ... - // * %D2 = IMPLICIT_DEF; flags: - // * %D7 = IMPLICIT_DEF; flags: - // After the IMPLICIT_DEFs were removed by the asm printer, the bundle - // became empty. - DEBUG(dbgs() << "Skipping empty bundle"); - return HexagonShuffler::SHUFFLE_SUCCESS; - } else if (!HexagonMCInstrInfo::isBundle(MCB)) { - DEBUG(dbgs() << "Skipping stand-alone insn"); - return HexagonShuffler::SHUFFLE_SUCCESS; - } - - bool doneShuffling = false; - unsigned shuffleError; - while (possibleDuplexes.size() > 0 && (!doneShuffling)) { - // case of Duplex Found - DuplexCandidate duplexToTry = possibleDuplexes.pop_back_val(); - MCInst Attempt(MCB); - HexagonMCInstrInfo::replaceDuplex(Context, Attempt, duplexToTry); - HexagonMCShuffler MCS(MCII, STI, Attempt); // copy packet to the shuffler - if (MCS.size() == 1) { // case of one duplex - // copy the created duplex in the shuffler to the bundle - MCS.copyTo(MCB); - doneShuffling = true; - return HexagonShuffler::SHUFFLE_SUCCESS; - } - // try shuffle with this duplex - doneShuffling = MCS.reshuffleTo(MCB); - shuffleError = MCS.getError(); - - if (doneShuffling) - break; - } - - if (doneShuffling == false) { - HexagonMCShuffler MCS(MCII, STI, MCB); - doneShuffling = MCS.reshuffleTo(MCB); // shuffle - shuffleError = MCS.getError(); - } - if (!doneShuffling) - return shuffleError; - - return HexagonShuffler::SHUFFLE_SUCCESS; -} - bool llvm::HexagonMCShuffle(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst &MCB, MCInst const *AddMI, int fixupCount) { if (!HexagonMCInstrInfo::isBundle(MCB) || !AddMI) diff --git a/test/CodeGen/Hexagon/args.ll b/test/CodeGen/Hexagon/args.ll index aea4ffe2eee..8af8baf3761 100644 --- a/test/CodeGen/Hexagon/args.ll +++ b/test/CodeGen/Hexagon/args.ll @@ -1,3 +1,4 @@ +; XFAIL: hexagon ; RUN: llc -march=hexagon -mcpu=hexagonv4 -disable-dfa-sched -disable-hexagon-misched < %s | FileCheck %s ; CHECK: memw(r29{{ *}}+{{ *}}#0){{ *}}={{ *}}#7 ; CHECK: r1:0 = combine(#2, #1) diff --git a/test/CodeGen/Hexagon/duplex.ll b/test/CodeGen/Hexagon/duplex.ll deleted file mode 100644 index 80fe61ceccc..00000000000 --- a/test/CodeGen/Hexagon/duplex.ll +++ /dev/null @@ -1,7 +0,0 @@ -; RUN: llc -march=hexagon -filetype=obj -o - %s | llvm-objdump -d - | FileCheck %s - -; CHECK: c0 3f 00 48 48003fc0 - -define i32 @foo() { -ret i32 0 -} \ No newline at end of file -- 2.34.1