From 4f3ccb634232c0c5a95549cad403252a2befb817 Mon Sep 17 00:00:00 2001 From: James Wylder Date: Fri, 19 Nov 2010 18:12:00 -0600 Subject: [PATCH] ARM: tegra: enable emc clock updates after lp0 Write a dummy value to EMC_MRW_0 to allow clock frequency changes after lp0. Change-Id: I2218967eaf9698eef6dcfe2e3edd89fbce2ebf1a Signed-off-by: James Wylder --- arch/arm/mach-tegra/suspend.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/mach-tegra/suspend.c b/arch/arm/mach-tegra/suspend.c index ead053e3acf4..af3252401256 100644 --- a/arch/arm/mach-tegra/suspend.c +++ b/arch/arm/mach-tegra/suspend.c @@ -127,6 +127,10 @@ static void __iomem *tmrus = IO_ADDRESS(TEGRA_TMRUS_BASE); #define FLOW_CTRL_CPU_CSR 0x8 #define FLOW_CTRL_CPU1_CSR 0x18 +#define EMC_MRW_0 0x0e8 +#define EMC_MRW_DEV_SELECTN 30 +#define EMC_MRW_DEV_NONE (3 << EMC_MRW_DEV_SELECTN) + unsigned long tegra_pgd_phys; /* pgd used by hotplug & LP2 bootup */ static pgd_t *tegra_pgd; void *tegra_context_area = NULL; @@ -568,6 +572,7 @@ static int tegra_suspend_enter(suspend_state_t state) { struct irq_desc *desc; void __iomem *mc = IO_ADDRESS(TEGRA_MC_BASE); + void __iomem *emc = IO_ADDRESS(TEGRA_EMC_BASE); unsigned long flags; u32 mc_data[3] = {0, 0, 0}; int irq; @@ -635,6 +640,9 @@ static int tegra_suspend_enter(suspend_state_t state) writel(mc_data[1], mc + MC_SECURITY_SIZE); writel(mc_data[2], mc + MC_SECURITY_CFG2); + /* trigger emc mode write */ + writel(EMC_MRW_DEV_NONE, emc + EMC_MRW_0); + tegra_clk_resume(); tegra_gpio_resume(); tegra_timer_resume(); -- 2.34.1