From 4f487054f732d381f41475ccea227dedc1d5d3db Mon Sep 17 00:00:00 2001
From: Elaine Zhang <zhangqing@rock-chips.com>
Date: Mon, 14 Mar 2016 15:33:19 +0800
Subject: [PATCH] ARM64: dts: rockchip: add power domain node for RK3399 Soc

add pd node for RK3399 Soc
create power domain tree

Change-Id: I5a455034f56b6d88860c3ed2decd8c6dc94896a3
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
---
 arch/arm64/boot/dts/rockchip/rk3399.dtsi | 64 ++++++++++++++++++++++++
 1 file changed, 64 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index abc27d799b2e..15455af384c1 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -39,11 +39,13 @@
  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  *     OTHER DEALINGS IN THE SOFTWARE.
  */
+
 #include <dt-bindings/clock/rk3399-cru.h>
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/power/rk3399-power.h>
 #include <dt-bindings/thermal/thermal.h>
 
 / {
@@ -575,6 +577,68 @@
 		status = "disabled";
 	};
 
+	pmu: power-management@ff731000 {
+		compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
+		reg = <0x0 0xff310000 0x0 0x1000>;
+
+		power: power-controller {
+			status = "disabled";
+			compatible = "rockchip,rk3399-power-controller";
+			#power-domain-cells = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			pd_center {
+				reg = <RK3399_PD_CENTER>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				pd_vdu {
+					reg = <RK3399_PD_VDU>;
+				};
+				pd_vcodec {
+					reg = <RK3399_PD_VCODEC>;
+				};
+				pd_iep {
+					reg = <RK3399_PD_IEP>;
+				};
+				pd_rga {
+					reg = <RK3399_PD_RGA>;
+				};
+			};
+			pd_vio {
+				reg = <RK3399_PD_VIO>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				pd_isp0 {
+					reg = <RK3399_PD_ISP0>;
+				};
+				pd_isp1 {
+					reg = <RK3399_PD_ISP1>;
+				};
+				pd_hdcp {
+					reg = <RK3399_PD_HDCP>;
+				};
+				pd_vo {
+					reg = <RK3399_PD_VO>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					pd_vopb {
+						reg = <RK3399_PD_VOPB>;
+					};
+					pd_vopl {
+						reg = <RK3399_PD_VOPL>;
+					};
+				};
+			};
+			pd_gpu {
+				reg = <RK3399_PD_GPU>;
+			};
+		};
+	};
+
 	pmucru: pmu-clock-controller@ff750000 {
 		compatible = "rockchip,rk3399-pmucru";
 		reg = <0x0 0xff750000 0x0 0x1000>;
-- 
2.34.1