From 515638e7d9a3d1b72d60934b2b7c679f21eb6db2 Mon Sep 17 00:00:00 2001 From: chenxing Date: Mon, 27 Aug 2012 14:08:51 +0800 Subject: [PATCH] rk2928:sdk: fix pll_mode POWER ON/DN ERROR --- arch/arm/mach-rk2928/clock_data.c | 5 +++-- arch/arm/mach-rk2928/include/mach/cru.h | 4 ++-- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/arch/arm/mach-rk2928/clock_data.c b/arch/arm/mach-rk2928/clock_data.c index 5fea3a07123a..3f7263951a07 100644 --- a/arch/arm/mach-rk2928/clock_data.c +++ b/arch/arm/mach-rk2928/clock_data.c @@ -545,6 +545,7 @@ static void pll_wait_lock(int pll_idx) while(1); } } + static int pll_clk_mode(struct clk *clk, int on) { u8 pll_id = clk->pll->id; @@ -554,13 +555,13 @@ static int pll_clk_mode(struct clk *clk, int on) CLKDATA_DBG("pll_mode %s(%d)\n", clk->name, on); //FIXME if (on) { - cru_writel(CRU_W_MSK_SETBIT(PLL_PWR_ON, PLL_LOCK_SHIFT), PLL_CONS(pll_id, 1)); + cru_writel(CRU_W_MSK_SETBIT(PLL_PWR_ON, PLL_BYPASS_SHIFT), PLL_CONS(pll_id, 0)); rk_clock_udelay(dly); pll_wait_lock(pll_id); cru_writel(PLL_MODE_NORM(pll_id), CRU_MODE_CON); } else { cru_writel(PLL_MODE_SLOW(pll_id), CRU_MODE_CON); - cru_writel(CRU_W_MSK_SETBIT(PLL_PWR_DN, PLL_LOCK_SHIFT), PLL_CONS(pll_id, 1)); + cru_writel(CRU_W_MSK_SETBIT(PLL_PWR_DN, PLL_BYPASS_SHIFT), PLL_CONS(pll_id, 0)); } return 0; } diff --git a/arch/arm/mach-rk2928/include/mach/cru.h b/arch/arm/mach-rk2928/include/mach/cru.h index 4d5025cc325f..906537534607 100755 --- a/arch/arm/mach-rk2928/include/mach/cru.h +++ b/arch/arm/mach-rk2928/include/mach/cru.h @@ -33,8 +33,8 @@ enum rk_plls_id { #define CRU_GLB_CNT_TH (0x140) /*PLL_CON 0,1,2*/ -#define PLL_PWR_ON (1) -#define PLL_PWR_DN (0) +#define PLL_PWR_ON (0) +#define PLL_PWR_DN (1) #define PLL_BYPASS (1 << 15) #define PLL_NO_BYPASS (0 << 15) //con0 -- 2.34.1