From 51a263434a8ba6305ded4bff46204058eb679c8e Mon Sep 17 00:00:00 2001 From: Chris Lattner Date: Tue, 11 Jan 2005 06:36:20 +0000 Subject: [PATCH] Instead of generating stuff like this: mov %ECX, %EAX add %ECX, 32768 mov %SI, WORD PTR [2*%ECX + l13_prev] Generate this: mov %SI, WORD PTR [2*%ECX + l13_prev + 65536] This occurs when you have a GEP instruction where an index is "something + imm". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19472 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/X86/X86ISelPattern.cpp | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/lib/Target/X86/X86ISelPattern.cpp b/lib/Target/X86/X86ISelPattern.cpp index 8073342895a..40e4c414ff9 100644 --- a/lib/Target/X86/X86ISelPattern.cpp +++ b/lib/Target/X86/X86ISelPattern.cpp @@ -429,7 +429,20 @@ bool ISel::SelectAddress(SDOperand N, X86AddressMode &AM) { unsigned Val = CN->getValue(); if (Val == 1 || Val == 2 || Val == 3) { AM.Scale = 1 << Val; - AM.IndexReg = SelectExpr(N.Val->getOperand(0)); + SDOperand ShVal = N.Val->getOperand(0); + + // Okay, we know that we have a scale by now. However, if the scaled + // value is an add of something and a constant, we can fold the + // constant into the disp field here. + if (ShVal.Val->getOpcode() == ISD::ADD && + isa(ShVal.Val->getOperand(1))) { + AM.IndexReg = SelectExpr(ShVal.Val->getOperand(0)); + ConstantSDNode *AddVal = + cast(ShVal.Val->getOperand(1)); + AM.Disp += AddVal->getValue() << Val; + } else { + AM.IndexReg = SelectExpr(ShVal); + } return false; } } -- 2.34.1