From 52578b085037248e3875089f9dcb2f95a5d9fb5d Mon Sep 17 00:00:00 2001
From: Asiri Rathnayake <asiri.rathnayake@arm.com>
Date: Mon, 19 Oct 2015 11:44:24 +0000
Subject: [PATCH] Fix mapping of @llvm.arm.ssat/usat intrinsics to ssat/usat
 instructions

The mapping of these two intrinsics in ARMInstrInfo.td had a small
omission which lead to their operands not being validated/transformed
before being lowered into usat and ssat instructions. This can cause
incorrect instructions to be emitted.

I've also added tests for the remaining two saturating arithmatic
intrinsics @llvm.arm.qadd and @llvm.arm.qsub as they are missing
codegen tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250697 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Target/ARM/ARMInstrInfo.td |  8 ++---
 test/CodeGen/ARM/sat-arith.ll  | 60 ++++++++++++++++++++++++++++++++++
 test/CodeGen/ARM/ssat-lower.ll | 10 ++++++
 test/CodeGen/ARM/ssat-upper.ll | 10 ++++++
 test/CodeGen/ARM/usat-lower.ll | 10 ++++++
 test/CodeGen/ARM/usat-upper.ll | 10 ++++++
 6 files changed, 104 insertions(+), 4 deletions(-)
 create mode 100644 test/CodeGen/ARM/sat-arith.ll
 create mode 100644 test/CodeGen/ARM/ssat-lower.ll
 create mode 100644 test/CodeGen/ARM/ssat-upper.ll
 create mode 100644 test/CodeGen/ARM/usat-lower.ll
 create mode 100644 test/CodeGen/ARM/usat-upper.ll

diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td
index 93ade1343d9..9506e1ebef7 100644
--- a/lib/Target/ARM/ARMInstrInfo.td
+++ b/lib/Target/ARM/ARMInstrInfo.td
@@ -3678,10 +3678,10 @@ def USAT16 : AI<(outs GPRnopc:$Rd),
   let Inst{3-0} = Rn;
 }
 
-def : ARMV6Pat<(int_arm_ssat GPRnopc:$a, imm:$pos),
-               (SSAT imm:$pos, GPRnopc:$a, 0)>;
-def : ARMV6Pat<(int_arm_usat GPRnopc:$a, imm:$pos),
-               (USAT imm:$pos, GPRnopc:$a, 0)>;
+def : ARMV6Pat<(int_arm_ssat GPRnopc:$a, imm1_32:$pos),
+               (SSAT imm1_32:$pos, GPRnopc:$a, 0)>;
+def : ARMV6Pat<(int_arm_usat GPRnopc:$a, imm0_31:$pos),
+               (USAT imm0_31:$pos, GPRnopc:$a, 0)>;
 
 //===----------------------------------------------------------------------===//
 //  Bitwise Instructions.
diff --git a/test/CodeGen/ARM/sat-arith.ll b/test/CodeGen/ARM/sat-arith.ll
new file mode 100644
index 00000000000..c1ad1a5858e
--- /dev/null
+++ b/test/CodeGen/ARM/sat-arith.ll
@@ -0,0 +1,60 @@
+; RUN: llc -O1 -mtriple=armv6-none-none-eabi %s -o - | FileCheck %s
+
+; CHECK-LABEL: qadd
+define i32 @qadd() nounwind {
+; CHECK: mov [[R0:.*]], #8
+; CHECK: mov [[R1:.*]], #128
+; CHECK: qadd [[R0]], [[R1]], [[R0]]
+  %tmp = call i32 @llvm.arm.qadd(i32 128, i32 8)
+  ret i32 %tmp
+}
+
+; CHECK-LABEL: qsub
+define i32 @qsub() nounwind {
+; CHECK: mov [[R0:.*]], #8
+; CHECK: mov [[R1:.*]], #128
+; CHECK: qsub [[R0]], [[R1]], [[R0]]
+  %tmp = call i32 @llvm.arm.qsub(i32 128, i32 8)
+  ret i32 %tmp
+}
+
+; upper-bound of the immediate argument
+; CHECK-LABEL: ssat1
+define i32 @ssat1() nounwind {
+; CHECK: mov [[R0:.*]], #128
+; CHECK: ssat [[R1:.*]], #32, [[R0]]
+  %tmp = call i32 @llvm.arm.ssat(i32 128, i32 32)
+  ret i32 %tmp
+}
+
+; lower-bound of the immediate argument
+; CHECK-LABEL: ssat2
+define i32 @ssat2() nounwind {
+; CHECK: mov [[R0:.*]], #128
+; CHECK: ssat [[R1:.*]], #1, [[R0]]
+  %tmp = call i32 @llvm.arm.ssat(i32 128, i32 1)
+  ret i32 %tmp
+}
+
+; upper-bound of the immediate argument
+; CHECK-LABEL: usat1
+define i32 @usat1() nounwind {
+; CHECK: mov [[R0:.*]], #128
+; CHECK: usat [[R1:.*]], #31, [[R0]]
+  %tmp = call i32 @llvm.arm.usat(i32 128, i32 31)
+  ret i32 %tmp
+}
+
+; lower-bound of the immediate argument
+; CHECK-LABEL: usat2
+define i32 @usat2() nounwind {
+; CHECK: mov [[R0:.*]], #128
+; CHECK: usat [[R1:.*]], #0, [[R0]]
+  %tmp = call i32 @llvm.arm.usat(i32 128, i32 0)
+  ret i32 %tmp
+}
+
+declare i32 @llvm.arm.qadd(i32, i32) nounwind
+declare i32 @llvm.arm.qsub(i32, i32) nounwind
+declare i32 @llvm.arm.ssat(i32, i32) nounwind readnone
+declare i32 @llvm.arm.usat(i32, i32) nounwind readnone
diff --git a/test/CodeGen/ARM/ssat-lower.ll b/test/CodeGen/ARM/ssat-lower.ll
new file mode 100644
index 00000000000..a2cdfd87faa
--- /dev/null
+++ b/test/CodeGen/ARM/ssat-lower.ll
@@ -0,0 +1,10 @@
+; RUN: not llc < %s -O1 -mtriple=armv6-none-none-eabi 2>&1 | FileCheck %s
+
+; immediate argument < lower-bound
+; CHECK: LLVM ERROR: Cannot select: intrinsic %llvm.arm.ssat
+define i32 @ssat1() nounwind {
+  %tmp = call i32 @llvm.arm.ssat(i32 128, i32 0)
+  ret i32 %tmp
+}
+
+declare i32 @llvm.arm.ssat(i32, i32) nounwind readnone
diff --git a/test/CodeGen/ARM/ssat-upper.ll b/test/CodeGen/ARM/ssat-upper.ll
new file mode 100644
index 00000000000..bc4712b1994
--- /dev/null
+++ b/test/CodeGen/ARM/ssat-upper.ll
@@ -0,0 +1,10 @@
+; RUN: not llc < %s -O1 -mtriple=armv6-none-none-eabi 2>&1 | FileCheck %s
+
+; immediate argument > upper-bound
+; CHECK: LLVM ERROR: Cannot select: intrinsic %llvm.arm.ssat
+define i32 @ssat1() nounwind {
+  %tmp = call i32 @llvm.arm.ssat(i32 128, i32 33)
+  ret i32 %tmp
+}
+
+declare i32 @llvm.arm.ssat(i32, i32) nounwind readnone
diff --git a/test/CodeGen/ARM/usat-lower.ll b/test/CodeGen/ARM/usat-lower.ll
new file mode 100644
index 00000000000..c19cc9c39c4
--- /dev/null
+++ b/test/CodeGen/ARM/usat-lower.ll
@@ -0,0 +1,10 @@
+; RUN: not llc < %s -O1 -mtriple=armv6-none-none-eabi 2>&1 | FileCheck %s
+
+; immediate argument < lower-bound
+; CHECK: LLVM ERROR: Cannot select: intrinsic %llvm.arm.usat
+define i32 @usat1() nounwind {
+  %tmp = call i32 @llvm.arm.usat(i32 128, i32 -1)
+  ret i32 %tmp
+}
+
+declare i32 @llvm.arm.usat(i32, i32) nounwind readnone
diff --git a/test/CodeGen/ARM/usat-upper.ll b/test/CodeGen/ARM/usat-upper.ll
new file mode 100644
index 00000000000..d6e4a6fd534
--- /dev/null
+++ b/test/CodeGen/ARM/usat-upper.ll
@@ -0,0 +1,10 @@
+; RUN: not llc < %s -O1 -mtriple=armv6-none-none-eabi 2>&1 | FileCheck %s
+
+; immediate argument > upper-bound
+; CHECK: LLVM ERROR: Cannot select: intrinsic %llvm.arm.usat
+define i32 @usat1() nounwind {
+  %tmp = call i32 @llvm.arm.usat(i32 128, i32 32)
+  ret i32 %tmp
+}
+
+declare i32 @llvm.arm.usat(i32, i32) nounwind readnone
-- 
2.34.1