From 54a7f7f9e0b81327c5de1985d4eefbe7b32142af Mon Sep 17 00:00:00 2001 From: Tim Northover Date: Sun, 27 Jul 2014 07:10:29 +0000 Subject: [PATCH] AArch64: fix conversion of 'J' inline asm constraints. 'J' represents a negative number suitable for an add/sub alias instruction, but while preparing it to become an int64_t we were mangling the sign extension. So "i32 -1" became 0xffffffffLL, for example. Should fix one half of PR20456. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214052 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/AArch64/AArch64ISelLowering.cpp | 4 +++- test/CodeGen/AArch64/arm64-inline-asm.ll | 10 +++++++--- 2 files changed, 10 insertions(+), 4 deletions(-) diff --git a/lib/Target/AArch64/AArch64ISelLowering.cpp b/lib/Target/AArch64/AArch64ISelLowering.cpp index 7776206aafa..994013f79be 100644 --- a/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -4013,8 +4013,10 @@ void AArch64TargetLowering::LowerAsmOperandForConstraint( return; case 'J': { uint64_t NVal = -C->getSExtValue(); - if (isUInt<12>(NVal) || isShiftedUInt<12, 12>(NVal)) + if (isUInt<12>(NVal) || isShiftedUInt<12, 12>(NVal)) { + CVal = C->getSExtValue(); break; + } return; } // The K and L constraints apply *only* to logical immediates, including diff --git a/test/CodeGen/AArch64/arm64-inline-asm.ll b/test/CodeGen/AArch64/arm64-inline-asm.ll index d76cca3f21c..9c8bcaadc17 100644 --- a/test/CodeGen/AArch64/arm64-inline-asm.ll +++ b/test/CodeGen/AArch64/arm64-inline-asm.ll @@ -87,13 +87,17 @@ entry: ret i32 %1 } -define i32 @constraint_J(i32 %i, i32 %j) nounwind { +define i32 @constraint_J(i32 %i, i32 %j, i64 %k) nounwind { entry: ; CHECK-LABEL: constraint_J: %0 = tail call i32 asm sideeffect "sub ${0:w}, ${1:w}, $2", "=r,r,J"(i32 %i, i32 -16773120) nounwind - ; CHECK: sub {{w[0-9]+}}, {{w[0-9]+}}, #4278194176 + ; CHECK: sub {{w[0-9]+}}, {{w[0-9]+}}, #-16773120 %1 = tail call i32 asm sideeffect "sub ${0:w}, ${1:w}, $2", "=r,r,J"(i32 %i, i32 -1) nounwind - ; CHECK: sub {{w[0-9]+}}, {{w[0-9]+}}, #4294967295 + ; CHECK: sub {{w[0-9]+}}, {{w[0-9]+}}, #-1 + %2 = tail call i64 asm sideeffect "sub ${0:x}, ${1:x}, $2", "=r,r,J"(i64 %k, i32 -1) nounwind + ; CHECK: sub {{x[0-9]+}}, {{x[0-9]+}}, #-1 + %3 = tail call i64 asm sideeffect "sub ${0:x}, ${1:x}, $2", "=r,r,J"(i64 %k, i64 -1) nounwind + ; CHECK: sub {{x[0-9]+}}, {{x[0-9]+}}, #-1 ret i32 %1 } -- 2.34.1