From 557c3631d320c5731e55b6f818a1c7b2d4d97176 Mon Sep 17 00:00:00 2001 From: Christopher Lamb Date: Thu, 26 Jul 2007 07:34:40 +0000 Subject: [PATCH] Add selection DAG nodes for subreg insert/extract. PR1350 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40516 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/SelectionDAGNodes.h | 9 +++++++++ lib/CodeGen/SelectionDAG/LegalizeDAG.cpp | 18 +++++++++++++++++- lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 5 ++++- lib/Target/TargetSelectionDAG.td | 5 +++++ 4 files changed, 35 insertions(+), 2 deletions(-) diff --git a/include/llvm/CodeGen/SelectionDAGNodes.h b/include/llvm/CodeGen/SelectionDAGNodes.h index c96d516eca1..a74c04836f9 100644 --- a/include/llvm/CodeGen/SelectionDAGNodes.h +++ b/include/llvm/CodeGen/SelectionDAGNodes.h @@ -289,6 +289,15 @@ namespace ISD { /// elements of the vector are undefined. SCALAR_TO_VECTOR, + // EXTRACT_SUBREG - This node is used to extract a sub-register value. + // This node takes a superreg and a constant sub-register index as operands. + EXTRACT_SUBREG, + + // INSERT_SUBREG - This node is used to insert a sub-register value. + // This node takes a superreg, a subreg value, and a constant sub-register + // index as operands. + INSERT_SUBREG, + // MULHU/MULHS - Multiply high - Multiply two integers of type iN, producing // an unsigned/signed value of type i[2*n], then return the top part. MULHU, MULHS, diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp index 25f032041d9..4131ed9ecf7 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp +++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp @@ -957,7 +957,23 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { AddLegalizedOperand(SDOperand(Node, i), Tmp1); } return Tmp2; - + case ISD::EXTRACT_SUBREG: { + Tmp1 = LegalizeOp(Node->getOperand(0)); + ConstantSDNode *idx = dyn_cast(Node->getOperand(1)); + assert(idx && "Operand must be a constant"); + Tmp2 = DAG.getTargetConstant(idx->getValue(), idx->getValueType(0)); + Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); + } + break; + case ISD::INSERT_SUBREG: { + Tmp1 = LegalizeOp(Node->getOperand(0)); + Tmp2 = LegalizeOp(Node->getOperand(1)); + ConstantSDNode *idx = dyn_cast(Node->getOperand(2)); + assert(idx && "Operand must be a constant"); + Tmp3 = DAG.getTargetConstant(idx->getValue(), idx->getValueType(0)); + Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); + } + break; case ISD::BUILD_VECTOR: switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) { default: assert(0 && "This action is not supported yet!"); diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp index 9b146eef629..d4d984b13f5 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp @@ -3455,7 +3455,10 @@ std::string SDNode::getOperationName(const SelectionDAG *G) const { case ISD::SHL_PARTS: return "shl_parts"; case ISD::SRA_PARTS: return "sra_parts"; case ISD::SRL_PARTS: return "srl_parts"; - + + case ISD::EXTRACT_SUBREG: return "extract_subreg"; + case ISD::INSERT_SUBREG: return "insert_subreg"; + // Conversion operators. case ISD::SIGN_EXTEND: return "sign_extend"; case ISD::ZERO_EXTEND: return "zero_extend"; diff --git a/lib/Target/TargetSelectionDAG.td b/lib/Target/TargetSelectionDAG.td index 491bb023fed..4b6d881f2c8 100644 --- a/lib/Target/TargetSelectionDAG.td +++ b/lib/Target/TargetSelectionDAG.td @@ -317,6 +317,11 @@ def vector_extract : SDNode<"ISD::EXTRACT_VECTOR_ELT", SDTypeProfile<1, 2, [SDTCisPtrTy<2>]>, []>; def vector_insert : SDNode<"ISD::INSERT_VECTOR_ELT", SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisPtrTy<3>]>, []>; + +def extract_subreg : SDNode<"ISD::EXTRACT_SUBREG", + SDTypeProfile<1, 2, []>>; +def insert_subreg : SDNode<"ISD::INSERT_SUBREG", + SDTypeProfile<1, 3, []>>; // Nodes for intrinsics, you should use the intrinsic itself and let tblgen use // these internally. Don't reference these directly. -- 2.34.1