From 5624f0b8366db96821aa9d4b99f7259f47a9ed10 Mon Sep 17 00:00:00 2001 From: "Huang, Tao" Date: Wed, 10 Dec 2014 19:23:04 +0800 Subject: [PATCH] rockchip: clk: covert dsb() to dsb(sy) --- drivers/clk/rockchip/clk-pll.c | 24 ++++++++++++------------ drivers/clk/rockchip/clk.c | 2 +- include/linux/rockchip/cru.h | 2 +- 3 files changed, 14 insertions(+), 14 deletions(-) diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c index 44ac6e82de41..760b54aca975 100755 --- a/drivers/clk/rockchip/clk-pll.c +++ b/drivers/clk/rockchip/clk-pll.c @@ -487,12 +487,12 @@ static int _pll_clk_set_rate_3188(struct pll_clk_set *clk_set, cru_writel(_RK3188_PLL_MODE_SLOW_SET(pll->mode_shift), pll->mode_offset); //pll power down cru_writel((0x1 << (16+1)) | (0x1<<1), pll->reg + RK3188_PLL_CON(3)); - dsb(); - dsb(); - dsb(); - dsb(); - dsb(); - dsb(); + dsb(sy); + dsb(sy); + dsb(sy); + dsb(sy); + dsb(sy); + dsb(sy); cru_writel(clk_set->pllcon0, pll->reg + RK3188_PLL_CON(0)); cru_writel(clk_set->pllcon1, pll->reg + RK3188_PLL_CON(1)); @@ -697,12 +697,12 @@ CHANGE_APLL: /* PLL power down */ cru_writel((0x1 << (16+1)) | (0x1<<1), pll->reg + RK3188_PLL_CON(3)); - dsb(); - dsb(); - dsb(); - dsb(); - dsb(); - dsb(); + dsb(sy); + dsb(sy); + dsb(sy); + dsb(sy); + dsb(sy); + dsb(sy); cru_writel(ps->pllcon0, pll->reg + RK3188_PLL_CON(0)); cru_writel(ps->pllcon1, pll->reg + RK3188_PLL_CON(1)); diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c index 97e1888e413b..6678dfc06e3c 100755 --- a/drivers/clk/rockchip/clk.c +++ b/drivers/clk/rockchip/clk.c @@ -36,7 +36,7 @@ u32 cru_readl(u32 offset) void cru_writel(u32 val, u32 offset) { writel(val, rk_cru_base + (offset)); - dsb(); + dsb(sy); } u32 grf_readl(u32 offset) diff --git a/include/linux/rockchip/cru.h b/include/linux/rockchip/cru.h index c3e2e63fd64a..d4cbb4b2f056 100755 --- a/include/linux/rockchip/cru.h +++ b/include/linux/rockchip/cru.h @@ -121,7 +121,7 @@ static inline void rk3288_cru_set_soft_reset(u32 idx, bool on) void __iomem *reg = RK_CRU_VIRT + RK3288_CRU_SOFTRSTS_CON(idx >> 4); u32 val = on ? 0x10001U << (idx & 0xf) : 0x10000U << (idx & 0xf); writel_relaxed(val, reg); - dsb(); + dsb(sy); } #define RK3036_CRU_MODE_CON 0x0040 -- 2.34.1