From 5684c4e2b41f1d6ddf70b116a84f438040f66297 Mon Sep 17 00:00:00 2001 From: "Vikram S. Adve" Date: Thu, 18 Oct 2001 00:02:06 +0000 Subject: [PATCH] Added virtual function to generate an instruction sequence to load a constant into a register. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@862 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/Target/MachineInstrInfo.h | 20 ++++++++++++++++++++ include/llvm/Target/TargetInstrInfo.h | 20 ++++++++++++++++++++ lib/Target/SparcV9/SparcV9Internals.h | 17 +++++++++++++---- 3 files changed, 53 insertions(+), 4 deletions(-) diff --git a/include/llvm/Target/MachineInstrInfo.h b/include/llvm/Target/MachineInstrInfo.h index 5106a260d99..d0294caf468 100644 --- a/include/llvm/Target/MachineInstrInfo.h +++ b/include/llvm/Target/MachineInstrInfo.h @@ -9,8 +9,13 @@ #include "llvm/Target/TargetMachine.h" #include "llvm/Support/DataTypes.h" +#include class MachineInstrDescriptor; +class TmpInstruction; +class MachineInstr; +class Value; +class Instruction; typedef int InstrSchedClass; @@ -211,6 +216,21 @@ public: isSignExtended = getDescriptor(opCode).immedIsSignExtended; return getDescriptor(opCode).maxImmedConst; } + + //------------------------------------------------------------------------- + // Code generation support for creating individual machine instructions + //------------------------------------------------------------------------- + + // Create an instruction sequence to put the constant `val' into + // the virtual register `dest'. `val' may be a ConstPoolVal or a + // GlobalValue, viz., the constant address of a global variable or function. + // The generated instructions are returned in `minstrVec'. + // Any temp. registers (TmpInstruction) created are returned in `tempVec'. + // + virtual void CreateCodeToLoadConst(Value* val, + Instruction* dest, + vector& minstrVec, + vector& temps) const =0; }; #endif diff --git a/include/llvm/Target/TargetInstrInfo.h b/include/llvm/Target/TargetInstrInfo.h index 5106a260d99..d0294caf468 100644 --- a/include/llvm/Target/TargetInstrInfo.h +++ b/include/llvm/Target/TargetInstrInfo.h @@ -9,8 +9,13 @@ #include "llvm/Target/TargetMachine.h" #include "llvm/Support/DataTypes.h" +#include class MachineInstrDescriptor; +class TmpInstruction; +class MachineInstr; +class Value; +class Instruction; typedef int InstrSchedClass; @@ -211,6 +216,21 @@ public: isSignExtended = getDescriptor(opCode).immedIsSignExtended; return getDescriptor(opCode).maxImmedConst; } + + //------------------------------------------------------------------------- + // Code generation support for creating individual machine instructions + //------------------------------------------------------------------------- + + // Create an instruction sequence to put the constant `val' into + // the virtual register `dest'. `val' may be a ConstPoolVal or a + // GlobalValue, viz., the constant address of a global variable or function. + // The generated instructions are returned in `minstrVec'. + // Any temp. registers (TmpInstruction) created are returned in `tempVec'. + // + virtual void CreateCodeToLoadConst(Value* val, + Instruction* dest, + vector& minstrVec, + vector& temps) const =0; }; #endif diff --git a/lib/Target/SparcV9/SparcV9Internals.h b/lib/Target/SparcV9/SparcV9Internals.h index 0d8d6729812..6828a68e667 100644 --- a/lib/Target/SparcV9/SparcV9Internals.h +++ b/lib/Target/SparcV9/SparcV9Internals.h @@ -85,7 +85,7 @@ class UltraSparcInstrInfo : public MachineInstrInfo { public: /*ctor*/ UltraSparcInstrInfo(); - virtual bool hasResultInterlock (MachineOpCode opCode) + virtual bool hasResultInterlock (MachineOpCode opCode) const { // All UltraSPARC instructions have interlocks (note that delay slots // are not considered here). @@ -96,10 +96,19 @@ public: return (opCode == FCMPS || opCode == FCMPD || opCode == FCMPQ); } - - - + //------------------------------------------------------------------------- + // Code generation support for creating individual machine instructions + //------------------------------------------------------------------------- + // Create an instruction sequence to put the constant `val' into + // the virtual register `dest'. The generated instructions are + // returned in `minstrVec'. Any temporary registers (TmpInstruction) + // created are returned in `tempVec'. + // + virtual void CreateCodeToLoadConst(Value* val, + Instruction* dest, + vector& minstrVec, + vector& tempVec) const; }; -- 2.34.1