From 572c46535894f9b7d54ff717865ba3fa63fe6355 Mon Sep 17 00:00:00 2001 From: Zheng Yang Date: Wed, 21 Jun 2017 15:18:04 +0800 Subject: [PATCH] drm: rockchip: hdmi: check sink max_tmds_clock in mode_valid If sink max TMDS clock < 340MHz, we think the mode pixel clock greater than 340MHz should support YCbCr420, or it is a bad mode. Change-Id: I9f53fa4f9875977ae0355b65d9ccd8a304558c5d Signed-off-by: Zheng Yang --- drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c index 104f8771bd31..fafdd94fd2ba 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c @@ -888,6 +888,14 @@ dw_hdmi_rockchip_mode_valid(struct drm_connector *connector, */ if (mode->clock > INT_MAX / 1000) return MODE_BAD; + /* + * If sink max TMDS clock < 340MHz, we should check the mode pixel + * clock > 340MHz is YCbCr420 or not. + */ + if (mode->clock > 340000 && + connector->display_info.max_tmds_clock < 340000 && + !(mode->flags & DRM_MODE_FLAG_420_MASK)) + return MODE_BAD; if (!encoder) { const struct drm_connector_helper_funcs *funcs; -- 2.34.1