From 57ebe9fbf067422a267b5d46b0b0282e437c15c3 Mon Sep 17 00:00:00 2001
From: Evan Cheng <evan.cheng@apple.com>
Date: Sat, 15 Apr 2006 05:37:34 +0000
Subject: [PATCH] Silly bug

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27719 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Target/X86/README.txt          |  5 -----
 lib/Target/X86/X86ISelLowering.cpp | 22 ++++++++++------------
 lib/Target/X86/X86InstrSSE.td      |  2 +-
 3 files changed, 11 insertions(+), 18 deletions(-)

diff --git a/lib/Target/X86/README.txt b/lib/Target/X86/README.txt
index de768b08132..f58991728ea 100644
--- a/lib/Target/X86/README.txt
+++ b/lib/Target/X86/README.txt
@@ -810,8 +810,3 @@ destination?
 How about andps, andpd, and pand? Do we really care about the type of the packed
 elements? If not, why not always use the "ps" variants which are likely to be
 shorter.
-
-//===---------------------------------------------------------------------===//
-
-Make sure XMM registers are spilled to 128-bit locations (if not already) and
-add vector SSE opcodes to X86RegisterInfo::foldMemoryOperand().
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index 409c39be5d2..38e4614299a 100644
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -1724,27 +1724,26 @@ bool X86::isMOVSHDUPMask(SDNode *N) {
     return false;
 
   // Expect 1, 1, 3, 3
-  unsigned NumNodes = 0;
   for (unsigned i = 0; i < 2; ++i) {
     SDOperand Arg = N->getOperand(i);
     if (Arg.getOpcode() == ISD::UNDEF) continue;
     assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
     unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
     if (Val != 1) return false;
-    NumNodes++;
   }
+
+  bool HasHi = false;
   for (unsigned i = 2; i < 4; ++i) {
     SDOperand Arg = N->getOperand(i);
     if (Arg.getOpcode() == ISD::UNDEF) continue;
     assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
     unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
     if (Val != 3) return false;
-    NumNodes++;
+    HasHi = true;
   }
 
-  // Don't use movshdup if the resulting vector contains only one undef node.
-  // Use {p}shuf* instead.
-  return NumNodes > 1;
+  // Don't use movshdup if it can be done with a shufps.
+  return HasHi;
 }
 
 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
@@ -1756,27 +1755,26 @@ bool X86::isMOVSLDUPMask(SDNode *N) {
     return false;
 
   // Expect 0, 0, 2, 2
-  unsigned NumNodes = 0;
   for (unsigned i = 0; i < 2; ++i) {
     SDOperand Arg = N->getOperand(i);
     if (Arg.getOpcode() == ISD::UNDEF) continue;
     assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
     unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
     if (Val != 0) return false;
-    NumNodes++;
   }
+
+  bool HasHi = false;
   for (unsigned i = 2; i < 4; ++i) {
     SDOperand Arg = N->getOperand(i);
     if (Arg.getOpcode() == ISD::UNDEF) continue;
     assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
     unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
     if (Val != 2) return false;
-    NumNodes++;
+    HasHi = true;
   }
 
-  // Don't use movsldup if the resulting vector contains only one undef node.
-  // Use {p}shuf* instead.
-  return NumNodes > 1;
+  // Don't use movshdup if it can be done with a shufps.
+  return HasHi;
 }
 
 /// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand specifies
diff --git a/lib/Target/X86/X86InstrSSE.td b/lib/Target/X86/X86InstrSSE.td
index 430dfd9f865..c4e80fcf4f7 100644
--- a/lib/Target/X86/X86InstrSSE.td
+++ b/lib/Target/X86/X86InstrSSE.td
@@ -169,7 +169,7 @@ def PSHUFD_binary_shuffle_mask : PatLeaf<(build_vector), [{
 // PDIi8 - SSE2 instructions with ImmT == Imm8 and TB and OpSize prefixes.
 // S3I - SSE3 instructions with TB and OpSize prefixes.
 // S3SI - SSE3 instructions with XS prefix.
-// S3SI - SSE3 instructions with XD prefix.
+// S3DI - SSE3 instructions with XD prefix.
 class SSI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
       : I<o, F, ops, asm, pattern>, XS, Requires<[HasSSE1]>;
 class SDI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
-- 
2.34.1