From 58c3a833a115aae236e56e9b1c498ef39b940671 Mon Sep 17 00:00:00 2001 From: luowei Date: Mon, 17 Mar 2014 19:35:11 +0800 Subject: [PATCH] pinctrl:add vol_domain and iomux operation for RK3288 --- arch/arm/boot/dts/rk3288-pinctrl.dtsi | 219 ++++++++++--- drivers/pinctrl/pinctrl-rockchip.c | 422 +++++++++++++++++++++++-- include/dt-bindings/pinctrl/rockchip.h | 21 +- include/linux/rockchip/grf.h | 6 + 4 files changed, 583 insertions(+), 85 deletions(-) mode change 100644 => 100755 include/linux/rockchip/grf.h diff --git a/arch/arm/boot/dts/rk3288-pinctrl.dtsi b/arch/arm/boot/dts/rk3288-pinctrl.dtsi index 7c207f10a0f9..2e9cb6539cba 100755 --- a/arch/arm/boot/dts/rk3288-pinctrl.dtsi +++ b/arch/arm/boot/dts/rk3288-pinctrl.dtsi @@ -17,9 +17,9 @@ gpio0: gpio0@ff750000 { compatible = "rockchip,rk3288-gpio-bank0"; reg = <0xff750000 0x100>, - <0xff730080 0x10>, + <0xff730080 0x10>, <0xff730060 0x0c>, - <0xff73006c 0x0c>; + <0xff73006c 0x0c>; reg-names = "base", "mux_bank0", "pull_bank0", "drv_bank0"; interrupts = ; //clocks = <&clk_gates8 9>; @@ -771,49 +771,6 @@ }; }; - - vol_domain { - ap0_vcc:ap0-vcc { - rockchip,pins = ; - rockchip,voltage = ; - }; - - ap1_vcc:ap1-vcc { - rockchip,pins = ; - rockchip,voltage = ; - }; - - cif_vcc:cif-vcc { - rockchip,pins = ; - rockchip,voltage = ; - }; - - flash_vcc:flash-vcc { - rockchip,pins = ; - rockchip,voltage = ; - }; - - vccio0_vcc:vccio0-vcc { - rockchip,pins = ; - rockchip,voltage = ; - }; - - vccio1_vcc:vccio1-vcc { - rockchip,pins = ; - rockchip,voltage = ; - }; - - lcdc0_vcc:lcdc0-vcc { - rockchip,pins = ; - rockchip,voltage = ; - }; - - lcdc1_vcc:lcdc1-vcc { - rockchip,pins = ; - rockchip,voltage = ; - }; - - }; gmac { mac_clk: mac-clk { @@ -850,5 +807,177 @@ }; //to add + + + + + + + + + vol_domain{ + //default 3.3V + lcdc_vcc:lcdc-vcc { + rockchip,pins = ; + rockchip,voltage = ; + }; + + dvp_vcc:dvp-vcc { + rockchip,pins = ; + rockchip,voltage = ; + }; + + flash0_vcc:flash0-vcc { + rockchip,pins = ; + rockchip,voltage = ; + }; + + flash1_vcc:flash1-vcc { + rockchip,pins = ; + rockchip,voltage = ; + }; + + wifi_vcc:wifi-vcc { + rockchip,pins = ; + rockchip,voltage = ; + }; + + bb_vcc:bb-vcc { + rockchip,pins = ; + rockchip,voltage = ; + }; + + audio_vcc:audio-vcc { + rockchip,pins = ; + rockchip,voltage = ; + }; + + sdcard_vcc:sdcard-vcc { + rockchip,pins = ; + rockchip,voltage = ; + }; + + gpio30_vcc:gpio30-vcc { + rockchip,pins = ; + rockchip,voltage = ; + }; + + gpio1830_vcc:gpio1830-vcc { + rockchip,pins = ; + rockchip,voltage = ; + }; + + + //1.8V + + lcdc_vcc_18:lcdc-vcc-18 { + rockchip,pins = ; + rockchip,voltage = ; + }; + + dvp_vcc_18:dvp-vcc-18 { + rockchip,pins = ; + rockchip,voltage = ; + }; + + flash0_vcc_18:flash0-vcc-18 { + rockchip,pins = ; + rockchip,voltage = ; + }; + + flash1_vcc_18:flash1-vcc-18 { + rockchip,pins = ; + rockchip,voltage = ; + }; + + wifi_vcc_18:wifi-vcc-18 { + rockchip,pins = ; + rockchip,voltage = ; + }; + + bb_vcc_18:bb-vcc-18 { + rockchip,pins = ; + rockchip,voltage = ; + }; + + audio_vcc_18:audio-vcc-18 { + rockchip,pins = ; + rockchip,voltage = ; + }; + + sdcard_vcc_18:sdcard-vcc-18 { + rockchip,pins = ; + rockchip,voltage = ; + }; + + gpio30_vcc_18:gpio30-vcc-18 { + rockchip,pins = ; + rockchip,voltage = ; + }; + + gpio1830_vcc_18:gpio1830-vcc-18 { + rockchip,pins = ; + rockchip,voltage = ; + }; + + + + + //3.3V + lcdc_vcc_33:lcdc-vcc-33 { + rockchip,pins = ; + rockchip,voltage = ; + }; + + dvp_vcc_33:dvp-vcc-33 { + rockchip,pins = ; + rockchip,voltage = ; + }; + + flash0_vcc_33:flash0-vcc-33 { + rockchip,pins = ; + rockchip,voltage = ; + }; + + flash1_vcc_33:flash1-vcc-33 { + rockchip,pins = ; + rockchip,voltage = ; + }; + + wifi_vcc_33:wifi-vcc-33 { + rockchip,pins = ; + rockchip,voltage = ; + }; + + bb_vcc_33:bb-vcc-33 { + rockchip,pins = ; + rockchip,voltage = ; + }; + + audio_vcc_33:audio-vcc-33 { + rockchip,pins = ; + rockchip,voltage = ; + }; + + sdcard_vcc_33:sdcard-vcc-33 { + rockchip,pins = ; + rockchip,voltage = ; + }; + + gpio30_vcc_33:gpio30-vcc-33 { + rockchip,pins = ; + rockchip,voltage = ; + }; + + gpio1830_vcc_33:gpio1830-vcc-33 { + rockchip,pins = ; + rockchip,voltage = ; + }; + + + }; + + + }; }; diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index ddf44078a3b7..41e0bfe0a42f 100755 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -47,6 +47,7 @@ #include #include #include +#include #ifdef CONFIG_DEBUG_FS #include @@ -150,6 +151,8 @@ struct rockchip_pin_ctrl { int mux_offset; void (*pull_calc_reg)(struct rockchip_pin_bank *bank, int pin_num, void __iomem **reg, u8 *bit); + void (*drv_calc_reg)(struct rockchip_pin_bank *bank, int pin_num, + void __iomem **reg, u8 *bit); }; struct rockchip_pin_config { @@ -541,6 +544,188 @@ static const struct pinctrl_ops rockchip_pctrl_ops = { }; +#define RK3288_GRF_GPIO1A_IOMUX 0x0000 +#define RK3288_GRF_GPIO5A_IOMUX 0x004C + +static int rk32_iomux_bit_op(struct rockchip_pin_bank *bank, int pin, int mux, void __iomem *reg, int bits) +{ + u32 data; + u8 bit; + unsigned long flags; + struct rockchip_pinctrl *info = bank->drvdata; + void __iomem *reg0 = reg; + + if(bits == 2) + { + reg += (pin / 8) * 4; + bit = (pin % 8) * 2; + + spin_lock_irqsave(&bank->slock, flags); + + data = (3 << (bit + 16)); + data |= (mux & 3) << bit; + writel(data, reg); + + spin_unlock_irqrestore(&bank->slock, flags); + + } + else if(bits == 4) + { + reg += (pin / 4) * 4; + bit = (pin % 4) * 4; + + spin_lock_irqsave(&bank->slock, flags); + + data = (0x0f << (bit + 16)); + data |= (mux & 0x0f) << bit; + writel(data, reg); + + spin_unlock_irqrestore(&bank->slock, flags); + } + else + { + printk("%s:unknow bits %d\n",__func__, bits); + } + + DBG_PINCTRL("%s:reg=0x%x,data=0x%x\n",__func__, reg - reg0, data); + return 0; + +} + + +static int rockchip_set_rk32_mux(struct rockchip_pin_bank *bank, int pin, int mux) +{ + struct rockchip_pinctrl *info = bank->drvdata; + void __iomem *reg = info->reg_mux; + unsigned long flags; + u8 bit; + u32 data; + struct union_mode m; + u8 bits = 0; + + m.mode = mux; + + if((m.mux.bank != bank->bank_num)) + { + printk("%s:error:mux_bank(%d) != gpio_bank(%d)\n",__func__, m.mux.bank, bank->bank_num); + return; + } + + switch(bank->bank_num) + { + case 0: + //pmu + reg = bank->reg_mux_bank0; + reg += RK3288_GRF_GPIO0_A_IOMUX; + bits = 2; + rk32_iomux_bit_op(bank, pin, mux, reg, bits); + break; + + case 1: + reg += RK3288_GRF_GPIO1A_IOMUX; + if((m.mux.goff == 0x0d)) + { + bits = 2; + } + rk32_iomux_bit_op(bank, pin, mux, reg, bits); + break; + + case 2: + reg += RK3288_GRF_GPIO2A_IOMUX; + if((m.mux.goff == 0x0a) || (m.mux.goff == 0x0b) || (m.mux.goff == 0x0c)) + { + bits = 2; + } + rk32_iomux_bit_op(bank, pin, mux, reg, bits); + break; + + case 3: + reg += RK3288_GRF_GPIO3A_IOMUX; + if((m.mux.goff == 0x0a) || (m.mux.goff == 0x0b) || (m.mux.goff == 0x0c)) + { + bits = 2; + } + else if(m.mux.goff == 0x0d) + { + bits = 4; + } + + rk32_iomux_bit_op(bank, pin, mux, reg, bits); + break; + + case 4: + reg += RK3288_GRF_GPIO4AL_IOMUX; + if((m.mux.goff == 0x0a) || (m.mux.goff == 0x0b)) + { + bits = 4; + } + else if((m.mux.goff == 0x0c) || (m.mux.goff == 0x0d)) + { + bits = 2; + } + + rk32_iomux_bit_op(bank, pin, mux, reg, bits); + + break; + + case 5: + reg += RK3288_GRF_GPIO5A_IOMUX; + if((m.mux.goff == 0x0b) || (m.mux.goff == 0x0c)) + { + bits = 2; + } + + rk32_iomux_bit_op(bank, pin, mux, reg, bits); + + break; + + case 6: + reg += RK3288_GRF_GPIO6A_IOMUX; + if((m.mux.goff == 0x0a) || (m.mux.goff == 0x0b) || (m.mux.goff == 0x0c)) + { + bits = 2; + } + + rk32_iomux_bit_op(bank, pin, mux, reg, bits); + break; + + case 7: + reg += RK3288_GRF_GPIO7A_IOMUX; + if((m.mux.goff == 0x0a) || (m.mux.goff == 0x0b)) + { + bits = 2; + } + else if((m.mux.goff == 0x0c)) + { + bits = 4; + } + + rk32_iomux_bit_op(bank, pin, mux, reg, bits); + break; + + case 8: + reg += RK3288_GRF_GPIO8A_IOMUX; + if((m.mux.goff == 0x0a) || (m.mux.goff == 0x0b)) + { + bits = 2; + } + + rk32_iomux_bit_op(bank, pin, mux, reg, bits); + break; + + default: + printk("%s:unknow bank num %d\n", __func__, bank->bank_num); + break; + + } + + DBG_PINCTRL("%s:bank_num=%d,pin=%d,mux=%d,bits=%d\n",__func__, bank->bank_num, pin, mux&0x0f, bits); + + return 0; + +} + + /* * Set a new mux function for a pin. @@ -573,6 +758,12 @@ static void rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) printk("%s:warning ignore bank num %d\n",__func__, bank->bank_num); return ; } + + if(info->ctrl->type == RK3288) + { + rockchip_set_rk32_mux(bank, pin, mux); + return; + } m.mode = mux; @@ -792,6 +983,23 @@ static struct func_to_reg_offset rk3188_func_to_vol_reg_offset[] = FUNC_GROUP_TO_REG_OFFSET(TYPE_VOL_REG, "lcdc1-vcc", "vol_domain", "lcdc1-vcc", RK3188_GRF_IO_CON4, 15 ,1), }; + +static struct func_to_reg_offset rk3288_func_to_vol_reg_offset[] = +{ + FUNC_GROUP_TO_REG_OFFSET(TYPE_VOL_REG, "lcdc-vcc", "vol_domain", "lcdc-vcc", RK3288_GRF_IO_VSEL, 0 ,1), + FUNC_GROUP_TO_REG_OFFSET(TYPE_VOL_REG, "dvp-vcc", "vol_domain", "dvp-vcc", RK3288_GRF_IO_VSEL, 1 ,1), + FUNC_GROUP_TO_REG_OFFSET(TYPE_VOL_REG, "flash0-vcc", "vol_domain", "flash0-vcc", RK3288_GRF_IO_VSEL, 2 ,1), + FUNC_GROUP_TO_REG_OFFSET(TYPE_VOL_REG, "flash1-vcc", "vol_domain", "flash1-vcc", RK3288_GRF_IO_VSEL, 3 ,1), + FUNC_GROUP_TO_REG_OFFSET(TYPE_VOL_REG, "wifi-vcc", "vol_domain", "wifi-vcc", RK3288_GRF_IO_VSEL, 4 ,1), + FUNC_GROUP_TO_REG_OFFSET(TYPE_VOL_REG, "bb-vcc", "vol_domain", "bb-vcc", RK3288_GRF_IO_VSEL, 5 ,1), + FUNC_GROUP_TO_REG_OFFSET(TYPE_VOL_REG, "audio-vcc", "vol_domain", "audio-vcc", RK3288_GRF_IO_VSEL, 6 ,1), + FUNC_GROUP_TO_REG_OFFSET(TYPE_VOL_REG, "sdcard-vcc", "vol_domain", "sdcard-vcc", RK3288_GRF_IO_VSEL, 7 ,1), + + FUNC_GROUP_TO_REG_OFFSET(TYPE_VOL_REG, "gpio30-vcc", "vol_domain", "gpio30-vcc", RK3288_GRF_IO_VSEL, 8 ,1), + FUNC_GROUP_TO_REG_OFFSET(TYPE_VOL_REG, "gpio1830-vcc", "vol_domain", "gpio1830-vcc", RK3288_GRF_IO_VSEL, 9 ,1), +}; + + static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, int pin_num, void __iomem **reg, u8 *bit) { @@ -835,6 +1043,55 @@ static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, DBG_PINCTRL("%s:GPIO%d-%d, pull_reg=0x%p, bit=%d\n", __func__, bank->bank_num, pin_num, *reg, *bit); } +static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, + int pin_num, void __iomem **reg, u8 *bit) +{ + struct rockchip_pinctrl *info = bank->drvdata; + + /* The first 24 pins of the first bank are located elsewhere */ + if (bank->bank_type == RK3288_BANK0 && pin_num < 24) { + *reg = bank->reg_pull_bank0 + + ((pin_num / 8) * 4); + *bit = pin_num % 8; + *bit *= 2; + } else { + *reg = info->reg_pull; + *reg += bank->bank_num * 0x10; + *reg += ((pin_num / 8) * 4); + + *bit = (pin_num % 8); + *bit *= 2; + } + + DBG_PINCTRL("%s:GPIO%d-%d, pull_reg=0x%p, bit=%d\n", __func__, bank->bank_num, pin_num, *reg, *bit); +} + + +static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, + int pin_num, void __iomem **reg, u8 *bit) +{ + struct rockchip_pinctrl *info = bank->drvdata; + + /* The first 24 pins of the first bank are located elsewhere */ + if (bank->bank_type == RK3288_BANK0 && pin_num < 24) { + *reg = bank->reg_drv_bank0 + + ((pin_num / 8) * 4); + *bit = pin_num % 8; + *bit *= 2; + } else { + *reg = info->reg_drv; + *reg += bank->bank_num * 0x10; + *reg += ((pin_num / 8) * 4); + + *bit = (pin_num % 8); + *bit *= 2; + } + + DBG_PINCTRL("%s:GPIO%d-%d, pull_reg=0x%p, bit=%d\n", __func__, bank->bank_num, pin_num, *reg, *bit); +} + + + static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num) { struct rockchip_pinctrl *info = bank->drvdata; @@ -977,7 +1234,8 @@ static int _rockchip_pinconf_get(struct rockchip_pin_bank *bank, struct func_to_reg_offset reg_offset[4];//same name count should be less four struct func_to_reg_offset *func_to_reg; int i = 0, ii = 0, j = 0, jj = 0, num = 0; - int data = 0; + int data = 0; + u8 bit; unsigned long flags; void __iomem *reg; @@ -1076,30 +1334,75 @@ static int _rockchip_pinconf_get(struct rockchip_pin_bank *bank, break; + case RK3288: + + switch(config_type) + { + case TYPE_VOL_REG: + //compare group_name + func_to_reg = rk3288_func_to_vol_reg_offset; + num = ARRAY_SIZE(rk3288_func_to_vol_reg_offset); + for(i = 0; i < num; i++) + { + //lcdc-vcc-33 = lcdc-vcc and lcdc-vcc-18 = lcdc-vcc + if(strstr(info->groups[group].name, func_to_reg[i].group_name) != NULL) + { + reg_offset[j++] = func_to_reg[i]; + DBG_PINCTRL("%s:select \"%s\" dts:\"%s\"\n",__func__, func_to_reg[i].group_name, info->groups[group].name); + } + } + + break; + + case TYPE_DRV_REG: + + ctrl->drv_calc_reg(bank, pin_num, ®, &bit); + + data = readl_relaxed(reg) >> bit; + data &= (1 << 2) - 1; + + *config = data; + + break; + default: + break; + + } + + break; + default: break; } - if(j <= 0) - { - printk("%s:could find config register for PIN%d-%d,type=%d,num=%d\n",__func__, bank->bank_num, pin_num, config_type, num); - return -1; - } - - - for(i=0; i < j; i++) + + if((ctrl->type == RK3188) || ((ctrl->type == RK3288) && (config_type == TYPE_VOL_REG))) { - reg = info->reg_base + reg_offset[i].reg_offset; - spin_lock_irqsave(&bank->slock, flags); - data = readl_relaxed(reg) >> reg_offset[i].bit_offset; - data &= reg_offset[i].bit_mask; - spin_unlock_irqrestore(&bank->slock, flags); + if(j <= 0) + { + printk("%s:could find config register for PIN%d-%d,type=%d,num=%d\n",__func__, bank->bank_num, pin_num, config_type, num); + return -1; + } - *config = data; + + for(i=0; i < j; i++) + { + reg = info->reg_base + reg_offset[i].reg_offset; + spin_lock_irqsave(&bank->slock, flags); + data = readl_relaxed(reg) >> reg_offset[i].bit_offset; + data &= reg_offset[i].bit_mask; + spin_unlock_irqrestore(&bank->slock, flags); + + *config = data; + + DBG_PINCTRL("%s:reg_offset[%d]=0x%x,,bit_offset[%d]=0x%x,data[%d]=0x%x\n",__func__, i, reg_offset[i].reg_offset, i, reg_offset[i].bit_offset, i, data); + } - DBG_PINCTRL("%s:reg_offset[%d]=0x%x,,bit_offset[%d]=0x%x,data[%d]=0x%x\n",__func__, i, reg_offset[i].reg_offset, i, reg_offset[i].bit_offset, i, data); } - + else if((ctrl->type == RK3288) && (config_type == TYPE_DRV_REG)) + { + DBG_PINCTRL("%s:GPIO-%d %d drv=0x%x\n",__func__, bank->bank_num, pin_num, (u32)*config); + } return 0; } @@ -1114,7 +1417,8 @@ static int _rockchip_pinconf_set(struct rockchip_pin_bank *bank, struct func_to_reg_offset reg_offset[4];//same name count should be less four struct func_to_reg_offset *func_to_reg; int i = 0, ii = 0, j = 0, jj = 0, num = 0; - int data = 0, value = 0; + int data = 0, value = 0; + u8 bit; unsigned long flags; void __iomem *reg; @@ -1213,29 +1517,79 @@ static int _rockchip_pinconf_set(struct rockchip_pin_bank *bank, break; + case RK3288: + + switch(config_type) + { + case TYPE_VOL_REG: + //compare group_name + func_to_reg = rk3288_func_to_vol_reg_offset; + num = ARRAY_SIZE(rk3288_func_to_vol_reg_offset); + for(i = 0; i < num; i++) + { + //lcdc-vcc-33 = lcdc-vcc and lcdc-vcc-18 = lcdc-vcc + if(strstr(info->groups[group].name, func_to_reg[i].group_name) != NULL) + { + reg_offset[j++] = func_to_reg[i]; + DBG_PINCTRL("%s:select \"%s\" dts:\"%s\"\n",__func__, func_to_reg[i].group_name, info->groups[group].name); + } + } + + break; + + case TYPE_DRV_REG: + + ctrl->drv_calc_reg(bank, pin_num, ®, &bit); + + spin_lock_irqsave(&bank->slock, flags); + + data = arg << bit; + data &= (3<slock, flags); + + break; + default: + break; + + } + + break; + default: break; } - if(j <= 0) + + if((ctrl->type == RK3188) || ((ctrl->type == RK3288) && (config_type == TYPE_VOL_REG))) { - printk("%s:could find config register for PIN%d-%d,type=%d,num=%d\n",__func__, bank->bank_num, pin_num, config_type, num); - return -1; + if(j <= 0) + { + printk("%s:could find config register for PIN%d-%d,type=%d,num=%d\n",__func__, bank->bank_num, pin_num, config_type, num); + return -1; + } + + for(i=0; i < j; i++) + { + reg = info->reg_base + reg_offset[i].reg_offset; + data |= ((arg & reg_offset[i].bit_mask) << (16 + reg_offset[i].bit_offset)); + data |= ((arg & reg_offset[i].bit_mask) << reg_offset[i].bit_offset); + spin_lock_irqsave(&bank->slock, flags); + writel_relaxed(data, reg); + value = readl_relaxed(reg); + spin_unlock_irqrestore(&bank->slock, flags); + DBG_PINCTRL("%s:reg_offset[%d]=0x%x,,bit_offset[%d]=%d,data[%d]=0x%08x,result=0x%08x,arg=%d\n",__func__, i, reg_offset[i].reg_offset, i, reg_offset[i].bit_offset, i, data, value, arg); + } + } - - for(i=0; i < j; i++) + + else if((ctrl->type == RK3288) && (config_type == TYPE_DRV_REG)) { - reg = info->reg_base + reg_offset[i].reg_offset; - data |= ((arg & reg_offset[i].bit_mask) << (16 + reg_offset[i].bit_offset)); - data |= ((arg & reg_offset[i].bit_mask) << reg_offset[i].bit_offset); - spin_lock_irqsave(&bank->slock, flags); - writel_relaxed(data, reg); - value = readl_relaxed(reg); - spin_unlock_irqrestore(&bank->slock, flags); - DBG_PINCTRL("%s:reg_offset[%d]=0x%x,,bit_offset[%d]=%d,data[%d]=0x%08x,result=0x%08x,arg=%d\n",__func__, i, reg_offset[i].reg_offset, i, reg_offset[i].bit_offset, i, data, value, arg); + DBG_PINCTRL("%s:GPIO-%d %d data=%d\n",__func__, bank->bank_num, pin_num, data); } - return 0; } @@ -2654,7 +3008,9 @@ static struct rockchip_pin_ctrl rk3288_pin_ctrl = { .nr_banks = ARRAY_SIZE(rk3288_pin_banks), .label = "RK3288-GPIO", .type = RK3288, - .mux_offset = 0x0, + .mux_offset = 0x0, + .pull_calc_reg = rk3288_calc_pull_reg_and_bit, + .drv_calc_reg = rk3288_calc_drv_reg_and_bit, }; diff --git a/include/dt-bindings/pinctrl/rockchip.h b/include/dt-bindings/pinctrl/rockchip.h index 1550654d620e..5e07df24806f 100755 --- a/include/dt-bindings/pinctrl/rockchip.h +++ b/include/dt-bindings/pinctrl/rockchip.h @@ -50,18 +50,25 @@ #define VIRTUAL_PIN_FOR_LCDC0_VCC 0xfA60 #define VIRTUAL_PIN_FOR_LCDC1_VCC 0xfA70 + +#define RK32_VIRTUAL_PIN_FOR_LCDC_VCC 0xfA00 +#define RK32_VIRTUAL_PIN_FOR_DVP_VCC 0xfA10 +#define RK32_VIRTUAL_PIN_FOR_FLASH0_VCC 0xfA20 +#define RK32_VIRTUAL_PIN_FOR_FLASH1_VCC 0xfA30 +#define RK32_VIRTUAL_PIN_FOR_WIFI_VCC 0xfA40 +#define RK32_VIRTUAL_PIN_FOR_BB_VCC 0xfA50 +#define RK32_VIRTUAL_PIN_FOR_AUDIO_VCC 0xfA60 +#define RK32_VIRTUAL_PIN_FOR_SDCARD_VCC 0xfA70 + +#define RK32_VIRTUAL_PIN_FOR_GPIO30_VCC 0xfB00 +#define RK32_VIRTUAL_PIN_FOR_GPIO1830_VCC 0xfB10 + + #define TYPE_PULL_REG 0x01 #define TYPE_VOL_REG 0x02 #define TYPE_DRV_REG 0x03 #define TYPE_TRI_REG 0x04 -#define RK3188_GRF_IO_CON0 0xf4 -#define RK3188_GRF_IO_CON1 0xf8 -#define RK3188_GRF_IO_CON2 0xfc -#define RK3188_GRF_IO_CON3 0x100 -#define RK3188_GRF_IO_CON4 0x104 - - #define RK2928_PULL_OFFSET 0x118 #define RK2928_PULL_PINS_PER_REG 16 #define RK2928_PULL_BANK_STRIDE 8 diff --git a/include/linux/rockchip/grf.h b/include/linux/rockchip/grf.h old mode 100644 new mode 100755 index 62a97b4d8420..15a2c580b449 --- a/include/linux/rockchip/grf.h +++ b/include/linux/rockchip/grf.h @@ -106,6 +106,12 @@ #define RK3188_GRF_FLASH_DATA_PULL 0x01a0 #define RK3188_GRF_FLASH_CMD_PULL 0x01a4 + +#define RK3288_GRF_GPIO0_A_IOMUX 0x0084 +#define RK3288_GRF_GPIO0_B_IOMUX 0x0088 +#define RK3288_GRF_GPIO0_C_IOMUX 0x008c +#define RK3288_GRF_GPIO0_D_IOMUX 0x0090 + #define RK3288_GRF_GPIO1D_IOMUX 0x000c #define RK3288_GRF_GPIO2A_IOMUX 0x0010 #define RK3288_GRF_GPIO2B_IOMUX 0x0014 -- 2.34.1