From 5a940870c8876218690a83de25a9f5e9ff7931bf Mon Sep 17 00:00:00 2001
From: qjb <qjb@rock-chips.com>
Date: Tue, 25 Feb 2014 17:22:13 +0800
Subject: [PATCH] rk3188 i2s dts : set i2s drive default 8ma

---
 arch/arm/boot/dts/rk3188-pinctrl.dtsi | 14 +++++++-------
 sound/soc/rockchip/rk30_i2s.c         |  6 +-----
 2 files changed, 8 insertions(+), 12 deletions(-)

diff --git a/arch/arm/boot/dts/rk3188-pinctrl.dtsi b/arch/arm/boot/dts/rk3188-pinctrl.dtsi
index c5e665b003da..81151a547629 100755
--- a/arch/arm/boot/dts/rk3188-pinctrl.dtsi
+++ b/arch/arm/boot/dts/rk3188-pinctrl.dtsi
@@ -390,7 +390,7 @@
 				rockchip,pins = <I2S0_MCLK>;
 				rockchip,pull = <VALUE_PULL_DISABLE>;
 				//rockchip,voltage = <VALUE_VOL_DEFAULT>;
-				rockchip,drive = <VALUE_DRV_DEFAULT>;
+				rockchip,drive = <VALUE_DRV_8MA>;
 				//rockchip,tristate = <VALUE_TRI_DEFAULT>;
 
 			};
@@ -399,7 +399,7 @@
 				rockchip,pins = <I2S0_SCLK>;
 				rockchip,pull = <VALUE_PULL_DISABLE>;
 				//rockchip,voltage = <VALUE_VOL_DEFAULT>;
-				rockchip,drive = <VALUE_DRV_DEFAULT>;
+				rockchip,drive = <VALUE_DRV_8MA>;
 				//rockchip,tristate = <VALUE_TRI_DEFAULT>;
 
 			};
@@ -408,7 +408,7 @@
 				rockchip,pins = <I2S0_LRCKRX>;
 				rockchip,pull = <VALUE_PULL_DISABLE>;
 				//rockchip,voltage = <VALUE_VOL_DEFAULT>;
-				rockchip,drive = <VALUE_DRV_DEFAULT>;
+				rockchip,drive = <VALUE_DRV_8MA>;
 				//rockchip,tristate = <VALUE_TRI_DEFAULT>;
 
 			};
@@ -417,7 +417,7 @@
 				rockchip,pins = <I2S0_LRCKTX>;
 				rockchip,pull = <VALUE_PULL_DISABLE>;
 				//rockchip,voltage = <VALUE_VOL_DEFAULT>;
-				rockchip,drive = <VALUE_DRV_DEFAULT>;
+				rockchip,drive = <VALUE_DRV_8MA>;
 				//rockchip,tristate = <VALUE_TRI_DEFAULT>;
 
 			};
@@ -426,7 +426,7 @@
 				rockchip,pins = <I2S0_SDO>;
 				rockchip,pull = <VALUE_PULL_DISABLE>;
 				//rockchip,voltage = <VALUE_VOL_DEFAULT>;
-				rockchip,drive = <VALUE_DRV_DEFAULT>;
+				rockchip,drive = <VALUE_DRV_8MA>;
 				//rockchip,tristate = <VALUE_TRI_DEFAULT>;
 
 			};
@@ -435,7 +435,7 @@
 				rockchip,pins = <I2S0_SDI>;
 				rockchip,pull = <VALUE_PULL_DISABLE>;
 				//rockchip,voltage = <VALUE_VOL_DEFAULT>;
-				rockchip,drive = <VALUE_DRV_DEFAULT>;
+				rockchip,drive = <VALUE_DRV_8MA>;
 				//rockchip,tristate = <VALUE_TRI_DEFAULT>;
 
 			};
@@ -447,7 +447,7 @@
 						<FUNC_TO_GPIO(I2S0_LRCKTX)>,
 						<FUNC_TO_GPIO(I2S0_SDO)>,
 						<FUNC_TO_GPIO(I2S0_SDI)>;
-				rockchip,drive = <VALUE_DRV_DEFAULT>;
+				rockchip,drive = <VALUE_DRV_8MA>;
 			};
 		};
 	
diff --git a/sound/soc/rockchip/rk30_i2s.c b/sound/soc/rockchip/rk30_i2s.c
index e72d893505ca..c28d46b75633 100755
--- a/sound/soc/rockchip/rk30_i2s.c
+++ b/sound/soc/rockchip/rk30_i2s.c
@@ -192,11 +192,7 @@ static void rockchip_snd_rxctrl(struct rk30_i2s_info *i2s, int on)
 	}
 
 	spin_unlock_irqrestore(&lock, flags);
-#ifdef CONFIG_SND_SOC_RT5631
-//bard 7-16 s
-		schedule_delayed_work(&rt5631_delay_cap,HZ/4);
-//bard 7-16 e
-#endif
+
 	if (is_need_delay){
 		while(readl(&(pheadi2s->I2S_CLR)) && clr_error_count){
 			udelay(1);
-- 
2.34.1