From 5afff3b917f576ef49016dc3fe785ca843eae791 Mon Sep 17 00:00:00 2001 From: "Vikram S. Adve" Date: Fri, 9 Nov 2001 02:15:52 +0000 Subject: [PATCH] Bug fix: Need to include the stack offset "bias" in assembly code itself. Added class UltraSparcCacheInfo. Added function to convert float to int by copying via memory. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@1224 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/SparcV9/SparcV9Internals.h | 47 ++++++++++++++++++++++----- 1 file changed, 39 insertions(+), 8 deletions(-) diff --git a/lib/Target/SparcV9/SparcV9Internals.h b/lib/Target/SparcV9/SparcV9Internals.h index abcd756ad93..f8707c2d521 100644 --- a/lib/Target/SparcV9/SparcV9Internals.h +++ b/lib/Target/SparcV9/SparcV9Internals.h @@ -16,8 +16,9 @@ #include "SparcRegClassInfo.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Target/MachineInstrInfo.h" -#include "llvm/Target/MachineFrameInfo.h" #include "llvm/Target/MachineSchedInfo.h" +#include "llvm/Target/MachineFrameInfo.h" +#include "llvm/Target/MachineCacheInfo.h" #include "llvm/CodeGen/RegClass.h" #include "llvm/Type.h" @@ -115,9 +116,9 @@ public: vector& tempVec) const; - // Create an instruction sequence to copy an integer value `val' from an - // integer to a floating point register `dest'. val must be an integral - // type. dest must be a Float or Double. + // Create an instruction sequence to copy an integer value `val' + // to a floating point value `dest' by copying to memory and back. + // val must be an integral type. dest must be a Float or Double. // The generated instructions are returned in `minstrVec'. // Any temp. registers (TmpInstruction) created are returned in `tempVec'. // @@ -127,6 +128,17 @@ public: vector& minstrVec, vector& tempVec, TargetMachine& target) const; + + // Similarly, create an instruction sequence to copy an FP value + // `val' to an integer value `dest' by copying to memory and back. + // See the previous function for information about return values. + // + virtual void CreateCodeToCopyFloatToInt(Method* method, + Value* val, + Instruction* dest, + vector& minstrVec, + vector& tempVec, + TargetMachine& target) const; }; @@ -1229,17 +1241,34 @@ public: } private: + // All stack addresses must be offset by 0x7ff (2047) on Sparc V9. + static const int OFFSET = (int) 0x7ff; static const int StackFrameSizeAlignment = 16; static const int MinStackFrameSize = 176; static const int NumFixedOutgoingArgs = 6; static const int SizeOfEachArgOnStack = 8; - static const int StaticAreaOffsetFromFP = -1; - static const int FirstIncomingArgOffsetFromFP = 126; - static const int FirstOutgoingArgOffsetFromSP = 128; - static const int FirstOptionalOutgoingArgOffsetFromSP = 176; + static const int StaticAreaOffsetFromFP = -1 + OFFSET; + static const int FirstIncomingArgOffsetFromFP = 128 + OFFSET; + static const int FirstOptionalIncomingArgOffsetFromFP = 176 + OFFSET; + static const int FirstOutgoingArgOffsetFromSP = 128 + OFFSET; + static const int FirstOptionalOutgoingArgOffsetFromSP = 176 + OFFSET; }; +//--------------------------------------------------------------------------- +// class UltraSparcCacheInfo +// +// Purpose: +// Interface to cache parameters for the UltraSPARC. +// Just use defaults for now. +//--------------------------------------------------------------------------- + +class UltraSparcCacheInfo: public MachineCacheInfo { +public: + /*ctor*/ UltraSparcCacheInfo (const TargetMachine& target) : + MachineCacheInfo(target) {} +}; + //--------------------------------------------------------------------------- // class UltraSparcMachine @@ -1257,6 +1286,7 @@ private: UltraSparcSchedInfo schedInfo; UltraSparcRegInfo regInfo; UltraSparcFrameInfo frameInfo; + UltraSparcCacheInfo cacheInfo; public: UltraSparc(); virtual ~UltraSparc() {} @@ -1265,6 +1295,7 @@ public: virtual const MachineSchedInfo &getSchedInfo() const { return schedInfo; } virtual const MachineRegInfo &getRegInfo() const { return regInfo; } virtual const MachineFrameInfo &getFrameInfo() const { return frameInfo; } + virtual const MachineCacheInfo &getCacheInfo() const { return cacheInfo; } // compileMethod - For the sparc, we do instruction selection, followed by // delay slot scheduling, then register allocation. -- 2.34.1