From 5b46d62c4459dbfd56bb6ac650a271cd02365092 Mon Sep 17 00:00:00 2001 From: Jim Grosbach Date: Tue, 14 Sep 2010 21:28:17 +0000 Subject: [PATCH] Add predicate and 's' bit operands to PICADD instruction lowering. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113860 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/ARMAsmPrinter.cpp | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/lib/Target/ARM/ARMAsmPrinter.cpp b/lib/Target/ARM/ARMAsmPrinter.cpp index 47d68fa80d2..067d1a6bf89 100644 --- a/lib/Target/ARM/ARMAsmPrinter.cpp +++ b/lib/Target/ARM/ARMAsmPrinter.cpp @@ -1349,6 +1349,11 @@ void ARMAsmPrinter::printInstructionThroughMCStreamer(const MachineInstr *MI) { AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg())); AddInst.addOperand(MCOperand::CreateReg(ARM::PC)); AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg())); + // Add predicate operands. + AddInst.addOperand(MCOperand::CreateImm(MI->getOperand(3).getImm())); + AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(4).getReg())); + // Add 's' bit operand (always reg0 for this) + AddInst.addOperand(MCOperand::CreateReg(0)); OutStreamer.EmitInstruction(AddInst); return; } -- 2.34.1