From 5c2eebd93186bcd2c97b6829ff247a782244b4f7 Mon Sep 17 00:00:00 2001 From: Jacob Chen Date: Fri, 9 Dec 2016 14:40:03 +0800 Subject: [PATCH] UPSTREAM: ARM: dts: rockchip: move rk3288 usbphy under the GRF node The rk3288 usbphy is completely enclosed in the general register files and the updated binding allows it to be a subnode of the GRF now. So move the node appropriately. Signed-off-by: Heiko Stuebner Change-Id: I85ca27786da0cd388ef6b4fddb11747761a579a3 (cherry picked from commit 546a3521f251462128d877e48fb3544c74976ce4) Signed-off-by: Jacob Chen --- arch/arm/boot/dts/rk3288.dtsi | 65 +++++++++++++++++------------------ 1 file changed, 32 insertions(+), 33 deletions(-) diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index df13ecef29f7..e5bedf896874 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -859,6 +859,38 @@ compatible = "rockchip,rk3288-io-voltage-domain"; status = "disabled"; }; + + usbphy: phy { + compatible = "rockchip,rk3288-usb-phy"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + usbphy0: usb-phy0 { + #phy-cells = <0>; + reg = <0x320>; + clocks = <&cru SCLK_OTGPHY0>; + clock-names = "phyclk"; + resets = <&cru SRST_USBOTG_PHY>; + reset-names = "phy-reset"; + }; + + usbphy1: usb-phy1 { + #phy-cells = <0>; + reg = <0x334>; + clocks = <&cru SCLK_OTGPHY1>; + clock-names = "phyclk"; + }; + + usbphy2: usb-phy2 { + #phy-cells = <0>; + reg = <0x348>; + clocks = <&cru SCLK_OTGPHY2>; + clock-names = "phyclk"; + resets = <&cru SRST_USBHOST1_PHY>; + reset-names = "phy-reset"; + }; + }; }; wdt: watchdog@ff800000 { @@ -1252,39 +1284,6 @@ }; }; - usbphy: phy { - compatible = "rockchip,rk3288-usb-phy"; - rockchip,grf = <&grf>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - usbphy0: usb-phy0 { - #phy-cells = <0>; - reg = <0x320>; - clocks = <&cru SCLK_OTGPHY0>; - clock-names = "phyclk"; - resets = <&cru SRST_USBOTG_PHY>; - reset-names = "phy-reset"; - }; - - usbphy1: usb-phy1 { - #phy-cells = <0>; - reg = <0x334>; - clocks = <&cru SCLK_OTGPHY1>; - clock-names = "phyclk"; - }; - - usbphy2: usb-phy2 { - #phy-cells = <0>; - reg = <0x348>; - clocks = <&cru SCLK_OTGPHY2>; - clock-names = "phyclk"; - resets = <&cru SRST_USBHOST1_PHY>; - reset-names = "phy-reset"; - }; - }; - cif_isp0: cif_isp@ff910000 { compatible = "rockchip,rk3288-cif-isp"; rockchip,grf = <&grf>; -- 2.34.1