From 5dd546a46322680abadc6c9dd091a215b4293f1e Mon Sep 17 00:00:00 2001 From: Colin Cross Date: Tue, 9 Nov 2010 13:50:25 -0800 Subject: [PATCH] ARM: tegra: dvfs: Add config options to disable dvfs Change-Id: I401ab5587f28dfabaf0aae1ffa062a2411a1ad92 Signed-off-by: Colin Cross --- arch/arm/mach-tegra/Kconfig | 9 +++ arch/arm/mach-tegra/tegra2_dvfs.c | 126 +++++++++++++++++------------- 2 files changed, 82 insertions(+), 53 deletions(-) diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index 398af59d7e3e..b916b99aacda 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig @@ -68,6 +68,15 @@ config TEGRA_PWM endif +config TEGRA_CPU_DVFS + bool "Enable voltage scaling on Tegra CPU" + default y + +config TEGRA_CORE_DVFS + bool "Enable voltage scaling on Tegra core" + depends on TEGRA_CORE_CPU + default y + config TEGRA_IOVMM_GART bool "Enable I/O virtual memory manager for GART" depends on ARCH_TEGRA_2x_SOC diff --git a/arch/arm/mach-tegra/tegra2_dvfs.c b/arch/arm/mach-tegra/tegra2_dvfs.c index 4a831435991e..265a7b538f7f 100644 --- a/arch/arm/mach-tegra/tegra2_dvfs.c +++ b/arch/arm/mach-tegra/tegra2_dvfs.c @@ -40,29 +40,41 @@ static int cpu_core_millivolts[MAX_DVFS_FREQS]; #define KHZ 1000 #define MHZ 1000000 -#define CPU_DVFS(_clk_name, _process_id, _mult, _freqs...) \ - { \ - .clk_name = _clk_name, \ - .reg_id = CORE_REGULATOR, \ - .cpu = false, \ - .process_id = _process_id, \ - .freqs = {_freqs}, \ - .freqs_mult = _mult, \ - .auto_dvfs = true, \ - .higher = true, \ - .max_millivolts = CORE_MAX_MILLIVOLTS \ - }, \ - { \ - .clk_name = _clk_name, \ - .reg_id = CPU_REGULATOR, \ - .cpu = true, \ - .process_id = _process_id, \ - .freqs = {_freqs}, \ - .freqs_mult = _mult, \ - .auto_dvfs = true, \ - .max_millivolts = CPU_MAX_MILLIVOLTS \ - } +#ifdef CONFIG_TEGRA_CPU_DVFS +#define CPU_DVFS_CPU(_clk_name, _process_id, _mult, _freqs...) \ + { \ + .clk_name = _clk_name, \ + .reg_id = CPU_REGULATOR, \ + .cpu = true, \ + .process_id = _process_id, \ + .freqs = {_freqs}, \ + .freqs_mult = _mult, \ + .auto_dvfs = true, \ + .max_millivolts = CPU_MAX_MILLIVOLTS \ + }, + +#ifdef CONFIG_TEGRA_CORE_DVFS /* CPU_DVFS && CORE_DVFS */ +#define CPU_DVFS_CORE(_clk_name, _process_id, _mult, _freqs...) \ + { \ + .clk_name = _clk_name, \ + .reg_id = CORE_REGULATOR, \ + .cpu = false, \ + .process_id = _process_id, \ + .freqs = {_freqs}, \ + .freqs_mult = _mult, \ + .auto_dvfs = true, \ + .higher = true, \ + .max_millivolts = CORE_MAX_MILLIVOLTS \ + }, +#else /* CPU_DVFS && !CORE_DVFS */ +#define CPU_DVFS_CORE(_clk_name, _process_id, _mult, _freqs...) +#endif +#else /* !CPU_DVFS */ +#define CPU_DVFS_CPU(_clk_name, _process_id, _mult, _freqs...) +#define CPU_DVFS_CORE(_clk_name, _process_id, _mult, _freqs...) +#endif +#ifdef CONFIG_TEGRA_CORE_DVFS #define CORE_DVFS(_clk_name, _auto, _mult, _freqs...) \ { \ .clk_name = _clk_name, \ @@ -72,14 +84,22 @@ static int cpu_core_millivolts[MAX_DVFS_FREQS]; .freqs_mult = _mult, \ .auto_dvfs = _auto, \ .max_millivolts = CORE_MAX_MILLIVOLTS \ - } + }, +#else +#define CORE_DVFS(_clk_name, _process_id, _mult, _freqs...) +#endif + +#define CPU_DVFS(_clk_name, _process_id, _mult, _freqs...) \ + CPU_DVFS_CORE(_clk_name, _process_id, _mult, _freqs) \ + CPU_DVFS_CPU(_clk_name, _process_id, _mult, _freqs) \ + static struct dvfs dvfs_init[] = { /* Cpu voltages (mV): 750, 775, 800, 825, 875, 900, 925, 975, 1000, 1050, 1100 */ - CPU_DVFS("cpu", 0, MHZ, 314, 314, 314, 456, 456, 608, 608, 760, 817, 912, 1000), - CPU_DVFS("cpu", 1, MHZ, 314, 314, 314, 456, 456, 618, 618, 770, 827, 922, 1000), - CPU_DVFS("cpu", 2, MHZ, 494, 675, 675, 675, 817, 817, 922, 1000), - CPU_DVFS("cpu", 3, MHZ, 730, 760, 845, 845, 1000), + CPU_DVFS("cpu", 0, MHZ, 314, 314, 314, 456, 456, 608, 608, 760, 817, 912, 1000) + CPU_DVFS("cpu", 1, MHZ, 314, 314, 314, 456, 456, 618, 618, 770, 827, 922, 1000) + CPU_DVFS("cpu", 2, MHZ, 494, 675, 675, 675, 817, 817, 922, 1000) + CPU_DVFS("cpu", 3, MHZ, 730, 760, 845, 845, 1000) /* Core voltages (mV): 950, 1000, 1100, 1200, 1275 */ @@ -90,22 +110,22 @@ static struct dvfs dvfs_init[] = { * For now, boards must ensure that the core voltage does not drop * below 1V, or that the sdmmc busses are set to 44 MHz or less. */ - CORE_DVFS("sdmmc1", 1, KHZ, 44000, 52000, 52000, 52000, 52000), - CORE_DVFS("sdmmc2", 1, KHZ, 44000, 52000, 52000, 52000, 52000), - CORE_DVFS("sdmmc3", 1, KHZ, 44000, 52000, 52000, 52000, 52000), - CORE_DVFS("sdmmc4", 1, KHZ, 44000, 52000, 52000, 52000, 52000), + CORE_DVFS("sdmmc1", 1, KHZ, 44000, 52000, 52000, 52000, 52000) + CORE_DVFS("sdmmc2", 1, KHZ, 44000, 52000, 52000, 52000, 52000) + CORE_DVFS("sdmmc3", 1, KHZ, 44000, 52000, 52000, 52000, 52000) + CORE_DVFS("sdmmc4", 1, KHZ, 44000, 52000, 52000, 52000, 52000) #endif - CORE_DVFS("ndflash", 1, KHZ, 130000, 150000, 158000, 164000, 164000), - CORE_DVFS("nor", 1, KHZ, 0, 92000, 92000, 92000, 92000), - CORE_DVFS("ide", 1, KHZ, 0, 0, 100000, 100000, 100000), - CORE_DVFS("mipi", 1, KHZ, 0, 40000, 40000, 40000, 60000), - CORE_DVFS("usbd", 1, KHZ, 0, 0, 480000, 480000, 480000), - CORE_DVFS("usb2", 1, KHZ, 0, 0, 480000, 480000, 480000), - CORE_DVFS("usb3", 1, KHZ, 0, 0, 480000, 480000, 480000), - CORE_DVFS("pcie", 1, KHZ, 0, 0, 0, 250000, 250000), - CORE_DVFS("dsi", 1, KHZ, 100000, 100000, 100000, 500000, 500000), - CORE_DVFS("tvo", 1, KHZ, 0, 0, 0, 250000, 250000), + CORE_DVFS("ndflash", 1, KHZ, 130000, 150000, 158000, 164000, 164000) + CORE_DVFS("nor", 1, KHZ, 0, 92000, 92000, 92000, 92000) + CORE_DVFS("ide", 1, KHZ, 0, 0, 100000, 100000, 100000) + CORE_DVFS("mipi", 1, KHZ, 0, 40000, 40000, 40000, 60000) + CORE_DVFS("usbd", 1, KHZ, 0, 0, 480000, 480000, 480000) + CORE_DVFS("usb2", 1, KHZ, 0, 0, 480000, 480000, 480000) + CORE_DVFS("usb3", 1, KHZ, 0, 0, 480000, 480000, 480000) + CORE_DVFS("pcie", 1, KHZ, 0, 0, 0, 250000, 250000) + CORE_DVFS("dsi", 1, KHZ, 100000, 100000, 100000, 500000, 500000) + CORE_DVFS("tvo", 1, KHZ, 0, 0, 0, 250000, 250000) /* * The clock rate for the display controllers that determines the @@ -113,24 +133,24 @@ static struct dvfs dvfs_init[] = { * to the display block. Disable auto-dvfs on the display clocks, * and let the display driver call tegra_dvfs_set_rate manually */ - CORE_DVFS("disp1", 0, KHZ, 158000, 158000, 190000, 190000, 190000), - CORE_DVFS("disp2", 0, KHZ, 158000, 158000, 190000, 190000, 190000), - CORE_DVFS("hdmi", 0, KHZ, 0, 0, 0, 148500, 148500), + CORE_DVFS("disp1", 0, KHZ, 158000, 158000, 190000, 190000, 190000) + CORE_DVFS("disp2", 0, KHZ, 158000, 158000, 190000, 190000, 190000) + CORE_DVFS("hdmi", 0, KHZ, 0, 0, 0, 148500, 148500) /* * These clocks technically depend on the core process id, * but just use the worst case value for now */ - CORE_DVFS("host1x", 1, KHZ, 104500, 133000, 166000, 166000, 166000), - CORE_DVFS("epp", 1, KHZ, 133000, 171000, 247000, 300000, 300000), - CORE_DVFS("2d", 1, KHZ, 133000, 171000, 247000, 300000, 300000), - CORE_DVFS("3d", 1, KHZ, 114000, 161500, 247000, 300000, 300000), - CORE_DVFS("mpe", 1, KHZ, 104500, 152000, 228000, 250000, 250000), - CORE_DVFS("vi", 1, KHZ, 85000, 100000, 150000, 150000, 150000), - CORE_DVFS("sclk", 1, KHZ, 95000, 133000, 190000, 250000, 250000), - CORE_DVFS("vde", 1, KHZ, 95000, 123500, 209000, 250000, 250000), + CORE_DVFS("host1x", 1, KHZ, 104500, 133000, 166000, 166000, 166000) + CORE_DVFS("epp", 1, KHZ, 133000, 171000, 247000, 300000, 300000) + CORE_DVFS("2d", 1, KHZ, 133000, 171000, 247000, 300000, 300000) + CORE_DVFS("3d", 1, KHZ, 114000, 161500, 247000, 300000, 300000) + CORE_DVFS("mpe", 1, KHZ, 104500, 152000, 228000, 250000, 250000) + CORE_DVFS("vi", 1, KHZ, 85000, 100000, 150000, 150000, 150000) + CORE_DVFS("sclk", 1, KHZ, 95000, 133000, 190000, 250000, 250000) + CORE_DVFS("vde", 1, KHZ, 95000, 123500, 209000, 250000, 250000) /* What is this? */ - CORE_DVFS("NVRM_DEVID_CLK_SRC", 1, MHZ, 480, 600, 800, 1067, 1067), + CORE_DVFS("NVRM_DEVID_CLK_SRC", 1, MHZ, 480, 600, 800, 1067, 1067) }; void __init tegra2_init_dvfs(void) -- 2.34.1