From 5e11a083b9ad18852bababbc0c82b3600bf1e309 Mon Sep 17 00:00:00 2001 From: chenxing Date: Sat, 10 Aug 2013 11:02:22 +0800 Subject: [PATCH] rk3066B: fix ddr pll do not update msg in clock tree display --- arch/arm/mach-rk30/clock_data-rk3066b.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-rk30/clock_data-rk3066b.c b/arch/arm/mach-rk30/clock_data-rk3066b.c index 008abcc3b9c1..bb7e740fad8c 100755 --- a/arch/arm/mach-rk30/clock_data-rk3066b.c +++ b/arch/arm/mach-rk30/clock_data-rk3066b.c @@ -1153,7 +1153,12 @@ static long ddr_clk_round_rate(struct clk *clk, unsigned long rate) static unsigned long ddr_clk_recalc_rate(struct clk *clk) { u32 shift = get_cru_bits(clk->clksel_con, clk->div_mask, clk->div_shift); - unsigned long rate = clk->parent->recalc(clk->parent) >> shift; + unsigned long rate = 0; + + clk->parent = clk->get_parent(clk); + clk->parent->rate = clk->parent->recalc(clk->parent); + rate = clk->parent->rate >> shift; + pr_debug("%s new clock rate is %lu (shift %u)\n", clk->name, rate, shift); return rate; } @@ -1161,6 +1166,8 @@ static struct clk *clk_ddr_parents[2] = {&ddr_pll_clk, &general_pll_clk}; static struct clk clk_ddr = { .name = "ddr", .parent = &ddr_pll_clk, + .get_parent = clksel_get_parent, + .set_parent = clksel_set_parent, .recalc = ddr_clk_recalc_rate, .set_rate = ddr_clk_set_rate, .round_rate = ddr_clk_round_rate, -- 2.34.1