From 5ed7eccb31a748046dfa4bbe1d06571285d6b510 Mon Sep 17 00:00:00 2001 From: =?utf8?q?=E9=BB=84=E6=B6=9B?= Date: Mon, 11 Jul 2011 20:26:15 +0800 Subject: [PATCH] rk29: L2 Data RAM latency set to 4 cycles, Tag RAM latency set to 3 cycles, suggested by zcs --- arch/arm/mm/proc-v7.S | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index f5e368dc0912..9b26be949ef2 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -271,8 +271,8 @@ __v7_setup: bic r5, r5, #1 << 29 @ L2 data RAM read multiplexer select: 0 = two cycles bic r5, r5, #7 << 6 bic r5, r5, #15 - orr r5, r5, #3 << 6 @ Tag RAM latency: b011 = 4 cycles - orr r5, r5, #4 @ Data RAM latency: b0100 = 5 cycles + orr r5, r5, #2 << 6 @ Tag RAM latency: b010 = 3 cycles + orr r5, r5, #3 @ Data RAM latency: b0011 = 4 cycles mcr p15, 1, r5, c9, c0, 2 #endif -- 2.34.1