From 6023ad2d3700ba00420f26221c782cb728686644 Mon Sep 17 00:00:00 2001 From: Michael Zolotukhin Date: Fri, 6 Mar 2015 01:13:01 +0000 Subject: [PATCH] LegalizeTypes: Handle shift by 0 in ExpandShiftByConstant. Though such shifts are usually optimized away by combiner, we still can encounter them after a vector shift is legalized. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231443 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp | 9 ++++++++- test/CodeGen/X86/vec_shift7.ll | 12 ++++++++++++ 2 files changed, 20 insertions(+), 1 deletion(-) create mode 100644 test/CodeGen/X86/vec_shift7.ll diff --git a/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp b/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp index 68ddb9e985d..25e80b9c736 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp +++ b/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp @@ -1333,12 +1333,19 @@ std::pair DAGTypeLegalizer::ExpandAtomic(SDNode *Node) { /// and the shift amount is a constant 'Amt'. Expand the operation. void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, unsigned Amt, SDValue &Lo, SDValue &Hi) { - assert(Amt && "Expected zero shifts to be already optimized away."); SDLoc DL(N); // Expand the incoming operand to be shifted, so that we have its parts SDValue InL, InH; GetExpandedInteger(N->getOperand(0), InL, InH); + // Though Amt shouldn't usually be 0, it's possible. E.g. when legalization + // splitted a vector shift, like this: SHL <0, 2>. + if (!Amt) { + Lo = InL; + Hi = InH; + return; + } + EVT NVT = InL.getValueType(); unsigned VTBits = N->getValueType(0).getSizeInBits(); unsigned NVTBits = NVT.getSizeInBits(); diff --git a/test/CodeGen/X86/vec_shift7.ll b/test/CodeGen/X86/vec_shift7.ll new file mode 100644 index 00000000000..cdf828976be --- /dev/null +++ b/test/CodeGen/X86/vec_shift7.ll @@ -0,0 +1,12 @@ +; RUN: llc < %s -march=x86 -mcpu=yonah | FileCheck %s + + +; Verify that we don't fail when shift by zero is encountered. + +define i64 @test1(<2 x i64> %a) { +entry: + %c = shl <2 x i64> %a, + %d = extractelement <2 x i64> %c, i32 0 + ret i64 %d +} +; CHECK-LABEL: test1 -- 2.34.1