From 61cc47e15d1899dac5b2633b2e13f9fcd04d3ce9 Mon Sep 17 00:00:00 2001 From: Eli Friedman Date: Tue, 26 Jul 2011 21:02:58 +0000 Subject: [PATCH] Prevent x86-specific DAGCombine from creating nodes with illegal type (which could not be selected). Fixes a minor isel issue that was breaking the testcase from r136130. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136148 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/X86/X86ISelLowering.cpp | 3 ++- test/CodeGen/X86/split-vector-bitcast.ll | 3 +-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index 2c62b93f7bd..1c87f14ad45 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -4520,7 +4520,8 @@ static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl &Elts, LDBase->getPointerInfo(), LDBase->isVolatile(), LDBase->isNonTemporal(), LDBase->getAlignment()); - } else if (NumElems == 4 && LastLoadedElt == 1) { + } else if (NumElems == 4 && LastLoadedElt == 1 && + DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) { SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other); SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() }; SDValue ResNode = DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, diff --git a/test/CodeGen/X86/split-vector-bitcast.ll b/test/CodeGen/X86/split-vector-bitcast.ll index 79cc1202dc1..fae15cfaf26 100644 --- a/test/CodeGen/X86/split-vector-bitcast.ll +++ b/test/CodeGen/X86/split-vector-bitcast.ll @@ -1,7 +1,6 @@ ; RUN: llc < %s -march=x86 -mattr=-sse2,+sse | grep addps -; XFAIL: * -; PR10497 +; PR10497 + another isel issue with sse2 disabled ; (This is primarily checking that this construct doesn't crash.) define void @a(<2 x float>* %a, <2 x i32>* %b) { %cc = load <2 x float>* %a -- 2.34.1