From 625763c2ebb68aa6c7b9ccdcc1bf6c13f48a2f36 Mon Sep 17 00:00:00 2001
From: =?utf8?q?=E9=BB=84=E6=B6=9B?= <huangtao@rock-chips.com>
Date: Fri, 13 Dec 2013 17:19:07 +0800
Subject: [PATCH] ARM: rockchip: l2 and cpu_axi_bus DT add rockchip prefix

---
 arch/arm/boot/dts/rk3188.dtsi   | 48 ++++++++++++++++-----------------
 arch/arm/mach-rockchip/common.c | 16 +++++------
 2 files changed, 32 insertions(+), 32 deletions(-)

diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi
index b3058e96d028..caeebda54cf4 100755
--- a/arch/arm/boot/dts/rk3188.dtsi
+++ b/arch/arm/boot/dts/rk3188.dtsi
@@ -61,9 +61,9 @@
 		cache-level = <2>;
 		arm,tag-latency = <1 1 1>;
 		arm,data-latency = <2 3 1>;
-		prefetch-ctrl = <0x70000003>;
+		rockchip,prefetch-ctrl = <0x70000003>;
 		/* L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN */
-		power-ctrl = <0x3>;
+		rockchip,power-ctrl = <0x3>;
 /*
 		(0x1 << 0) |	// Full line of write zero behavior Enabled
 		(0x1 << 25) | 	// Round-robin replacement
@@ -71,7 +71,7 @@
 		(0x1 << L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT) |
 		(0x1 << L2X0_AUX_CTRL_EARLY_BRESP_SHIFT)
 */
-		aux-ctrl = <0x72000001 (~0x72000001)>;
+		rockchip,aux-ctrl = <0x72000001 (~0x72000001)>;
 	};
 
 	cpu_axi_bus: cpu_axi_bus@10128000 {
@@ -79,51 +79,51 @@
 		reg = <0x10128000 0x8000>;
 		qos {
 			dmac {
-				offset = <0x1000>;
-				priority = <0 0>;
+				rockchip,offset = <0x1000>;
+				rockchip,priority = <0 0>;
 			};
 			cpu0 {
-				offset = <0x2000>;
-				priority = <0 0>;
+				rockchip,offset = <0x2000>;
+				rockchip,priority = <0 0>;
 			};
 			cpu1r {
-				offset = <0x2080>;
-				priority = <0 0>;
+				rockchip,offset = <0x2080>;
+				rockchip,priority = <0 0>;
 			};
 			cpu1w {
-				offset = <0x2100>;
-				priority = <0 0>;
+				rockchip,offset = <0x2100>;
+				rockchip,priority = <0 0>;
 			};
 			peri {
-				offset = <0x4000>;
-				priority = <2 2>;
+				rockchip,offset = <0x4000>;
+				rockchip,priority = <2 2>;
 			};
 			gpu {
-				offset = <0x5000>;
-				priority = <2 1>;
+				rockchip,offset = <0x5000>;
+				rockchip,priority = <2 1>;
 			};
 			vpu {
-				offset = <0x6000>;
+				rockchip,offset = <0x6000>;
 			};
 			vop0 {
-				offset = <0x7000>;
-				priority = <3 3>;
+				rockchip,offset = <0x7000>;
+				rockchip,priority = <3 3>;
 			};
 			cif0 {
-				offset = <0x7080>;
+				rockchip,offset = <0x7080>;
 			};
 			ipp {
-				offset = <0x7100>;
+				rockchip,offset = <0x7100>;
 			};
 			vop1 {
-				offset = <0x7180>;
-				priority = <3 3>;
+				rockchip,offset = <0x7180>;
+				rockchip,priority = <3 3>;
 			};
 			cif1 {
-				offset = <0x7200>;
+				rockchip,offset = <0x7200>;
 			};
 			rga {
-				offset = <0x7280>;
+				rockchip,offset = <0x7280>;
 			};
 		};
 	};
diff --git a/arch/arm/mach-rockchip/common.c b/arch/arm/mach-rockchip/common.c
index 83ab47f9808b..93a9b4cb641f 100644
--- a/arch/arm/mach-rockchip/common.c
+++ b/arch/arm/mach-rockchip/common.c
@@ -36,23 +36,23 @@ static int __init rockchip_cpu_axi_init(void)
 	if (np) {
 		for_each_child_of_node(np, cp) {
 			u32 offset, priority[2], mode, bandwidth, saturation;
-			if (of_property_read_u32(cp, "offset", &offset))
+			if (of_property_read_u32(cp, "rockchip,offset", &offset))
 				continue;
 			pr_debug("qos: %s offset %x\n", cp->name, offset);
 			cbase = base + offset;
-			if (!of_property_read_u32_array(cp, "priority", priority, ARRAY_SIZE(priority))) {
+			if (!of_property_read_u32_array(cp, "rockchip,priority", priority, ARRAY_SIZE(priority))) {
 				CPU_AXI_SET_QOS_PRIORITY(priority[0], priority[1], cbase);
 				pr_debug("qos: %s priority %x %x\n", cp->name, priority[0], priority[1]);
 			}
-			if (!of_property_read_u32(cp, "mode", &mode)) {
+			if (!of_property_read_u32(cp, "rockchip,mode", &mode)) {
 				CPU_AXI_SET_QOS_MODE(mode, cbase);
 				pr_debug("qos: %s mode %x\n", cp->name, mode);
 			}
-			if (!of_property_read_u32(cp, "bandwidth", &bandwidth)) {
+			if (!of_property_read_u32(cp, "rockchip,bandwidth", &bandwidth)) {
 				CPU_AXI_SET_QOS_BANDWIDTH(bandwidth, cbase);
 				pr_debug("qos: %s bandwidth %x\n", cp->name, bandwidth);
 			}
-			if (!of_property_read_u32(cp, "saturation", &saturation)) {
+			if (!of_property_read_u32(cp, "rockchip,saturation", &saturation)) {
 				CPU_AXI_SET_QOS_SATURATION(saturation, cbase);
 				pr_debug("qos: %s saturation %x\n", cp->name, saturation);
 			}
@@ -87,13 +87,13 @@ static int __init rockchip_pl330_l2_cache_init(void)
 	if (!base)
 		return -EINVAL;
 
-	if (!of_property_read_u32(np, "prefetch-ctrl", &prefetch)) {
+	if (!of_property_read_u32(np, "rockchip,prefetch-ctrl", &prefetch)) {
 		/* L2X0 Prefetch Control */
 		writel_relaxed(prefetch, base + L2X0_PREFETCH_CTRL);
 		pr_debug("l2c: prefetch %x\n", prefetch);
 	}
 
-	if (!of_property_read_u32(np, "power-ctrl", &power)) {
+	if (!of_property_read_u32(np, "rockchip,power-ctrl", &power)) {
 		/* L2X0 Power Control */
 		writel_relaxed(power, base + L2X0_POWER_CTRL);
 		pr_debug("l2c: power %x\n", power);
@@ -101,7 +101,7 @@ static int __init rockchip_pl330_l2_cache_init(void)
 
 	iounmap(base);
 
-	of_property_read_u32_array(np, "aux-ctrl", aux, ARRAY_SIZE(aux));
+	of_property_read_u32_array(np, "rockchip,aux-ctrl", aux, ARRAY_SIZE(aux));
 	pr_debug("l2c: aux %08x mask %08x\n", aux[0], aux[1]);
 
 	l2x0_of_init(aux[0], aux[1]);
-- 
2.34.1