From 62b9c33e13feb8f5567cc633cd1c12639cc620b1 Mon Sep 17 00:00:00 2001
From: Colin LeMahieu <colinl@codeaurora.org>
Date: Wed, 21 Jan 2015 18:13:15 +0000
Subject: [PATCH] [Hexagon] Converting multiply and accumulate with immediate
 intrinsics to patterns.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226681 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Target/Hexagon/HexagonIntrinsics.td    |  21 ++++
 test/CodeGen/Hexagon/intrinsics-mpy-acc.ll | 120 +++++++++++++++++++++
 2 files changed, 141 insertions(+)
 create mode 100644 test/CodeGen/Hexagon/intrinsics-mpy-acc.ll

diff --git a/lib/Target/Hexagon/HexagonIntrinsics.td b/lib/Target/Hexagon/HexagonIntrinsics.td
index 25618c5f3cb..f58e7655ed1 100644
--- a/lib/Target/Hexagon/HexagonIntrinsics.td
+++ b/lib/Target/Hexagon/HexagonIntrinsics.td
@@ -53,6 +53,10 @@ class T_QIR_pat <InstHexagon MI, Intrinsic IntID, PatFrag ImmPred>
   : Pat <(IntID (i32 PredRegs:$Ps), ImmPred:$Is, I32:$Rs),
          (MI PredRegs:$Ps, ImmPred:$Is, I32:$Rs)>;
 
+class T_RRI_pat <InstHexagon MI, Intrinsic IntID>
+  : Pat <(IntID I32:$Rs, I32:$Rt, imm:$Iu),
+         (MI I32:$Rs, I32:$Rt, imm:$Iu)>;
+
 class T_RRR_pat <InstHexagon MI, Intrinsic IntID>
   : Pat <(IntID I32:$Rs, I32:$Rt, I32:$Ru),
          (MI I32:$Rs, I32:$Rt, I32:$Ru)>;
@@ -333,6 +337,23 @@ def: T_PP_pat<A2_xorp,     int_hexagon_A2_xorp>;
 def: T_PP_pat<S2_parityp,  int_hexagon_S2_parityp>;
 def: T_RR_pat<S2_packhl,   int_hexagon_S2_packhl>;
 
+// Multiply 32x32 and use lower result
+def : T_RRI_pat <M2_macsip, int_hexagon_M2_macsip>;
+def : T_RRI_pat <M2_macsin, int_hexagon_M2_macsin>;
+def : T_RRR_pat <M2_maci, int_hexagon_M2_maci>;
+
+// Subtract and accumulate
+def : T_RRR_pat <M2_subacc, int_hexagon_M2_subacc>;
+
+// Add and accumulate
+def : T_RRR_pat <M2_acci,   int_hexagon_M2_acci>;
+def : T_RRR_pat <M2_nacci,  int_hexagon_M2_nacci>;
+def : T_RRI_pat <M2_accii,  int_hexagon_M2_accii>;
+def : T_RRI_pat <M2_naccii, int_hexagon_M2_naccii>;
+
+// XOR and XOR with destination
+def : T_RRR_pat <M2_xor_xacc, int_hexagon_M2_xor_xacc>;
+
 //
 // ALU 32 types.
 //
diff --git a/test/CodeGen/Hexagon/intrinsics-mpy-acc.ll b/test/CodeGen/Hexagon/intrinsics-mpy-acc.ll
new file mode 100644
index 00000000000..a1639aabf13
--- /dev/null
+++ b/test/CodeGen/Hexagon/intrinsics-mpy-acc.ll
@@ -0,0 +1,120 @@
+; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s
+
+; Verify that the mpy intrinsics with add/subtract are being lowered to the right instruction.
+
+@c = external global i64
+
+; CHECK: r{{[0-9]+}}{{ *}}+{{ *}}={{ *}}mpyi(r{{[0-9]+}}{{ *}},{{ *}}#124)
+
+define void @test1(i32 %a) #0 {
+entry:
+  %0 = load i64* @c, align 8
+  %conv = trunc i64 %0 to i32
+  %1 = tail call i32 @llvm.hexagon.M2.macsip(i32 %conv, i32 %a, i32 124)
+  %conv1 = sext i32 %1 to i64
+  store i64 %conv1, i64* @c, align 8
+  ret void
+}
+
+declare i32 @llvm.hexagon.M2.macsip(i32, i32, i32) #1
+
+; CHECK: r{{[0-9]+}}{{ *}}-{{ *}}={{ *}}mpyi(r{{[0-9]+}}{{ *}},{{ *}}#166)
+
+define void @test2(i32 %a) #0 {
+entry:
+  %0 = load i64* @c, align 8
+  %conv = trunc i64 %0 to i32
+  %1 = tail call i32 @llvm.hexagon.M2.macsin(i32 %conv, i32 %a, i32 166)
+  %conv1 = sext i32 %1 to i64
+  store i64 %conv1, i64* @c, align 8
+  ret void
+}
+
+declare i32 @llvm.hexagon.M2.macsin(i32, i32, i32) #1
+
+; CHECK: r{{[0-9]+}}{{ *}}+{{ *}}={{ *}}mpyi(r{{[0-9]+}}{{ *}},{{ *}}r{{[0-9]+}})
+
+define void @test3(i32 %a, i32 %b) #0 {
+entry:
+  %0 = load i64* @c, align 8
+  %conv = trunc i64 %0 to i32
+  %1 = tail call i32 @llvm.hexagon.M2.maci(i32 %conv, i32 %a, i32 %b)
+  %conv1 = sext i32 %1 to i64
+  store i64 %conv1, i64* @c, align 8
+  ret void
+}
+
+declare i32 @llvm.hexagon.M2.maci(i32, i32, i32) #1
+
+@d = external global i32
+
+; CHECK: r{{[0-9]+}}{{ *}}+{{ *}}={{ *}}add(r{{[0-9]+}}{{ *}},{{ *}}#40)
+
+define void @test7(i32 %a) #0 {
+entry:
+  %0 = load i64* @c, align 8
+  %conv = trunc i64 %0 to i32
+  %1 = tail call i32 @llvm.hexagon.M2.accii(i32 %conv, i32 %a, i32 40)
+  %conv1 = sext i32 %1 to i64
+  store i64 %conv1, i64* @c, align 8
+  ret void
+}
+
+declare i32 @llvm.hexagon.M2.accii(i32, i32, i32) #1
+
+; CHECK: r{{[0-9]+}}{{ *}}-{{ *}}={{ *}}add(r{{[0-9]+}}{{ *}},{{ *}}#100)
+
+define void @test8(i32 %a) #0 {
+entry:
+  %0 = load i64* @c, align 8
+  %conv = trunc i64 %0 to i32
+  %1 = tail call i32 @llvm.hexagon.M2.naccii(i32 %conv, i32 %a, i32 100)
+  %conv1 = sext i32 %1 to i64
+  store i64 %conv1, i64* @c, align 8
+  ret void
+}
+
+declare i32 @llvm.hexagon.M2.naccii(i32, i32, i32) #1
+
+
+; CHECK: r{{[0-9]+}}{{ *}}+{{ *}}={{ *}}add(r{{[0-9]+}}{{ *}},{{ *}}r{{[0-9]+}})
+
+define void @test9(i32 %a, i32 %b) #0 {
+entry:
+  %0 = load i64* @c, align 8
+  %conv = trunc i64 %0 to i32
+  %1 = tail call i32 @llvm.hexagon.M2.acci(i32 %conv, i32 %a, i32 %b)
+  %conv1 = sext i32 %1 to i64
+  store i64 %conv1, i64* @c, align 8
+  ret void
+}
+
+declare i32 @llvm.hexagon.M2.acci(i32, i32, i32) #1
+
+; CHECK: r{{[0-9]+}}{{ *}}+{{ *}}={{ *}}sub(r{{[0-9]+}}{{ *}},{{ *}}r{{[0-9]+}})
+
+define void @test10(i32 %a, i32 %b) #0 {
+entry:
+  %0 = load i64* @c, align 8
+  %conv = trunc i64 %0 to i32
+  %1 = tail call i32 @llvm.hexagon.M2.subacc(i32 %conv, i32 %a, i32 %b)
+  %conv1 = sext i32 %1 to i64
+  store i64 %conv1, i64* @c, align 8
+  ret void
+}
+
+declare i32 @llvm.hexagon.M2.subacc(i32, i32, i32) #1
+
+; CHECK: r{{[0-9]+}}{{ *}}-{{ *}}={{ *}}add(r{{[0-9]+}}{{ *}},{{ *}}r{{[0-9]+}})
+
+define void @test11(i32 %a, i32 %b) #0 {
+entry:
+  %0 = load i64* @c, align 8
+  %conv = trunc i64 %0 to i32
+  %1 = tail call i32 @llvm.hexagon.M2.nacci(i32 %conv, i32 %a, i32 %b)
+  %conv1 = sext i32 %1 to i64
+  store i64 %conv1, i64* @c, align 8
+  ret void
+}
+
+declare i32 @llvm.hexagon.M2.nacci(i32, i32, i32) #1
-- 
2.34.1