From 636a601b70a457a23b06c83ff93fbf0ffa2180e2 Mon Sep 17 00:00:00 2001 From: =?utf8?q?=E9=99=88=E4=BA=AE?= Date: Thu, 3 Jul 2014 22:51:38 -0700 Subject: [PATCH] set screen status before and after ddr change freq MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Signed-off-by: 陈亮 --- arch/arm/mach-rockchip/ddr_rk32.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/mach-rockchip/ddr_rk32.c b/arch/arm/mach-rockchip/ddr_rk32.c index 27367cec5b72..79ff71af6881 100755 --- a/arch/arm/mach-rockchip/ddr_rk32.c +++ b/arch/arm/mach-rockchip/ddr_rk32.c @@ -3748,6 +3748,7 @@ static noinline uint32 ddr_change_freq_sram(void *arg) param.freq = freq; param.freq_slew = freq_slew; param.dqstr_value = dqstr_value; + rk_fb_set_prmry_screen_status(SCREEN_PREPARE_DDR_CHANGE); if (screen.lcdc_id == 0) cru_writel(0 | CRU_W_MSK_SETBITS(0xff, 8, 0xff), RK3288_CRU_CLKSELS_CON(27)); @@ -3765,6 +3766,7 @@ static noinline uint32 ddr_change_freq_sram(void *arg) else if (screen.lcdc_id == 1) cru_writel(0 | CRU_W_MSK_SETBITS(dclk_div, 8, 0xff), RK3288_CRU_CLKSELS_CON(29)); + rk_fb_set_prmry_screen_status(SCREEN_UNPREPARE_DDR_CHANGE); #if defined (DDR_CHANGE_FREQ_IN_LCDC_VSYNC) end: -- 2.34.1