From 64340b93df27c256053ab01a0e5dafabd1fe1d8f Mon Sep 17 00:00:00 2001 From: =?utf8?q?=E9=BB=84=E6=B6=9B?= Date: Wed, 8 Aug 2012 11:25:30 +0800 Subject: [PATCH] rk2928: l2 data ram latency, write 1 cycle, read 3 cycles, setup 2 cycles --- arch/arm/mach-rk2928/common.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-rk2928/common.c b/arch/arm/mach-rk2928/common.c index 5585deb22ce0..1236dca8f1e4 100644 --- a/arch/arm/mach-rk2928/common.c +++ b/arch/arm/mach-rk2928/common.c @@ -49,8 +49,8 @@ static void __init rk2928_l2_cache_init(void) writel_relaxed(L2_LY_SET(1,L2_LY_SP_OFF) |L2_LY_SET(1,L2_LY_RD_OFF) |L2_LY_SET(1,L2_LY_WR_OFF), RK2928_L2C_BASE + L2X0_TAG_LATENCY_CTRL); - writel_relaxed(L2_LY_SET(4,L2_LY_SP_OFF) - |L2_LY_SET(6,L2_LY_RD_OFF) + writel_relaxed(L2_LY_SET(2,L2_LY_SP_OFF) + |L2_LY_SET(3,L2_LY_RD_OFF) |L2_LY_SET(1,L2_LY_WR_OFF), RK2928_L2C_BASE + L2X0_DATA_LATENCY_CTRL); /* L2X0 Prefetch Control */ -- 2.34.1