From 64b639e07082bf6ee7325a3815cda1a7fee52509 Mon Sep 17 00:00:00 2001 From: Wu Liang feng Date: Wed, 17 Aug 2016 14:32:11 +0800 Subject: [PATCH] arm64: dts: rockchip: change dr_mode for rk3399 dwc3 The DesignWare USB3 integrated in rockchip SoCs is a configurable IP Core which can be instantiated as Dual-Role Device (DRD), Host Only (XHCI) and Peripheral Only configurations. For rk3399, it has two DWC3 controllers, we set DRD for DWC3_0 and Host only for DWC3_1 by default. Change-Id: Ia0063e04e48770d8d0ec7ec86cb621c5e9979fb9 Signed-off-by: Wu Liang feng --- arch/arm64/boot/dts/rockchip/rk3399-android.dtsi | 4 ---- arch/arm64/boot/dts/rockchip/rk3399.dtsi | 2 +- 2 files changed, 1 insertion(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-android.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-android.dtsi index a5911c8ed015..9dec42dad55e 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-android.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-android.dtsi @@ -460,10 +460,6 @@ }; }; -&usbdrd_dwc3_0 { - dr_mode = "peripheral"; -}; - &pinctrl { isp { cif_clkout: cif-clkout { diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index 634ca036e25a..020996bb185e 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -480,7 +480,7 @@ compatible = "snps,dwc3"; reg = <0x0 0xfe900000 0x0 0x100000>; interrupts = ; - dr_mode = "otg"; + dr_mode = "host"; phys = <&u2phy1_otg>, <&tcphy1 1>; phy-names = "usb2-phy", "usb3-phy"; phy_type = "utmi_wide"; -- 2.34.1