From 64fddf4e59dfc3e3e4c8c341a3523869ac587652 Mon Sep 17 00:00:00 2001 From: dkl Date: Tue, 13 May 2014 14:21:45 +0800 Subject: [PATCH] clk: rk3288: keep arm_gpll enable when rk3288 apll set_rate --- drivers/clk/rockchip/clk-pll.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c index 51c10fd440d6..7a1b76ce6cb1 100644 --- a/drivers/clk/rockchip/clk-pll.c +++ b/drivers/clk/rockchip/clk-pll.c @@ -1152,7 +1152,7 @@ static int clk_pll_set_rate_3288_apll(struct clk_hw *hw, unsigned long rate, goto CHANGE_APLL; } -#if 1 +#if 0 if (clk_prepare(arm_gpll)) { clk_err("fail to prepare arm_gpll path\n"); clk_unprepare(arm_gpll); @@ -1246,8 +1246,8 @@ CHANGE_APLL: if (sel_gpll) { sel_gpll = 0; - clk_disable(arm_gpll); - clk_unprepare(arm_gpll); + //clk_disable(arm_gpll); + //clk_unprepare(arm_gpll); } //clk_debug("apll set loops_per_jiffy =%lu\n", loops_per_jiffy); -- 2.34.1