From 65c58daa8b8985d2116216043103009815a55e77 Mon Sep 17 00:00:00 2001 From: Jim Grosbach Date: Thu, 8 Oct 2009 01:46:59 +0000 Subject: [PATCH] Re-enable register scavenging in Thumb1 by default. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83521 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/Target/TargetRegisterInfo.h | 6 ++ lib/CodeGen/PrologEpilogInserter.cpp | 11 +--- lib/CodeGen/PrologEpilogInserter.h | 5 ++ lib/Target/ARM/Thumb1RegisterInfo.cpp | 73 +++--------------------- lib/Target/ARM/Thumb1RegisterInfo.h | 1 + 5 files changed, 22 insertions(+), 74 deletions(-) diff --git a/include/llvm/Target/TargetRegisterInfo.h b/include/llvm/Target/TargetRegisterInfo.h index e2a02fd2cb3..390b95fbe2f 100644 --- a/include/llvm/Target/TargetRegisterInfo.h +++ b/include/llvm/Target/TargetRegisterInfo.h @@ -561,6 +561,12 @@ public: return false; } + /// requiresFrameIndexScavenging - returns true if the target requires post + /// PEI scavenging of registers for materializing frame index constants. + virtual bool requiresFrameIndexScavenging(const MachineFunction &MF) const { + return false; + } + /// hasFP - Return true if the specified function should have a dedicated /// frame pointer register. For most targets this is true only if the function /// has variable sized allocas or if frame pointer elimination is disabled. diff --git a/lib/CodeGen/PrologEpilogInserter.cpp b/lib/CodeGen/PrologEpilogInserter.cpp index 9e8c8c256a4..d9b01d0b266 100644 --- a/lib/CodeGen/PrologEpilogInserter.cpp +++ b/lib/CodeGen/PrologEpilogInserter.cpp @@ -44,16 +44,6 @@ char PEI::ID = 0; static RegisterPass X("prologepilog", "Prologue/Epilogue Insertion"); -// FIXME: For now, the frame index scavenging is off by default and only -// used by the Thumb1 target. When it's the default and replaces the current -// on-the-fly PEI scavenging for all targets, requiresRegisterScavenging() -// will replace this. -cl::opt -FrameIndexVirtualScavenging("enable-frame-index-scavenging", - cl::Hidden, - cl::desc("Enable frame index elimination with" - "virtual register scavenging")); - /// createPrologEpilogCodeInserter - This function returns a pass that inserts /// prolog and epilog code, and eliminates abstract frame references. /// @@ -66,6 +56,7 @@ bool PEI::runOnMachineFunction(MachineFunction &Fn) { const Function* F = Fn.getFunction(); const TargetRegisterInfo *TRI = Fn.getTarget().getRegisterInfo(); RS = TRI->requiresRegisterScavenging(Fn) ? new RegScavenger() : NULL; + FrameIndexVirtualScavenging = TRI->requiresFrameIndexScavenging(Fn); // Get MachineModuleInfo so that we can track the construction of the // frame. diff --git a/lib/CodeGen/PrologEpilogInserter.h b/lib/CodeGen/PrologEpilogInserter.h index 1dccfd3c43f..931f1eb231b 100644 --- a/lib/CodeGen/PrologEpilogInserter.h +++ b/lib/CodeGen/PrologEpilogInserter.h @@ -94,6 +94,11 @@ namespace llvm { // functions. bool ShrinkWrapThisFunction; + // Flag to control whether to use the register scavenger to resolve + // frame index materialization registers. Set according to + // TRI->requiresFrameIndexScavenging() for the curren function. + bool FrameIndexVirtualScavenging; + // When using the scavenger post-pass to resolve frame reference // materialization registers, maintain a map of the registers to // the constant value and SP adjustment associated with it. diff --git a/lib/Target/ARM/Thumb1RegisterInfo.cpp b/lib/Target/ARM/Thumb1RegisterInfo.cpp index f07c056a87d..c8a0b15c572 100644 --- a/lib/Target/ARM/Thumb1RegisterInfo.cpp +++ b/lib/Target/ARM/Thumb1RegisterInfo.cpp @@ -37,11 +37,6 @@ #include "llvm/Support/raw_ostream.h" using namespace llvm; -// FIXME: This cmd line option conditionalizes the new register scavenging -// implemenation in PEI. Remove the option when scavenging works well enough -// to be the default. -extern cl::opt FrameIndexVirtualScavenging; - Thumb1RegisterInfo::Thumb1RegisterInfo(const ARMBaseInstrInfo &tii, const ARMSubtarget &sti) : ARMBaseRegisterInfo(tii, sti) { @@ -84,9 +79,16 @@ Thumb1RegisterInfo::getPhysicalRegisterRegClass(unsigned Reg, EVT VT) const { bool Thumb1RegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const { - return FrameIndexVirtualScavenging; + return true; +} + +bool +Thumb1RegisterInfo::requiresFrameIndexScavenging(const MachineFunction &MF) + const { + return true; } + bool Thumb1RegisterInfo::hasReservedCallFrame(MachineFunction &MF) const { const MachineFrameInfo *FFI = MF.getFrameInfo(); unsigned CFSize = FFI->getMaxCallFrameSize(); @@ -128,13 +130,7 @@ void emitThumbRegPlusImmInReg(MachineBasicBlock &MBB, unsigned LdReg = DestReg; if (DestReg == ARM::SP) { assert(BaseReg == ARM::SP && "Unexpected!"); - if (FrameIndexVirtualScavenging) { - LdReg = MF.getRegInfo().createVirtualRegister(ARM::tGPRRegisterClass); - } else { - LdReg = ARM::R3; - BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVtgpr2gpr), ARM::R12) - .addReg(ARM::R3, RegState::Kill); - } + LdReg = MF.getRegInfo().createVirtualRegister(ARM::tGPRRegisterClass); } if (NumBytes <= 255 && NumBytes >= 0) @@ -159,10 +155,6 @@ void emitThumbRegPlusImmInReg(MachineBasicBlock &MBB, else MIB.addReg(LdReg).addReg(BaseReg, RegState::Kill); AddDefaultPred(MIB); - - if (!FrameIndexVirtualScavenging && DestReg == ARM::SP) - BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2tgpr), ARM::R3) - .addReg(ARM::R12, RegState::Kill); } /// calcNumMI - Returns the number of instructions required to materialize @@ -635,7 +627,6 @@ Thumb1RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, else // tLDR has an extra register operand. MI.addOperand(MachineOperand::CreateReg(0, false)); } else if (Desc.mayStore()) { - if (FrameIndexVirtualScavenging) { VReg = MF.getRegInfo().createVirtualRegister(ARM::tGPRRegisterClass); assert (Value && "Frame index virtual allocated, but Value arg is NULL!"); *Value = Offset; @@ -658,52 +649,6 @@ Thumb1RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, MI.addOperand(MachineOperand::CreateReg(FrameReg, false)); else // tSTR has an extra register operand. MI.addOperand(MachineOperand::CreateReg(0, false)); - } else { - // FIXME! This is horrific!!! We need register scavenging. - // Our temporary workaround has marked r3 unavailable. Of course, r3 is - // also a ABI register so it's possible that is is the register that is - // being storing here. If that's the case, we do the following: - // r12 = r2 - // Use r2 to materialize sp + offset - // str r3, r2 - // r2 = r12 - unsigned ValReg = MI.getOperand(0).getReg(); - unsigned TmpReg = ARM::R3; - bool UseRR = false; - if (ValReg == ARM::R3) { - BuildMI(MBB, II, dl, TII.get(ARM::tMOVtgpr2gpr), ARM::R12) - .addReg(ARM::R2, RegState::Kill); - TmpReg = ARM::R2; - } - if (TmpReg == ARM::R3 && AFI->isR3LiveIn()) - BuildMI(MBB, II, dl, TII.get(ARM::tMOVtgpr2gpr), ARM::R12) - .addReg(ARM::R3, RegState::Kill); - if (Opcode == ARM::tSpill) { - if (FrameReg == ARM::SP) - emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg, - Offset, false, TII, *this, dl); - else { - emitLoadConstPool(MBB, II, dl, TmpReg, 0, Offset); - UseRR = true; - } - } else - emitThumbRegPlusImmediate(MBB, II, TmpReg, FrameReg, Offset, TII, - *this, dl); - MI.setDesc(TII.get(ARM::tSTR)); - MI.getOperand(i).ChangeToRegister(TmpReg, false, false, true); - if (UseRR) // Use [reg, reg] addrmode. - MI.addOperand(MachineOperand::CreateReg(FrameReg, false)); - else // tSTR has an extra register operand. - MI.addOperand(MachineOperand::CreateReg(0, false)); - - MachineBasicBlock::iterator NII = next(II); - if (ValReg == ARM::R3) - BuildMI(MBB, NII, dl, TII.get(ARM::tMOVgpr2tgpr), ARM::R2) - .addReg(ARM::R12, RegState::Kill); - if (TmpReg == ARM::R3 && AFI->isR3LiveIn()) - BuildMI(MBB, NII, dl, TII.get(ARM::tMOVgpr2tgpr), ARM::R3) - .addReg(ARM::R12, RegState::Kill); - } } else assert(false && "Unexpected opcode!"); diff --git a/lib/Target/ARM/Thumb1RegisterInfo.h b/lib/Target/ARM/Thumb1RegisterInfo.h index 8d9efd9259c..bb7a6199d10 100644 --- a/lib/Target/ARM/Thumb1RegisterInfo.h +++ b/lib/Target/ARM/Thumb1RegisterInfo.h @@ -41,6 +41,7 @@ public: getPhysicalRegisterRegClass(unsigned Reg, EVT VT = MVT::Other) const; bool requiresRegisterScavenging(const MachineFunction &MF) const; + bool requiresFrameIndexScavenging(const MachineFunction &MF) const; bool hasReservedCallFrame(MachineFunction &MF) const; -- 2.34.1